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An Unbalanced Clock Based Dynamic Comparator: A High-Speed Low-Offset Design Approach for ADC Applications

Varshney, Vikrant · 2019

Abstract

Currently, dynamic comparator approach necessitates in high-speed and power eÿcient analog-to-digital converter applications due to its high latching speed and ultra-low power consumption. In this paper, a novel dynamic comparator is proposed to reduce latch delay and offset. The comparator benefits from add-on cross-coupled transistors in latch structure and unbalanced clocks to enhance comparison speed and to lessen input offset voltage occurred due to mismatch in cross-coupled circuits in latch stage. The derivations for delay and input offset voltage are presented for proposed dynamic comparator with meticulous Monte-Carlo simulations. The results are verified by simulations in CADENCE SPECTRE at 1 V supply voltage and 90 nm CMOS technology. A comparative analysis between the proposed dynamic comparator and the previous reported comparators has been presented. It is observed that the delay is reduced up to 46 % and 6 % as compared to conventional and two phase dynamic comparator, respectively. Moreover, the proposed design consumes 53.36 µW power only. The Monte-Carlo simulation shows that the standard deviation of input offset voltage is 10.8 mV which is 12 % and 77 % of conventional and two phase dynamic comparator, respectively

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An Unbalanced Clock Based Dynamic Comparator: A High-Speed Low-Offset Design Approach for ADC Applications

Author: Varshney, Vikrant
Publisher: Vysoká škola báňská - Technická univerzita Ostrava
Year: 2019
DOI: 10.15598/aeee.v17i4.3326
Source: https://dspace.vsb.cz/bitstreams/263156f6-df80-40c8-9ea9-3a4e2bd49582/download
THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 17 |NUMBER: 4 |2019 |DECEMBER
An Unbalanced Clock Based Dynamic Compa a o :
A High-Speed Low-O se Design App oach o
ADC Applica ions
Vik an VARSHNEY, Rajend a Kuma NAGARIA
Depa men o Elec onics & Communica ion Enginee ing, Mo ilal Neh u Na ional Ins i u e o Technology,
MNNIT Allahabad Campus, Telia ganj, Allahabad, 211004 U a P adesh, India
[email p o ec ed], [email p o ec ed]
DOI: 10.15598/aeee. 17i4.3326
Abs ac . Cu en ly, dynamic compa a o app oach
necessi a es in high-speed and powe e icien analog-
o-digi al con e e applica ions due o i s high la ching
speed and ul a-low powe consump ion. In his pape ,
a no el dynamic compa a o is p oposed o educe la ch
delay and o se . The compa a o bene i s om add-on
c oss-coupled ansis o s in la ch s uc u e and unbal-
anced clocks o enhance compa ison speed and o lessen
inpu o se ol age occu ed due o misma ch in c oss-
coupled ci cui s in la ch s age. The de i a ions o de-
lay and inpu o se ol age a e p esen ed o p oposed
dynamic compa a o wi h me iculous Mon e-Ca lo sim-
ula ions. The esul s a e e i ied by simula ions in CA-
DENCE SPECTRE a 1 V supply ol age and 90 nm
CMOS echnology. A compa a i e analysis be ween he
p oposed dynamic compa a o and he p e ious epo ed
compa a o s has been p esen ed. I is obse ed ha he
delay is educed up o 46 % and 6 % as compa ed o
con en ional and wo phase dynamic compa a o , e-
spec i ely. Mo eo e , he p oposed design consumes
53.36 µW powe only. The Mon e-Ca lo simula ion
shows ha he s anda d de ia ion o inpu o se ol -
age is 10.8 mV which is 12 % and 77 % o con en ional
and wo phase dynamic compa a o , espec i ely.
Keywo ds
Dynamic compa a o , high speed, la ch com-
pa a o , low o se design, unbalanced clock.
1. In oduc ion
Fo pas ew decades, he egene a i e la ch ci cui s in
compa a o s ha e been playing a i al ole as in e ace
be ween digi al and analog signals [1]. I is a main
building block ha is widely used in a a ie y o sys-
ems such as Analog- o-Digi al Con e e s (ADCs) [2],
memo y de ices [3] and [4], Va iable Gain Ampli ie s
(VGAs) [5] o swi ched capaci o ci cui s. High swi ch-
ing speed, low o se [6] and [7] and ene gy e icien [8]
compa a o s ha ing small die a ea a e equi ed o lash
ype ADCs. Bu ade-o be ween speed, o se and
powe makes i challenging o design high speed low o -
se compa a o s [6]. In ecen CMOS p ocesses, high
speed compa a o s su e om low ol age supply in
Ul a-Deep Submic on (UDSM) CMOS echnology be-
cause he h eshold ol age is no scaled in same way
as supply ol age [9], esul ing in limi a ions on ol -
age head oom and common mode inpu ol age ange.
A challenge owa ds high speed low powe compa a o
is inc ease o kickback noise [10] and o se caused by
misma ches due o h eshold ol age, capaci ances, and
cu en ac o s. Thus, his majo h us o design high
pe o mance compa a o s is a huge challenging ask in
ADC design en i onmen .
Compa a o s a e classi ied as s a ic and dynamic de-
pending on he clock signal. S a ic compa a o s [10]
su e om s a ic powe dissipa ion and a e no sui -
able o high speed low powe applica ions. Bes
sui ed compa a o s o high speed ope a ions a e dy-
namic compa a o s ha ing no s a ic powe dissipa-
ion [11]. Howe e , his opology c ea es s acking
e ec and ails o low ol age applica ions because
app op ia e delay ime equi es p ope ol age head-
oom [12]. Many esea che s ha e in oduced a lo o
echniques o design compa a o s such as body d i en
echnique [13], [14] and [15], cha ge s ee ing ech-
nique [16], Ze o-V MOS based echnique [17], o se
cancella ion echnique [15], [18], [19] and [20], sha ed
cha ge me hod [21], and supply ol age boo s apping
and boos ing [22] and [23] me hod o mee he abo e e-
qui emen s. In body-d i en echnique [13], he h esh-
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old ol age equi emen is emo ed due o MOSFET
ope a ion in deple ion mode, bu i su e s om lesse
ans-conduc ance in compa ison o ga e d i en ech-
nique. Also, o bo h PMOS and NMOS ope a ion
in body d i en design, a unique ab ica ion p ocess as
n-well is equi ed. The compa a o , based on Ze o-
V de ices [17] p o ides ail- o- ail inpu ange and
as swi ching a low supply ol age. Howe e , Ze o-
V de ices in many CMOS p ocesses a e no a ailable,
and ab ica e hem physically is impossible. So, abo e
men ioned echniques a e no unswe ing o low ol -
age applica ions in spi e o being e ec i e. To emo e
s acking e ec in [9] and [12], an ex a ci cui y is
added o con en ional compa a o o inc ease speed in
UDSM low ol age supply. In his app oach, addi ional
ci cui y c ea es componen misma ch which should be
conside ed. To o e come all hese challenges, double-
ail wo s age dynamic compa a o s [24], [25] and [26]
comp ising sepa a e ampli ica ion s age and egene a-
i e s age a e p oposed o ene gy e icien and lesse
delay. By including some ex a ci cui y [25], powe
consump ion is educed in he expense o delay and
a ea. To enhance egene a i e speed, a new quasi-
dynamic [8] egene a i e s age is p oposed, bu s a ic
powe dissipa ion occu s in ampli ica ion s age.
A classical single phase compa a o named
as "Lewis-G ay" compa a o was in oduced
in [27] and [28] o explain comp omise in o se ,
delay and powe . I is widely used in ADC sys-
ems [28], he e o e is aken as e e ence in his pape .
I is ully di e en ial dynamic compa a o and consis s
o p e-ampli ie s age and egene a i e la ch s age like
o he single phase compa a o s. When p e-ampli ie
s age de elops su icien ol age di e ence a he
inne nodes o la ch s age, i s a s compa ison and
unc ions p ope ly. In [29], an analysis o inpu o se
ol age shows ha i can be diminished on he cos
o highe powe consump ion. A he egene a ion
phase ampli ica ion o inpu ol ages and egene a ion
o c oss-coupled in e e s occu concu en ly. The e-
o e, ampli ica ion should be quick and su icien o
supp ess o se o c oss-coupled in e e s which leads
o mo e powe consump ion. A he ou pu node,
load capaci ance misma ch again a ec s inpu o se
which needs mo e con olling inpu s age. To b eak
his s alema e be ween powe and o se , a new double
phase based a chi ec u e [30] was in oduced wi h
signi ican lesse inpu o se wi h less powe penal y.
Ne e heless, a penal y on delay occu s.
In his pape , an imp o ed unbalanced clock based
dynamic compa a o has been p oposed in which an ex-
a ci cui y is included in la ch s age as c oss-coupled
ansis o s. Now, ou pu nodes o p e-ampli ie s ages
a e passed o in e media e ansis o s in place o di-
ec connec ed wi h ou pu nodes o la ch s age ha
imp o es he pe o mance o he p oposed compa a o .
A signi ican delay is educed wi hou penal y on o se
and powe consump ion bu on he cos o some a ea
caused by ex a ci cui y. The emnan o his pape is
s uc u ed as ollows: In Sec. 2. , he p oposed com-
pa a o is explained along wi h ma hema ical analysis
o delay and inpu o se . In Sec. 3. , design consid-
e a ions a e explained in which some design issues a e
elabo a ed. Simula ion esul s a e discussed and com-
pa ed wi h pas designs in Sec. 4. whe eas Sec. 5.
concludes he pape .
2. P oposed Compa a o
The p oposed compa a o , shown in Fig. 1, is
composed o wo s ages: 1) p e-ampli ica ion
s age and 2) egene a i e la ch s age. P e-
ampli ica ion s age is o med by ansis o s
M1,M2,M3,M4,M5, and M6, whe e M1&M2
a e inpu ansis o s and es a e con olled by
clock CLK1. Regene a i e la ch s age is o med by
ansis o s M7,M8,M9,M10,M11,M12,MK1, and
MK2, whe e M7/M9&M8/M10 ansis o pai s se
up a la ch oge he and M11 &M12 a e con olled
by clock CLK2. I has been depic ed ha la ch
e ec i e ans-conduc ance, gm,e and di e en ial
ou pu ol age a he s a o compa ison phase, ∆V0
a ec he o al delay ime o compa a o . To enhance
e ec i e ans-conduc ance o la ch s age and la ch
speed, wo in e media e ansis o s MK1&MK2a e
included in la ch s age which in u n enhancing ∆V0
esul ing lowe delay.
VDD
CLK1
CLK1
Vin
+
F+
V e
+
M5
M3
M1
IN1
Vou
+Vou
_
CLK2CLK2
M4
M2
M6
CLK1
CLK1
Vin
_
IN2
VDD
V e
_
F_
VDD
CL
CL
CL, _
IB2
IB1
M8
M7
CL, +MK1MK2
M11 M9M10 M12
Fig. 1: P oposed unbalanced clock based dynamic compa a o .
The wo sepa a e s ages, i.e. egene a i e la ch s age
and p e-ampli ica ion s age unc ion wi h wo clock
pulses CLK1and CLK2indi idually. These clocks aid
he inpu ansis o s o educe he misma ch e ec in
he la ch s age. Thus, he inpu o se ol age o com-
pa a o is educed signi ican ly. This ci cui has less
s acking, so i can ope a e a low supply ol age.
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2.1. Ope a ion o P oposed Ci cui
A chi ec u e
The p oposed compa a o unc ions wi h he h ee
phase ope a ions: p e-cha ge, ampli ica ion and com-
pa ison phase as illus a ed in Fig. 2. Du ing he i s
phase when bo h he clocks CLK1and CLK2a e low,
he ansis o s M3–M4p e-cha ge he nodes F+ and
F−causing MK1–MK2 o be o and M11–M12 an-
sis o s pull he ou pu nodes V+
ou and V−
ou o VDD.
In second phase, CLK1is high, howe e CLK2is
s ill low. Now, he nodes F+ and F−s a o dis-
cha ge and an inpu and e e ence dependen di e en-
ial ol age ∆VF+/F −is de eloped due o di e en ial
cu en p oduced in inpu b anches IN1–IN2. The in-
e media e ansis o s MK1and MK2pass ∆VF+/F −
o c oss-coupled in e e s ha p o ides good shield-
ing be ween inpu and ou pu . Hence, kickback noise
is educed. A su icien di e en ial ol age is de el-
oped a he ou pu nodes o he la ch s age which is
ela ed o di e en ial inpu and e e ence ol ages. The
clock CLK2is se o high du ing hi d phase, esul ing
la ch ci cui s a s o ope a e. The egene a i e loop
o back- o-back in e e s boos s he de eloped di e -
en ial ol age a ou pu nodes. Assuming V+
in > V −
in ,
V+
ou discha ges as e han V−
ou . Consequen ly, when
V+
ou (discha ged by MK1d ain cu en ) alls down o
VDD −|V hp|be o e V−
ou (discha ged by MK2d ain cu -
en ), he co esponding ansis o M10 will be ON in-
s iga ing compa ison phase. V−
ou pulls back o VDD
and V+
ou discha ges o V hp due o PMOS in e media e
ansis o s. I V+
in < V −
in , he ci cui wo ks ice- e sa.
0 . 0 2 0 . 0 4 0 . 0 6 0 . 0 8 0 . 1 0 0 . 1 2 0 . 1 4 0 . 1 6 0 . 1 8 0 . 2 0
0 . 0
0 . 2
0 . 4
0 . 6
0 . 8
1 . 0
1 . 2
d e l a y
a m p
V o l a g e ( V )
T i m e ( n S )
V o u +
V o u -
F +
F -
C L K 1
C L K 2
P e - c h a g e A m p l i i c a i o n C o m p a i s o n
VDD/ 2
Fig. 2: P oposed unbalanced clock based dynamic T ansien
esponse o he p oposed compa a o o he di e -
en ial inpu ol age, ∆Vin = 5 mV, supply ol age,
VDD = 1 V and common mode ol age, VCM =VDD.
2.2. Delay Analysis
In o de o alida e delay educ ion ma hema ically,
he delay equa ions a e de i ed o his p oposed ci -
cui as p esen ed in [21] and [24]. The o al delay con-
sis s wo pa s: ampli ica ion phase du a ion, amp and
egene a i e la ch s age delay, la ch.
delay = amp + la ch.(1)
The delay amp is he ime du a ion in he ampli i-
ca ion phase when he la ch s age load capaci ance
CLa ou pu nodes discha ges un il he i s PMOS
(M9/M10) u ns on. He e, he i s PMOS (M9/M10)
will u n on when i s p eampli ie ou pu node
(F+/F−) will discha ge om VDD o (VDD−V hp) [24].
Thus, CLis discha ged by V hp in amp ime du a ion.
Hence, amp is ob ained as:
amp =CL· {VDD −(VDD − |V hp|)}
IB1
,(2)
amp =CL· |V hp|
IB1
=2CL· |V hp|
I,(3)
whe e IB1is he d ain cu en o MK1. Le , sum o
IB1and IB2cu en s (i.e. IB1+IB2) is equal o o al
supply cu en I, hen IB1can be app oxima ed as hal
o supply cu en I o small di e en ial inpu (∆Vin).
I ∆V0is he ini ial ou pu ol age di e ence a he
beginning o compa ison phase, la ch delay can be ob-
ained om [31]:
la ch =τ·ln 


VDD
2
∆V0

,(4)
whe e τ=CL/gm,e in which gm,e is he e ec i e
ans-conduc ance o he c oss-coupled in e e s. F om
Eq. (4), i is clea ha speed o p oposed compa a o
can be imp o ed by enhancing ∆V0and gm,e .
•Enhancemen in ∆V0: As discussed ea lie , amp
is he ime a e which compa ison phase s a s
and one o he la ch ou pu cha ges back o VDD.
Acco ding o Eq. (4) a his ime amp, di e en ial
ou pu ∆V0has a signi ican impac on la ch ime.
Enhancemen in ∆V0lessens he la ch ime la ch.
F om [24], ∆V0o his compa a o is calcula ed as:
∆V0=|V+
ou ( = amp)−V−
ou ( = amp)|=
=|V hp| − IB2· amp
CL
=
=|V hp| 1−IB2
IB1!,
(5)
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whe e, IB1and IB2a e he d ain cu en s o he
le and igh b anches o he la ch s age. Consid-
e ing ∆IB=|IB1−IB2|=gmK1,2×∆VF+/F −,
Eq. (5) is ew i en as:
∆V0=|V hp|· ∆IB
IB1
≈2|V hp|· gmK1,2×∆VF+/F −
I,
(6)
whe e gmK1,2is he e ec i e ans-conduc ance o
he in e media e PMOS ansis o s MK1and MK2
o la ch s age and ∆VF+/F −is he di e en ial ol -
age o he p e-ampli ie s age ou pu nodes F+
and F−a he ime amp. Bo h hese in luencing
pa ame e s gmK1,2and ∆VF+/F −ampli y ∆V0 e-
sul ing la ch delay educes.
The ol age di e ence a nodes F+/F−a ime
amp,∆VF+/F −can be de e mined as:
∆VF+/F −=|VF+( = amp)−VF−( = amp)|=
= amp ·IN1−IN2
CL,F +(−)
=
= amp ·gm1,2·∆Vin
CL,F +(−)
.
(7)
In his equa ion, IN1and IN2a e he cu -
en s o inpu ansis o s o which di e ence
depends on he inpu ol age di e ence i.e.
∆IB=gm1,2×∆Vin and gm1,2is he ans-
conduc ance o he inpu ansis o s M1/M2. By
subs i u ing Eq. (7) in Eq. (6), we ha e:
∆V0= 2|V hp|
I!2
×CL
CL,F +(−)
×
×gmK1,2×gm1,2×∆Vin.
(8)
•Enhancemen in e ec i e ans-conduc ance: In
p oposed compa a o , i is e iden ha he ou -
pu nodes F+/F−o inpu s age discha ge in de-
cision making phase, ensuing u ns on in e medi-
a e s age ansis o s and s eng hens posi i e eed-
back, hus he e ec i e ans-conduc ance o he
la ch is inc eased i.e. (gm,e +gmK1,2). Hence,
τ=CL
gmK1,2+gm,e
, and:
la ch =CL
(gmK1,2+gm,e )·ln 


VDD
2
∆V0

.(9)
Finally, including e ec s o bo h pa ame e s, he
o al delay o p oposed compa a o is de i ed
om:
delay = la ch + amp =
=2CL· |V hp|
I+CL
(gmK1,2+gm,e )×
ln 




VDD
2
2|V hp|
I2CL
CL,F +(−)
.gmK1,2.gm1,2.∆Vin





.
(10)
F om exp ession de i ed in Eq. (10), i can be
concluded ha o al delay s ongly depends on
inpu ol age di e ence, supply cu en , ans-
conduc ance o inpu and in e media e s age an-
sis o s, and he a io o CLand CL,F +(−). These
pa ame e s educe delay loga i hmically and am-
pli y he whole speed o p oposed compa a o
which can be con i med by he simula ion esul s.
2.3. Misma ch Analysis
In he p oposed compa a o , wo in e media e PMOS
ansis o s (MK1and MK2) a e included wi h wo
phase dynamic compa a o [30], hus misma ch e ec
o h eshold ol age (∆VT hK1,2) and cu en ac o
(∆βK1,2) due o MK1/MK2 ansis o s is conside ed
o inpu o se analysis. Howe e , he h eshold ol -
age and cu en ac o misma ch e ec is insigni ican
in mos cases excep small di e en ial inpu ol age
(∆Vin), whe e ou pu nodes o inpu s age F+and F−
ollows each o he a simila discha ge a e. As a esul ,
he decision making ou come migh be dis u bed due
o he misma ch o in e media e ansis o s. The e-
o e, ollowing wo b ie analysis o misma ch e ec s,
caused by h eshold ol age and cu en ac o , ha e
been conside ed on he inpu o se ol age.
•E ec o Th eshold Vol age Misma ch o MK1and
MK2(∆VT hK1,2): The di e en ial cu en caused
by he MK1/MK2 h eshold misma ch is achie ed
as:
∆IB=gmK1,2×∆VT hK1,2.(11)
Hence, he inpu o se ol age caused by he
MK1/MK2 h eshold misma ch is calcula ed as ol-
lows:
∆Veq,due∆VT hK1,2=CL,F +(−)
amp ·gm1,2
·∆VT hK1,2.(12)
•E ec o Cu en Fac o Misma ch o MK1and
MK2(∆βK1,2): The cu en ac o misma ch o
MK1/MK2can be ob ained as channel leng h mis-
ma ch ∆WK1,2. In o de o ind inpu o se ol -
age due o cu en ac o misma ch, he di e en ial
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cu en in e ms o ∆WK1,2can be w i en as:
∆IB=1
2µp.Cox ·∆WK1,2
L·(VgsK1,2−VT hK1,2)2.
(13)
Hence, he inpu o se ol age caused by he
MK1/MK2cu en ac o misma ch is calcula ed
as ollows:
∆Veq,due∆βK1,2=∆IB·CL,F +(−)
amp ·gmk1,2·gm1,2
=
=0.5µp·Cox ·CL,F +(−)
amp ·gmk1,2·gm1,2
×∆WK1,2
L×
×(VgsK1,2−VT hK1,2)2.
(14)
Thus, he o al inpu o se due o bo h misma ch
ac o s o he in e media e ansis o s MK1/MK2
can be de e mined as:
σ o al =qσ2
∆VT hK1,2+σ2
∆βK1,2.(15)
Exp essions de i ed in Eq. (12) and Eq. (14) con-
clude ha he ans-conduc ance o inpu ansis-
o s (gm1,2) is e ec i e o diminish inpu o se .
So, he size o hese inpu ansis o s is kep usu-
ally la ge in educing he e ec o in e media e
ansis o s misma ch, which esul s in low inpu
o se ol age.
2.4. Kickback Noise
In he egene a i e la ched based dynamic compa a-
o s, he ol age disc epancy a he ou pu nodes, cou-
pled o inpu s age ansis o s, can dis u b he inpu
ol age due o nonze o ou pu impedance. This e ec ,
known as kickback noise, may a ec he compa a o
accu acy. As explained in [10], he high speed and
low powe compa a o s c ea e la ge dis u bance a
he inpu nodes. Hence, i is inescapable in he as
la ching ci cui s. In Fig. 3, he undesi ed peak e o s
a e depic ed in he ansien esponse o inpu ol -
age a ∆Vin = 10 mV. To de e mine kickback noise,
he The enin equi alen o inpu is modeled wi h e-
sis ance o 8 kΩ. Figu e 4 illus a es he peak e o
in he inpu ol age as a unc ion o inpu ol age di -
e ence o h ee di e en s uc u es. The p oposed
compa a o has highe kickback noise han wo phase
dynamic [30] while lowe han con en ional [27]. The
in e media e ansis o s o p oposed ci cui a e no as
obus as la ch o wo phase dynamic. Thus, he size o
hese ansis o s is de e mined in such a way ha he
p oposed ci cui main ains high swi ching speed and
low powe dissipa ion wi h educed kickback noise.
The dis u bance a e e ence ol ages is negligible as
compa ed o inpu s due o low impedance a e e ence
nodes. The main disc epancy occu s du ing ampli i-
ca ion phase when e e ence ol age akes some le el
se ling ime be o e he s a o egene a ion phase. In
some applica ions, in o de o educe he kickback noise
whe e i becomes signi ican , he kickback noise educ-
ion echniques, such as neu aliza ion in [10], can be
applied. The p oposed compa a o is simula ed wi h
neu aliza ion echnique as shown in Fig. 4.
0.5
Di e en ial Inpu Vol age (mV)
Time (ns)
Di e en ial Inpu Vol age (mV)
0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7
-2
-1
0
1
2
3
4
5
6
7
8
9
10
11
Fig. 3: Undesi ed peak e o s in he inpu ol age a
∆Vin = 10 mV and VDD = 1 V.
10
0
10
1
10
2
10
0
10
1
10
2
10
3
Peak Inpu Vol age E o (mV)
Inpu Vol age Di e ence (mV)
Con en ional [27]
Two Phase Dynamic [30]
P oposed
P oposed wi h neu a liza ion
Fig. 4: The plo o measu ed peak e o in inpu ol age due o
kickback noise e sus inpu ol age di e ence a ia ion.
3. Design Conside a ions
In he p oposed s uc u e, he e a e se e al design is-
sues ha mus be conside ed. The sizing o c oss-
coupled PMOS ansis o s MK1/MK2, loca ed be ween
c oss-coupled in e e s o la ch s age, is an impo an
issue o high speed, low ol age, and low o se ope -
a ions. These ansis o s may c ea e he ol age head-
oom p oblem, limi ing he low ol age applica ions. In
c
2019 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 450

THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 17 |NUMBER: 4 |2019 |DECEMBER
o de o o e come his p oblem, MK1/MK2 ansis o s
o low esis ance, i.e. o la ge size, a e equi ed. The
inpu o se migh be a ec ed by he h eshold ol -
age and cu en ac o misma ch be ween MK1/MK2
ansis o s. To diminish his e ec , MK1/MK2 ansis-
o s o la ge ansconduc ance a e equi ed. The e o e,
la ge ansis o s mus be used. Howe e , he la ge size
ansis o s a ec he pa asi ic capaci ances o F+/F−
nodes, CL,F +(−), and esul ing delay bo lenecks. As,
he inc eased pa asi ic capaci ances es ic he speed
o compa a o , he size o he MK1/MK2 ansis o s
is op imally selec ed in such a way ha main ains he
high speed, low ol age, and low o se ope a ions.
In he p oposed compa a o , CLK1and CLK2a e
designed as unbalanced clocks. CLK2is delayed by
∆ ime om CLK1, and ampli ica ion delay ( amp)
depends on his delay ime (∆ ). So, he design o
clock gene a ion ci cui is ano he impo an issue. As
depic ed in Fig. 5(a), he delay o CLK2wi h espec
o CLK1is con olled by a ying Vc l o he cu en
in e e s in he clock bu e s. A small ∆Vin, he com-
pa ison is e y di icul in e alua ion phase. The e-
o e, in ampli ica ion phase, he su icien ampli ica-
ion ime ( amp) is equi ed o de elop he di e en ial
ou pu ol age a he in e nal nodes F+/F −. Thus,
∆ ime is se such ha i is equal o o g ea e han
amp (∆ ≥ amp). I ∆ < amp, i will c ea e he e o
in compa ison phase o small ∆Vin. A highe alues
o ∆ , he inpu o se is educed e ec i ely. Howe e ,
he delay is inc eased apidly. Hence, o main ain he
high speed and low inpu o se , ∆ is kep equal o
o sligh ly g ea e han amp. Fo p oposed ci cui ,
∆ = amp. The concep ual wa e o ms a e shown in
Fig. 5(b).
Vou
Vc l
Vin
CLK1
CLK2
Delayed
byΔ
Cu en In e e
(a)
Δ
amp
F-
F+
VDD
CLK1
CLK2
(b)
Fig. 5: (a) Clock gene a ion ci cui , (b) Concep ual wa e o m.
4. Simula ion Resul s and
Discussion
To compa e he p oposed compa a o wi h exis ing
con en ional [27] and wo phase dynamic compa a-
o [30], he ci cui is designed in CADENCE and
esul s a e simula ed in SPECTRE a 90 nm CMOS
echnology wi h VDD = 1 V, VCM = 0.9V and
∆Vin = 5 mV. Fo ai and au hen ic compa -
ison o simula ion esul s, he designed ci cui s
om [27] and [30] a e simula ed in alike simula ion
en i onmen and amewo k which is used o simu-
la e he p oposed ci cui . Figu e 6 shows he layou
o p oposed ci cui wi h a ea occupancy 64.08 µm2
(9 µm×7.12 µm). The app op ia e cau ion has been
aken in layou design o a oid e ec on powe , o se
and delay. Figu e 7 shows he dependence o delay on
powe supply o p oposed compa a o and esul s a e
compa ed wi h o he wo con igu a ions. I is ob ious
ha speed is signi ican ly enhanced in compa ison o
o he ci cui s. Howe e , delay is highe a low supply
ol ages in espec o highe ol age supplies. The de-
lay a ies om 364.3pS o 221 pS o powe supply
0.7V o 1.2V. Figu e 8 and Fig. 9 demons a e he
a ia ion o TDelay and TLa ch wi h VDD a di e en
alues o di e en ial inpu ol age. The alues o ∆Vin
a e se as 1mV, 5mV, 10 mV, 50 mV and 100 mV.
I is ob ious ha TDelay and TLa ch a pa icula VDD
a e educed as ∆Vin is inc eased. A VDD = 1.1V,
o al delay is d opped om 334.59 pS a ∆Vin = 1 mV
o 168.87 pS a ∆Vin = 100 mV whe eas la ch delay
d ops down om 217.08 pS o 51.36 pS. Also, TDelay
and TLa ch a pa icula ∆Vin a e dec eased as VDD
is inc eased. A ∆Vin = 10 mV, TDelay lessens om
272.28 pS a VDD = 0.7V o 186.46 pS a VDD = 1.2V
and TLa ch om 132.04 pS o 71.33 pS.
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11111111
11111111
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11111111
11111111
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11111111111111111111111111111111111111111111111111111111
11111111111111111111111111111111111111111111111111111111
1111111111111111111111111111111111111111
1111111111111111111111111111111111111111
1111111111111111111111111111111111111111
111111111111111
111111111111111
1111111111111111111111111111111
1111111111111111111111111111111
1111111111111111111111111111111
111
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11111111111111111111
11111111111111111111
1111111111111
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111111111111111111111111111111111111
111111111111111111111111111111111111
11111111111111111111111111111111111111111111111111111111111111111111111111111111
11111111111111111111111111111111111111111111111111111111111111111111111111111111
11111111111111111111111111111111111111111111111111111111111111111111111111111111
11111111111111111111111111111111111111111111
11111111111111111111111111111111111111111111
11111111111111111111111111111111111111111111
11111111111111111
11111111111111111
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1111
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111111
Fig. 6: Layou schema ic diag am o p oposed compa a o
(A ea = 9 µm×7.12 µm).
In Fig. 10, he analy ical ou comes om Eq. (10)
a e compa ed wi h simula ed alues o delay a di e -
en ∆Vin and VCM =VDD −0.1V. The delay calcu-
la ed om analy ical de i a ions shows good ma ching
wi h delay om simula ions. The negligible di e ence
is ound which is due o non-linea second o de e ec s.
These e ec s a e app oxima ed and neglec ed du ing
analy ical de i a ions o delay o con e he complex
exp essions in o simple exp essions.
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2019 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 451
THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 17 |NUMBER: 4 |2019 |DECEMBER
Figu e 11 and Fig. 12 depic he dependency o
TDelay and TLa ch on inpu ol age di e ence and e-
sul s a e compa ed wi h p e ious s uc u es. He e,
∆Vin a ies om 1mV o 30 mV a VDD = 1 V,
VCM = 0.9V and load capaci ance, CLis 5 F.
A ∆Vin = 20 mV, TDelay o p oposed ci cui is
190.63 pS while 298.6pS and 197.67 pS o con en-
ional design and wo phase dynamic ci cui , espec-
i ely. These esul s con i m ha he delay is educed
o p oposed compa a o in compa ison wi h pas com-
pa a o s. Also, a signi ican speed is enhanced com-
pa ed o con en ional ci cui . The eason behind he
speed imp o emen is a boos in ∆V0. As shown in
Fig. 13, ∆V0 a ia ion is ep esen ed wi h ∆Vin. As
∆Vin is inc eased om 1mV o 30 mV, ∆V0ampli-
ies as a small di e en ial inpu and becomes ap-
p oxima ely cons an a highe alues o ∆Vin which
con i ms he delay is educed minimally a la ge al-
ues o ∆Vin. I also depic s ha ∆V0is heigh ened a
pa icula alue o ∆Vin o p oposed con igu a ion as
compa ed o o he s. Fo example, a ∆Vin = 10 mV,
∆V0is boos ed o 353 mV whe eas 136 mV o con en-
ional ci cui . A pa icula alue o CL= 5 F and
VDD = 1 V, ∆V0inc eases by 225 mV, om 190 mV
o 415 mV o ∆Vin a ia ion om 1mV o 30 mV.
0.7 0.8 0.9 1.0 1.1 1.2
200
300
400
500
600
700
800
T
Delay
(pS)
V
DD
(V)
Con en ional [27]
Two Phase Dynamic [30]
P oposed
Fig. 7: To al delay o di e en s uc u es e sus VDD a
∆Vin = 5 mV, VCM =VDD −0.1V.
Figu e 14 ep esen s ha slew a e depends on ∆Vin.
Slew a e inc eases wi h inc emen o ∆Vin and has
la ge alues o p oposed ci cui han o he ci cui s.
The slew a e is de ined as change in ou pu ol age
wi h espec o ime (∆V0/∆ ). I p o es ha slew a e
will be highe a small delay ime. Slew a e a ∆Vin =
5mV is 4.03 V·nS−1which is much g ea e han
2.14 V·nS−1 o con en ional s uc u e. The whole
simula ed esul s conclude ha delay is signi ican ly
educed wi h compa able powe dissipa ion, Pdiss as
shown in Fig. 15. Pdiss a ∆Vin = 10 mV is 44.97 µW
o p oposed which is compa able o 43.79 µW o wo
phase dynamic. Mo eo e , Pdiss is signi ican ly lowe
han ha o con en ional ci cui a e e y pa icula
alue o ∆Vin. Fo example, Pdiss = 53.36 µW a
∆Vin = 5 mV o p oposed, on he con a y, 86.07 µW
o con en ional ci cui . I is ob ious ha speed is
exp essi ely enhanced while consuming almos same
powe . Hence Ene gy Pe Con e sion (EPC) [24] is e-
duced which is de ined as EPC =Pdiss
2ENOB · s
, whe e
ENOB is e ec i e numbe o bi s and sis sampling
equency.
0.7 0.8 0.9 1.0 1.1 1.2
150
200
250
300
350
400
450
500
550
T
Delay
(pS)
V
DD
(V)
V
in
=1mV
V
in
=5mV
V
in
=10mV
V
in
=50mV
V
in
=100mV
Fig. 8: To al delay o p oposed compa a o e sus VDD a a -
ious ∆Vin (VCM =VDD −0.1V).
0.7 0.8 0.9 1.0 1.1 1.2
0
50
100
150
200
250
300
350
400
T
la ch
(pS)
V
DD
(V)
V
in
=1mV
V
in
=5mV
V
in
=10mV
V
in
=50mV
V
in
=100mV
Fig. 9: La ch delay o p oposed compa a o e sus VDD a a -
ious ∆Vin (VCM =VDD −0.1V).
EPC in p oposed ci cui is sligh ly educed in com-
pa ison wi h wo phase dynamic ci cui while an im-
p essi e d op occu s in espec o con en ional ci cui
as shown in Fig. 16. Fo 1bi con e sion, EPC is
dec eased om 13.25 J o 3.4 J a ∆Vin = 5 mV
a e compa ing wi h con en ional s uc u e, on he
con a y, a sligh d op wi h wo phase dynamic om
2.15 J o 1.99 J a ∆Vin = 10 mV. In Tab. 1, he
pe o mance o he p oposed s uc u e has been sum-
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2019 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 452
THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 17 |NUMBER: 4 |2019 |DECEMBER
ma ized. Table 2 includes and e i ies bo h analy ical
analysis and 0.2k Mon e Ca lo simula ed alues o
o se ol age. The e is a small di e ence in calcula ed
and simula ed alues. The o se ol age calcula ed
om analy ical de i a ions is lowe han he simula ed
esul by me iculous 1−σMon e Ca lo simula ions.
The small di e ence is due o he dynamic o se which
is no conside ed in analy ical de i a ions.
0 . 7 0 . 8 0 . 9 1 . 0 1 . 1 1 . 2
150
200
250
300
350
400
450
500
550
600
TD e l a y ( p S )
VDD ( V )
∆Vin = 1 m V ( A n a l y i c a l )
∆Vin = 1 m V ( S im u l a e d )
∆Vin = 5 m V ( A n a l y i c a l )
∆Vi n = 5 m V ( S i m u l a e d )
∆Vi n = 1 0 m V ( A n a l y i c a l )
∆Vi n = 1 0 m V ( S i m u l a e d )
Fig. 10: Ve i ica ion o analy ical analysis wi h simula-
ion esul s o delay a di e en ∆Vin and
VCM =VDD −0.1V.
0 5 10 15 20 25 30
160
240
320
400
480
560
640
720
800
T
Delay
(pS)
V
in
(mV)
Con en ional [27]
Two Phase Dynamic [30]
P oposed
Fig. 11: To al delay o di e en s uc u es e sus ∆Vin a
VDD = 1 V, VCM = 0.9V.
Figu e 17 shows he o se ol age a ia ion o cu -
en p oposed ci cui wi h p e ious con igu a ions a
h ee di e en supply ol ages. By using unbalanced
clock scheme, he inpu o se is educed ema kable
wi h espec o con en ional, and addi ions o in e -
media e ansis o s lessen somewha mo e inpu o -
se ol age, bu keep in mind ha size o hese an-
sis o s should be la ge wi h espec o o he s. A
VDD = 1.2V, he inpu o se ol age (Vos) is 63.85 mV,
11.67 mV and 8.32 mV o con en ional, wo phase
dynamic and p oposed ci cui , espec i ely. A each
poin , he o se esul s a e achie ed using 1−σMon e
Ca lo simula ions a 200 samples un. As shown in
Fig. 18, he s anda d de ia ion o he inpu o se (σos)
o he p oposed ci cui is de i ed o be 10.8mV a
VDD = 1 V using 1−σbased Mon e Ca lo simula-
ions.
0 5 10 15 20 25 30
0
100
200
300
400
500
600
T
La ch
(pS)
V
in
(V)
Con en ional [27]
Two Phase Dynamic [30]
P oposed
Fig. 12: La ch delay o di e en s uc u es e sus ∆Vin a
VDD = 1 V, VCM = 0.9V.
0 5 10 15 20 25 30
0
50
100
150
200
250
300
350
400
450
V
0
(mV)
V
in
(mV)
Con en ional [27]
Two Phase Dynamic [30]
P oposed
Fig. 13: ∆V0(di e en ial ou pu ol age a = amp) o
di e en s uc u es e sus ∆Vin a VDD = 1 V,
VCM = 0.9V.
Table 3 p esen s he co ne analysis o p oposed
compa a o a ∆Vin = 5 mV and VDD = 1 V. Thus,
he p oposed ci cui wo ks p ope ly a di e en co -
ne s. Howe e , he delay is inc eased wi h some ex en
a SS co ne . To d aw a ai compa ison, he p oposed
s uc u e and wo o he s uc u es om [27] and [30]
a e simula ed and compa ed in same simula ion en-
i onmen a 90 nm CMOS echnology as shown in
Tab. 4. The wid h o he MOS ansis o s is se such
ha he op imized alues a e d awn o delay and o -
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2019 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 453
THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 17 |NUMBER: 4 |2019 |DECEMBER
se . Finally, Tab. 5 ela es he pe o mance pa ame e s
o he p oposed s uc u e wi h p e ious wo ks.
Slew Ra e (V nS-
1
)
V
in
(mV)
Con en ional [27]
Two Phase Dynamic [30]
P oposed
.
0 5 10 15 20 25 30
1
2
3
4
5
6
Fig. 14: Slew a e o di e en s uc u es e sus ∆Vin a
VDD = 1 V, VCM = 0.9V.
0 5 10 15 20 25 30
30
40
50
60
70
80
90
100
110
120
130
P
diss
( W)
V
in
(mV)
Con en ional [27]
Two Phase Dynamic [30]
P oposed
Fig. 15: Powe dissipa ion o di e en s uc u es e sus ∆Vin
a VDD = 1 V, VCM = 0.9V.
Tab. 1: P oposed Compa a o Pe o mance Summa y.
Pa ame e s Values
CMOS Technology 90 nm
Supply Vol age 1V
To al Delay, TDelay (VCM = 0.9V, 248.2pS
∆Vin = 5 mV)
La ch Delay, TLa ch 127.53 pS
Di e en ial Ou pu Vol age a amp (∆V0)308 mV
A e age Powe Dissipa ion @ eq. = 0.5GHz 53.36 µW
Maximum Sampling F equency 5.7GHz
Slew Ra e 4.03 V·nS−1
Ene gy Pe Con e sion @ ∆Vin = 5 mV 3.4 J
Inpu O se Vol age (1−σ) (σos)10.8mV
0 5 10 15 20 25 30
0
5
10
15
20
25
30
35
EPC ( J)
V
in
(mV)
Con en ional [27]
Two Phase Dynamic [30]
P oposed
Fig. 16: EPC o di e en s uc u es e sus ∆Vin a
VDD = 1 V, VCM = 0.9V.
0.8V 1V 1.2V
0
20
40
60
80
100
120
140
V
os
(mV)
V
DD
(V)
Con en ional [27]
Two phase dynamic [30]
P oposed
Fig. 17: Inpu o se o di e en s uc u es e sus VDD a
∆Vin = 5 mV, VCM =VDD −0.1V.
Tab. 2: Valida ion o analy ical analysis wi h simula ed alues
o o se ol age.
VDD
∆Vin =1mV ∆Vin =5mV
(V)
Simula ed Analy ical Simula ed Analy ical
Value Value Value Value
(mV) (mV) (mV) (mV)
0.8 12.32 10.95 16.81 15.7
1.0 8.79 7.41 11.56 10.8
1.2 6.98 6.03 9.12 8.32
Tab. 3: Pe o mance summa y o p oposed compa a o a di -
e en co ne s.
Co ne s
Pa ame e s
Delay Powe 1−σO se EPC
(pS) (µW)(mV) ( J)
TT 248.2 53.36 10.8 3.39
FF 212.6 56.94 8.9 3.01
FS 273.8 50.23 13.3 3.47
SF 262.4 51.87 11.7 3.42
SS 325.1 48.35 15.4 3.96
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2019 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 454