An Unbalanced Clock Based Dynamic Comparator: A High-Speed Low-Offset Design Approach for ADC Applications

THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 17 |NUMBER: 4 |2019 |DECEMBER An Unbalanced Clock Based Dynamic Comparator: A High-Speed Low-Offset Design Approach for ADC Applications Vikrant VARSHNEY, Rajendra Kumar NAGARIA Department of Electronics & Communication Engineering, Motilal Nehru National Institute of Technology, MNNIT Allahabad Campus, Teliarganj, Allahabad, 211004 Uttar Pradesh, India [email protected], [email protected] DOI: 10.15598/aeee.v17i4.3326 Abstract. Currently, dynamic comparator approach necessitates in high-speed and power efficient analogto-digital converter applications due to its high latching speed and ultra-low power consumption. In this paper, a novel dynamic comparator is proposed to reduce latch delay and offset. The comparator benefits from add-on cross-coupled transistors in latch structure and unbalanced clocks to enhance comparison speed and to lessen input offset voltage occurred due to mismatch in crosscoupled circuits in latch stage. The derivations for delay and input offset voltage are presented for proposed dynamic comparator with meticulous Monte-Carlo simulations. The results are verified by simulations in CADENCE SPECTRE at 1 V supply voltage and 90 nm CMOS technology. A comparative analysis between the proposed dynamic comparator and the previous reported comparators has been presented. It is observed that the delay is reduced up to 46 % and 6 % as compared to conventional and two phase dynamic comparator, respectively. Moreover, the proposed design consumes 53.36 µW power only. The Monte-Carlo simulation shows that the standard deviation of input offset voltage is 10.8 mV which is 12 % and 77 % of conventional and two phase dynamic comparator, respectively. Keywords Dynamic comparator, high speed, latch comparator, low offset design, unbalanced clock. 1. Introduction For past few decades, the regenerative latch circuits in comparators have been playing a vital role as interface between digital and analog signals [1]. It is a main building block that is widely used in a variety of systems such as Analog-to-Digital Converters (ADCs) [2], memory devices [3] and [4], Variable Gain Amplifiers (VGAs) [5] or switched capacitor circuits. High switching speed, low offset [6] and [7] and energy efficient [8] comparators having small die area are required for flash type ADCs. But trade-off between speed, offset and power makes it challenging to design high speed low offset comparators [6]. In recent CMOS processes, high speed comparators suffer from low voltage supply in Ultra-Deep Submicron (UDSM) CMOS technology because the threshold voltage is not scaled in same way as supply voltage [9], resulting in limitations on voltage headroom and common mode input voltage range. A challenge towards high speed low power comparator is increase of kickback noise [10] and offset caused by mismatches due to threshold voltage, capacitances, and current factors. Thus, this major thrust to design high performance comparators is a huge challenging task in ADC design environment. Comparators are classified as static and dynamic depending on the clock signal. Static comparators [10] suffer from static power dissipation and are not suitable for high speed low power applications. Best suited comparators for high speed operations are dynamic comparators having no static power dissipation [11]. However, this topology creates stacking effect and fails for low voltage applications because appropriate delay time requires proper voltage headroom [12]. Many researchers have introduced a lot of techniques to design comparators such as body driven technique [13], [14] and [15], charge steering technique [16], Zero-VtMOS based technique [17], offset cancellation technique [15], [18], [19] and [20], shared charge method [21], and supply voltage bootstrapping and boosting [22] and [23] method to meet the above requirements. In body-driven technique [13], the threshc 2019 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 446 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 17 |NUMBER: 4 |2019 |DECEMBER old voltage requirement is removed due to MOSFET operation in depletion mode, but it suffers from lesser trans-conductance in comparison of gate driven technique. Also, for both PMOS and NMOS operation in body driven design, a unique fabrication process as n-well is required. The comparator, based on ZeroVtdevices [17] provides rail-to-rail input range and fast switching at low supply voltage. However, ZeroVtdevices in many CMOS processes are not available, and fabricate them physically is impossible. So, above mentioned techniques are not unswerving for low voltage applications in spite of being effective. To remove stacking effect in [9] and [12], an extra circuitry is added to conventional comparator to increase speed in UDSM low voltage supply. In this approach, additional circuitry creates component mismatch which should be considered. To overcome all these challenges, doubletail two stage dynamic comparators [24], [25] and [26] comprising separate amplification stage and regenerative stage are proposed for energy efficient and lesser delay. By including some extra circuitry [25], power consumption is reduced in the expense of delay and area. To enhance regenerative speed, a new quasidynamic [8] regenerative stage is proposed, but static power dissipation occurs in amplification stage. A classical single phase comparator named as "Lewis-Gray" comparator was introduced in [27] and [28] to explain compromise in offset, delay and power. It is widely used in ADC systems [28], therefore is taken as reference in this paper. It is fully differential dynamic comparator and consists of pre-amplifier stage and regenerative latch stage like other single phase comparators. When pre-amplifier stage develops sufficient voltage difference at the inner nodes of latch stage, it starts comparison and functions properly. In [29], an analysis of input offset voltage shows that it can be diminished on the cost of higher power consumption. At the regeneration phase amplification of input voltages and regeneration of cross-coupled inverters occur concurrently. Therefore, amplification should be quick and sufficient to suppress offset of cross-coupled inverters which leads to more power consumption. At the output node, load capacitance mismatch again affects input offset which needs more controlling input stage. To break this stalemate between power and offset, a new double phase based architecture [30] was introduced with significant lesser input offset with less power penalty. Nevertheless, a penalty on delay occurs. In this paper, an improved unbalanced clock based dynamic comparator has been proposed in which an extra circuitry is included in latch stage as cross-coupled transistors. Now, output nodes of pre-amplifier stages are passed to intermediate transistors in place of direct connected with output nodes of latch stage that improves the performance of the proposed comparator. A significant delay is reduced without penalty on offset and power consumption but on the cost of some area caused by extra circuitry. The remnant of this paper is structured as follows: In Sec. 2. , the proposed comparator is explained along with mathematical analysis of delay and input offset. In Sec. 3. , design considerations are explained in which some design issues are elaborated. Simulation results are discussed and compared with past designs in Sec. 4. whereas Sec. 5. concludes the paper. 2. Proposed Comparator The proposed comparator, shown in Fig. 1, is composed of two stages: 1) pre-amplification stage and 2) regenerative latch stage. Preamplification stage is formed by transistors M1,M2,M3,M4,M5, and M6, where M1&M2 are input transistors and rest are controlled by clock CLK1. Regenerative latch stage is formed by transistors M7,M8,M9,M10,M11,M12,MK1, and MK2, where M7/M9&M8/M10 transistor pairs set up a latch together and M11 &M12 are controlled by clock CLK2. It has been depicted that latch effective trans-conductance, gm,eff and differential output voltage at the start of comparison phase, ∆V0 affect the total delay time of comparator. To enhance effective trans-conductance of latch stage and latch speed, two intermediate transistors MK1&MK2are included in latch stage which in turn enhancing ∆V0 resulting lower delay. VDD CLK1 CLK1 Vin + F+ Vref + M5 M3 M1 IN1 Vout +Vout _ CLK2CLK2 M4 M2 M6 CLK1 CLK1 Vin _ IN2 VDD Vref _ F_ VDD CL CL CL,f _ IB2 IB1 M8 M7 CL,f +MK1MK2 M11 M9M10 M12 Fig. 1: Proposed unbalanced clock based dynamic comparator. The two separate stages, i.e. regenerative latch stage and pre-amplification stage function with two clock pulses CLK1and CLK2individually. These clocks aid the input transistors to reduce the mismatch effect in the latch stage. Thus, the input offset voltage of comparator is reduced significantly. This circuit has less stacking, so it can operate at low supply voltage. c 2019 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 447 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 17 |NUMBER: 4 |2019 |DECEMBER 2.1. Operation of Proposed Circuit Architecture The proposed comparator functions with the three phase operations: pre-charge, amplification and comparison phase as illustrated in Fig. 2. During the first phase when both the clocks CLK1and CLK2are low, the transistors M3–M4pre-charge the nodes F+ and F−causing MK1–MK2to be off and M11–M12 transistors pull the output nodes V+ out and V− out to VDD. In second phase, CLK1is high, however CLK2is still low. Now, the nodes F+ and F−start to discharge and an input and reference dependent differential voltage ∆VF+/F −is developed due to differential current produced in input branches IN1–IN2. The intermediate transistors MK1and MK2pass ∆VF+/F − to cross-coupled inverters that provides good shielding between input and output. Hence, kickback noise is reduced. A sufficient differential voltage is developed at the output nodes of the latch stage which is related to differential input and reference voltages. The clock CLK2is set to high during third phase, resulting latch circuit starts to operate. The regenerative loop of back-to-back inverters boosts the developed differential voltage at output nodes. Assuming V+ in > V − in , V+ out discharges faster than V− out. Consequently, when V+ out (discharged by MK1drain current) falls down to VDD −|Vthp|before V− out (discharged by MK2drain current), the corresponding transistor M10 will be ON instigating comparison phase. V− out pulls back to VDD and V+ out discharges to Vthp due to PMOS intermediate transistors. If V+ in < V − in , the circuit works vice-versa. 0 . 0 2 0 . 0 4 0 . 0 6 0 . 0 8 0 . 1 0 0 . 1 2 0 . 1 4 0 . 1 6 0 . 1 8 0 . 2 0 0 . 0 0 . 2 0 . 4 0 . 6 0 . 8 1 . 0 1 . 2 td e l a y ta m p V o l t a g e ( V ) T i m e ( n S ) V o u t + V o u t - F + F - C L K 1 C L K 2 P r e - c h a r g e A m p l i f i c a t i o n C o m p a r i s o n VDD/ 2 Fig. 2: Proposed unbalanced clock based dynamic Transient response of the proposed comparator for the differential input voltage, ∆Vin = 5 mV, supply voltage, VDD = 1 V and common mode voltage, VCM =VDD. 2.2. Delay Analysis In order to validate delay reduction mathematically, the delay equations are derived for this proposed circuit as presented in [21] and [24]. The total delay consists two parts: amplification phase duration, tamp and regenerative latch stage delay, tlatch. tdelay =tamp +tlatch.(1) The delay tamp is the time duration in the amplification phase when the latch stage load capacitance CLat output nodes discharges until the first PMOS (M9/M10) turns on. Here, the first PMOS (M9/M10) will turn on when first preamplifier output node (F+/F−) will discharge from VDD to (VDD−Vthp) [24]. Thus, CLis discharged by Vthp in tamp time duration. Hence, tamp is obtained as: tamp =CL· {VDD −(VDD − |Vthp|)} IB1 ,(2) tamp =CL· |Vthp| IB1 =2CL· |Vthp| I,(3) where IB1is the drain current of MK1. Let, sum of IB1and IB2currents (i.e. IB1+IB2) is equal to total supply current I, then IB1can be approximated as half of supply current Ifor small differential input (∆Vin). If ∆V0is the initial output voltage difference at the beginning of comparison phase, latch delay can be obtained from [31]: tlatch =τ·ln    VDD 2 ∆V0  ,(4) where τ=CL/gm,eff in which gm,eff is the effective trans-conductance of the cross-coupled inverters. From Eq. (4), it is clear that speed of proposed comparator can be improved by enhancing ∆V0and gm,eff . •Enhancement in ∆V0: As discussed earlier, tamp is the time after which comparison phase starts and one of the latch output charges back to VDD. According to Eq. (4) at this time tamp, differential output ∆V0has a significant impact on tlatch time. Enhancement in ∆V0lessens the latch time tlatch. From [24], ∆V0of this comparator is calculated as: ∆V0=|V+ out(t=tamp)−V− out(t=tamp)|= =|Vthp| − IB2·tamp CL = =|Vthp| 1−IB2 IB1!, (5) c 2019 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 448 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 17 |NUMBER: 4 |2019 |DECEMBER where, IB1and IB2are the drain currents of the left and right branches of the latch stage. Considering ∆IB=|IB1−IB2|=gmK1,2×∆VF+/F −, Eq. (5) is rewritten as: ∆V0=|Vthp|· ∆IB IB1 ≈2|Vthp|· gmK1,2×∆VF+/F − I, (6) where gmK1,2is the effective trans-conductance of the intermediate PMOS transistors MK1and MK2 of latch stage and ∆VF+/F −is the differential voltage of the pre-amplifier stage output nodes F+ and F−at the time tamp. Both these influencing parameters gmK1,2and ∆VF+/F −amplify ∆V0resulting latch delay reduces. The voltage difference at nodes F+/F−at time tamp,∆VF+/F −can be determined as: ∆VF+/F −=|VF+(t=tamp)−VF−(t=tamp)|= =tamp ·IN1−IN2 CL,F +(−) = =tamp ·gm1,2·∆Vin CL,F +(−) . (7) In this equation, IN1and IN2are the currents of input transistors of which difference depends on the input voltage difference i.e. ∆IB=gm1,2×∆Vin and gm1,2is the transconductance of the input transistors M1/M2. By substituting Eq. (7) in Eq. (6), we have: ∆V0= 2|Vthp| I!2 ×CL CL,F +(−) × ×gmK1,2×gm1,2×∆Vin. (8) •Enhancement in effective trans-conductance: In proposed comparator, it is evident that the output nodes F+/F−of input stage discharge in decision making phase, ensuing turns on intermediate stage transistors and strengthens positive feedback, thus the effective trans-conductance of the latch is increased i.e. (gm,eff +gmK1,2). Hence, τ=CL gmK1,2+gm,eff , and: tlatch =CL (gmK1,2+gm,eff )·ln    VDD 2 ∆V0  .(9) Finally, including effects of both parameters, the total delay of proposed comparator is derived from: tdelay =tlatch +tamp = =2CL· |Vthp| I+CL (gmK1,2+gm,eff )× ln      VDD 2 2|Vthp| I2CL CL,F +(−) .gmK1,2.gm1,2.∆Vin      . (10) From expression derived in Eq. (10), it can be concluded that total delay strongly depends on input voltage difference, supply current, transconductance of input and intermediate stage transistors, and the ratio of CLand CL,F +(−). These parameters reduce delay logarithmically and amplify the whole speed of proposed comparator which can be confirmed by the simulation results. 2.3. Mismatch Analysis In the proposed comparator, two intermediate PMOS transistors (MK1and MK2) are included with two phase dynamic comparator [30], thus mismatch effect of threshold voltage (∆VT hK1,2) and current factor (∆βK1,2) due to MK1/MK2transistors is considered for input offset analysis. However, the threshold voltage and current factor mismatch effect is insignificant in most cases except small differential input voltage (∆Vin), where output nodes of input stage F+and F− follows each other at similar discharge rate. As a result, the decision making outcome might be disturbed due to the mismatch of intermediate transistors. Therefore, following two brief analysis of mismatch effects, caused by threshold voltage and current factor, have been considered on the input offset voltage. •Effect of Threshold Voltage Mismatch of MK1and MK2(∆VT hK1,2): The differential current caused by the MK1/MK2threshold mismatch is achieved as: ∆IB=gmK1,2×∆VT hK1,2.(11) Hence, the input offset voltage caused by the MK1/MK2threshold mismatch is calculated as follows: ∆Veq,due∆VT hK1,2=CL,F +(−) tamp ·gm1,2 ·∆VT hK1,2.(12) •Effect of Current Factor Mismatch of MK1and MK2(∆βK1,2): The current factor mismatch of MK1/MK2can be obtained as channel length mismatch ∆WK1,2. In order to find input offset voltage due to current factor mismatch, the differential c 2019 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 449 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 17 |NUMBER: 4 |2019 |DECEMBER current in terms of ∆WK1,2can be written as: ∆IB=1 2µp.Cox ·∆WK1,2 L·(VgsK1,2−VT hK1,2)2. (13) Hence, the input offset voltage caused by the MK1/MK2current factor mismatch is calculated as follows: ∆Veq,due∆βK1,2=∆IB·CL,F +(−) tamp ·gmk1,2·gm1,2 = =0.5µp·Cox ·CL,F +(−) tamp ·gmk1,2·gm1,2 ×∆WK1,2 L× ×(VgsK1,2−VT hK1,2)2. (14) Thus, the total input offset due to both mismatch factors of the intermediate transistors MK1/MK2 can be determined as: σtotal =qσ2 ∆VT hK1,2+σ2 ∆βK1,2.(15) Expressions derived in Eq. (12) and Eq. (14) conclude that the trans-conductance of input transistors (gm1,2) is effective to diminish input offset. So, the size of these input transistors is kept usually large in reducing the effect of intermediate transistors mismatch, which results in low input offset voltage. 2.4. Kickback Noise In the regenerative latched based dynamic comparators, the voltage discrepancy at the output nodes, coupled to input stage transistors, can disturb the input voltage due to nonzero output impedance. This effect, known as kickback noise, may affect the comparator accuracy. As explained in [10], the high speed and low power comparators create larger disturbance at the input nodes. Hence, it is inescapable in the fast latching circuits. In Fig. 3, the undesired peak errors are depicted in the transient response of input voltage at ∆Vin = 10 mV. To determine kickback noise, the Thevenin equivalent of input is modeled with resistance of 8 kΩ. Figure 4 illustrates the peak error in the input voltage as a function of input voltage difference for three different structures. The proposed comparator has higher kickback noise than two phase dynamic [30] while lower than conventional [27]. The intermediate transistors of proposed circuit are not as robust as latch of two phase dynamic. Thus, the size of these transistors is determined in such a way that the proposed circuit maintains high switching speed and low power dissipation with reduced kickback noise. The disturbance at reference voltages is negligible as compared to inputs due to low impedance at reference nodes. The main discrepancy occurs during amplification phase when reference voltage takes some level settling time before the start of regeneration phase. In some applications, in order to reduce the kickback noise where it becomes significant, the kickback noise reduction techniques, such as neutralization in [10], can be applied. The proposed comparator is simulated with neutralization technique as shown in Fig. 4. 0.5 Differential Input Voltage (mV) Time (ns) Differential Input Voltage (mV) 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 Fig. 3: Undesired peak errors in the input voltage at ∆Vin = 10 mV and VDD = 1 V. 10 0 10 1 10 2 10 0 10 1 10 2 10 3 Peak Input Voltage Error (mV) Input Voltage Difference (mV) Conventional [27] Two Phase Dynamic [30] Proposed Proposed with neutra lization Fig. 4: The plot of measured peak error in input voltage due to kickback noise versus input voltage difference variation. 3. Design Considerations In the proposed structure, there are several design issues that must be considered. The sizing of crosscoupled PMOS transistors MK1/MK2, located between cross-coupled inverters of latch stage, is an important issue for high speed, low voltage, and low offset operations. These transistors may create the voltage headroom problem, limiting the low voltage applications. In c 2019 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 450 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 17 |NUMBER: 4 |2019 |DECEMBER order to overcome this problem, MK1/MK2transistors of low resistance, i.e. of large size, are required. The input offset might be affected by the threshold voltage and current factor mismatch between MK1/MK2 transistors. To diminish this effect, MK1/MK2transistors of large transconductance are required. Therefore, large transistors must be used. However, the large size transistors affect the parasitic capacitances of F+/F− nodes, CL,F +(−), and resulting delay bottlenecks. As, the increased parasitic capacitances restrict the speed of comparator, the size of the MK1/MK2transistors is optimally selected in such a way that maintains the high speed, low voltage, and low offset operations. In the proposed comparator, CLK1and CLK2are designed as unbalanced clocks. CLK2is delayed by ∆ttime from CLK1, and amplification delay (tamp) depends on this delay time (∆t). So, the design of clock generation circuit is another important issue. As depicted in Fig. 5(a), the delay of CLK2with respect to CLK1is controlled by varying Vctrl of the current inverters in the clock buffers. At small ∆Vin, the comparison is very difficult in evaluation phase. Therefore, in amplification phase, the sufficient amplification time (tamp) is required to develop the differential output voltage at the internal nodes F+/F −. Thus, ∆ttime is set such that it is equal to or greater than tamp (∆t≥tamp). If ∆t<tamp, it will create the error in comparison phase for small ∆Vin. At higher values of ∆t, the input offset is reduced effectively. However, the delay is increased rapidly. Hence, to maintain the high speed and low input offset, ∆tis kept equal to or slightly greater than tamp. For proposed circuit, ∆t=tamp. The conceptual waveforms are shown in Fig. 5(b). Vout Vctrl Vin CLK1 CLK2 Delayed byΔt Current Inverter (a) Δt tamp FF+ VDD CLK1 CLK2 (b) Fig. 5: (a) Clock generation circuit, (b) Conceptual waveform. 4. Simulation Results and Discussion To compare the proposed comparator with existing conventional [27] and two phase dynamic comparator [30], the circuit is designed in CADENCE and results are simulated in SPECTRE at 90 nm CMOS technology with VDD = 1 V, VCM = 0.9V and ∆Vin = 5 mV. For fair and authentic comparison of simulation results, the designed circuits from [27] and [30] are simulated in alike simulation environment and framework which is used to simulate the proposed circuit. Figure 6 shows the layout of proposed circuit with area occupancy 64.08 µm2 (9 µm×7.12 µm). The appropriate caution has been taken in layout design to avoid effect on power, offset and delay. Figure 7 shows the dependence of delay on power supply for proposed comparator and results are compared with other two configurations. It is obvious that speed is significantly enhanced in comparison to other circuits. However, delay is higher at low supply voltages in respect of higher voltage supplies. The delay varies from 364.3pS to 221 pS for power supply 0.7V to 1.2V. Figure 8 and Fig. 9 demonstrate the variation of TDelay and TLatch with VDD at different values of differential input voltage. The values of ∆Vin are set as 1mV, 5mV, 10 mV, 50 mV and 100 mV. It is obvious that TDelay and TLatch at particular VDD are reduced as ∆Vin is increased. At VDD = 1.1V, total delay is dropped from 334.59 pS at ∆Vin = 1 mV to 168.87 pS at ∆Vin = 100 mV whereas latch delay drops down from 217.08 pS to 51.36 pS. Also, TDelay and TLatch at particular ∆Vin are decreased as VDD is increased. At ∆Vin = 10 mV, TDelay lessens from 272.28 pS at VDD = 0.7V to 186.46 pS at VDD = 1.2V and TLatch from 132.04 pS to 71.33 pS. 111111111111111 111111111111111 111111111111111 111111111111111 111111111111111 111111111111111 111111111111111 111111111111111 111111111111111 111111111111111 111111111111111 111111111111111 111111111111111 111111111111111 111111111111111 111111111111111 111111111111111 111111111111111 111111111111111 111111111111111 111111111111111 111111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 11111111111111 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In Fig. 10, the analytical outcomes from Eq. (10) are compared with simulated values of delay at different ∆Vin and VCM =VDD −0.1V. The delay calculated from analytical derivations shows good matching with delay from simulations. The negligible difference is found which is due to non-linear second order effects. These effects are approximated and neglected during analytical derivations of delay to convert the complex expressions into simple expressions. c 2019 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 451 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 17 |NUMBER: 4 |2019 |DECEMBER Figure 11 and Fig. 12 depict the dependency of TDelay and TLatch on input voltage difference and results are compared with previous structures. Here, ∆Vin varies from 1mV to 30 mV at VDD = 1 V, VCM = 0.9V and load capacitance, CLis 5fF. At ∆Vin = 20 mV, TDelay for proposed circuit is 190.63 pS while 298.6pS and 197.67 pS for conventional design and two phase dynamic circuit, respectively. These results confirm that the delay is reduced for proposed comparator in comparison with past comparators. Also, a significant speed is enhanced compared to conventional circuit. The reason behind the speed improvement is a boost in ∆V0. As shown in Fig. 13, ∆V0variation is represented with ∆Vin. As ∆Vin is increased from 1mV to 30 mV, ∆V0amplifies fast at small differential input and becomes approximately constant at higher values of ∆Vin which confirms the delay is reduced minimally at large values of ∆Vin. It also depicts that ∆V0is heightened at particular value of ∆Vin for proposed configuration as compared to others. For example, at ∆Vin = 10 mV, ∆V0is boosted to 353 mV whereas 136 mV for conventional circuit. At particular value of CL= 5 fF and VDD = 1 V, ∆V0increases by 225 mV, from 190 mV to 415 mV for ∆Vin variation from 1mV to 30 mV. 0.7 0.8 0.9 1.0 1.1 1.2 200 300 400 500 600 700 800 T Delay (pS) V DD (V) Conventional [27] Two Phase Dynamic [30] Proposed Fig. 7: Total delay for different structures versus VDD at ∆Vin = 5 mV, VCM =VDD −0.1V. Figure 14 represents that slew rate depends on ∆Vin. Slew rate increases with increment of ∆Vin and has larger values for proposed circuit than other circuits. The slew rate is defined as change in output voltage with respect to time (∆V0/∆t). It proves that slew rate will be higher at small delay time. Slew rate at ∆Vin = 5mV is 4.03 V·nS−1which is much greater than 2.14 V·nS−1for conventional structure. The whole simulated results conclude that delay is significantly reduced with comparable power dissipation, Pdiss as shown in Fig. 15. Pdiss at ∆Vin = 10 mV is 44.97 µW for proposed which is comparable to 43.79 µW for two phase dynamic. Moreover, Pdiss is significantly lower than that of conventional circuit at every particular value of ∆Vin. For example, Pdiss = 53.36 µW at ∆Vin = 5 mV for proposed, on the contrary, 86.07 µW for conventional circuit. It is obvious that speed is expressively enhanced while consuming almost same power. Hence Energy Per Conversion (EPC) [24] is reduced which is defined as EPC =Pdiss 2ENOB ·fs , where ENOB is effective number of bits and fsis sampling frequency. 0.7 0.8 0.9 1.0 1.1 1.2 150 200 250 300 350 400 450 500 550 T Delay (pS) V DD (V) V in =1mV V in =5mV V in =10mV V in =50mV V in =100mV Fig. 8: Total delay for proposed comparator versus VDD at various ∆Vin (VCM =VDD −0.1V). 0.7 0.8 0.9 1.0 1.1 1.2 0 50 100 150 200 250 300 350 400 T latch (pS) V DD (V) V in =1mV V in =5mV V in =10mV V in =50mV V in =100mV Fig. 9: Latch delay for proposed comparator versus VDD at various ∆Vin (VCM =VDD −0.1V). EPC in proposed circuit is slightly reduced in comparison with two phase dynamic circuit while an impressive drop occurs in respect of conventional circuit as shown in Fig. 16. For 1bit conversion, EPC is decreased from 13.25 fJ to 3.4fJ at ∆Vin = 5 mV after comparing with conventional structure, on the contrary, a slight drop with two phase dynamic from 2.15 fJ to 1.99 fJ at ∆Vin = 10 mV. In Tab. 1, the performance of the proposed structure has been sumc 2019 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 452 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 17 |NUMBER: 4 |2019 |DECEMBER marized. Table 2 includes and verifies both analytical analysis and 0.2k Monte Carlo simulated values for offset voltage. There is a small difference in calculated and simulated values. The offset voltage calculated from analytical derivations is lower than the simulated result by meticulous 1−σMonte Carlo simulations. The small difference is due to the dynamic offset which is not considered in analytical derivations. 0 . 7 0 . 8 0 . 9 1 . 0 1 . 1 1 . 2 150 200 250 300 350 400 450 500 550 600 TD e l a y ( p S ) VDD ( V ) ∆Vin = 1 m V ( A n a l y t i c a l ) ∆Vin = 1 m V ( S im u l a t e d ) ∆Vin = 5 m V ( A n a l y t i c a l ) ∆Vi n = 5 m V ( S i m u l a t e d ) ∆Vi n = 1 0 m V ( A n a l y t i c a l ) ∆Vi n = 1 0 m V ( S i m u l a t e d ) Fig. 10: Verification of analytical analysis with simulation results for delay at different ∆Vin and VCM =VDD −0.1V. 0 5 10 15 20 25 30 160 240 320 400 480 560 640 720 800 T Delay (pS) V in (mV) Conventional [27] Two Phase Dynamic [30] Proposed Fig. 11: Total delay for different structures versus ∆Vin at VDD = 1 V, VCM = 0.9V. Figure 17 shows the offset voltage variation of current proposed circuit with previous configurations at three different supply voltages. By using unbalanced clock scheme, the input offset is reduced remarkable with respect to conventional, and additions of intermediate transistors lessen somewhat more input offset voltage, but keep in mind that size of these transistors should be larger with respect to others. At VDD = 1.2V, the input offset voltage (Vos) is 63.85 mV, 11.67 mV and 8.32 mV for conventional, two phase dynamic and proposed circuit, respectively. At each point, the offset results are achieved using 1−σMonte Carlo simulations at 200 samples run. As shown in Fig. 18, the standard deviation of the input offset (σos) for the proposed circuit is derived to be 10.8mV at VDD = 1 V using 1−σbased Monte Carlo simulations. 0 5 10 15 20 25 30 0 100 200 300 400 500 600 T Latch (pS) V in (V) Conventional [27] Two Phase Dynamic [30] Proposed Fig. 12: Latch delay for different structures versus ∆Vin at VDD = 1 V, VCM = 0.9V. 0 5 10 15 20 25 30 0 50 100 150 200 250 300 350 400 450 V 0 (mV) V in (mV) Conventional [27] Two Phase Dynamic [30] Proposed Fig. 13: ∆V0(differential output voltage at t=tamp) for different structures versus ∆Vin at VDD = 1 V, VCM = 0.9V. Table 3 presents the corner analysis for proposed comparator at ∆Vin = 5 mV and VDD = 1 V. Thus, the proposed circuit works properly at different corners. However, the delay is increased with some extent at SS corner. To draw a fair comparison, the proposed structure and two other structures from [27] and [30] are simulated and compared in same simulation environment at 90 nm CMOS technology as shown in Tab. 4. The width of the MOS transistors is set such that the optimized values are drawn for delay and offc 2019 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 453 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 17 |NUMBER: 4 |2019 |DECEMBER set. Finally, Tab. 5 relates the performance parameters of the proposed structure with previous works. Slew Rate (V nS1 ) V in (mV) Conventional [27] Two Phase Dynamic [30] Proposed . 0 5 10 15 20 25 30 1 2 3 4 5 6 Fig. 14: Slew rate for different structures versus ∆Vin at VDD = 1 V, VCM = 0.9V. 0 5 10 15 20 25 30 30 40 50 60 70 80 90 100 110 120 130 P diss ( W) V in (mV) Conventional [27] Two Phase Dynamic [30] Proposed Fig. 15: Power dissipation for different structures versus ∆Vin at VDD = 1 V, VCM = 0.9V. Tab. 1: Proposed Comparator Performance Summary. Parameters Values CMOS Technology 90 nm Supply Voltage 1V Total Delay, TDelay (VCM = 0.9V, 248.2pS ∆Vin = 5 mV) Latch Delay, TLatch 127.53 pS Differential Output Voltage at tamp (∆V0)308 mV Average Power Dissipation @ freq. = 0.5GHz 53.36 µW Maximum Sampling Frequency 5.7GHz Slew Rate 4.03 V·nS−1 Energy Per Conversion @ ∆Vin = 5 mV 3.4fJ Input Offset Voltage (1−σ) (σos)10.8mV 0 5 10 15 20 25 30 0 5 10 15 20 25 30 35 EPC (fJ) V in (mV) Conventional [27] Two Phase Dynamic [30] Proposed Fig. 16: EPC for different structures versus ∆Vin at VDD = 1 V, VCM = 0.9V. 0.8V 1V 1.2V 0 20 40 60 80 100 120 140 V os (mV) V DD (V) Conventional [27] Two phase dynamic [30] Proposed Fig. 17: Input offset for different structures versus VDD at ∆Vin = 5 mV, VCM =VDD −0.1V. Tab. 2: Validation of analytical analysis with simulated values of offset voltage. VDD ∆Vin =1mV ∆Vin =5mV (V) Simulated Analytical Simulated Analytical Value Value Value Value (mV) (mV) (mV) (mV) 0.8 12.32 10.95 16.81 15.7 1.0 8.79 7.41 11.56 10.8 1.2 6.98 6.03 9.12 8.32 Tab. 3: Performance summary of proposed comparator at different corners. Corners Parameters Delay Power 1−σOffset EPC (pS) (µW)(mV) (fJ) TT 248.2 53.36 10.8 3.39 FF 212.6 56.94 8.9 3.01 FS 273.8 50.23 13.3 3.47 SF 262.4 51.87 11.7 3.42 SS 325.1 48.35 15.4 3.96 c 2019 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 454