Current limiting strategies for grid forming inverters under low voltage ride through

Renewable and Sustainable Energy Reviews 202 (2024) 114657 1364-0321/© 2024 The Author(s). Published by Elsevier Ltd. This is an open access article under the CC BY license (http://creativecommons.org/licenses/by/4.0/). Contents lists available at ScienceDirect Renewable and Sustainable Energy Reviews journal homepage: www.elsevier.com/locate/rser Review article Current limiting strategies for grid forming inverters under low voltage ride through Ander Ordonoa,∗, Alain Sanchez-Ruizb, Markel Zubiagac, Francisco Javier Asensioa, Jose Antonio Cortajarenac aDepartment of Electrical Engineering, University of the Basque Country (UPV/EHU), Avd. Otaola, 29, Eibar, 20600, Spain bDepartment of Electronic Technology, University of the Basque Country (UPV/EHU), Nieves Cano 12, Vitoria-Gasteiz, 01006, Spain cDepartment of Electronic Technology, University of the Basque Country (UPV/EHU), Avd. Otaola, 29, Eibar, 20600, Spain ARTICLE INFO Keywords: Current limiting strategies Grid forming Low voltage ride through Sequence prioritization Transient enhancing strategies Transient synchronization stability ABSTRACT Grid forming inverters are expected to play a key role in future power grids, replacing synchronous generatorbased plants. However, the limited current capability of power electronics makes a difference when facing fault induced voltage sags. This work provides a comprehensive review of strategies to handle low voltage ride through events in grid forming inverters. A key contribution of this work is to differentiate between current limiting and transient stability enhancing strategies. Current limiting strategies are classified into voltage and current-based approaches according to the inverter behaviour during the fault. Their performance is evaluated attending to three criteria: (1) transient current limitation capability, related to the self-preservation of the device; and (2) fault current management and (3) transient synchronization stability, key aspects to meet grid code requirements. The modifications that are required to support the grid under asymmetrical faults are also described, focusing on the management and prioritization of positive and negative-sequence fault currents. Transient stability enhancing strategies are classified according to their implementation into (1) power synchronization loop-based and (2) current saturation-based approaches. Their main characteristics are highlighted and compared, whereas their compatibility with previous current limiting strategies is also discussed. Finally, identified open issues and challenges are covered. Contents 1. Introduction ...................................................................................................................................................................................................... 2 2. LVRT requirements ............................................................................................................................................................................................ 3 2.1. Self-preservation..................................................................................................................................................................................... 3 2.2. Grid synchronization .............................................................................................................................................................................. 4 2.3. Fault current contribution ....................................................................................................................................................................... 5 2.4. Summary............................................................................................................................................................................................... 5 3. Classification of current limiting strategies........................................................................................................................................................... 5 3.1. Current-based limiters............................................................................................................................................................................. 5 3.1.1. Mode switching........................................................................................................................................................................ 5 3.1.2. Current saturation .................................................................................................................................................................... 5 3.2. Voltage-based limiters............................................................................................................................................................................. 6 3.2.1. Threshold virtual impedance ..................................................................................................................................................... 6 3.2.2. Voltage saturation .................................................................................................................................................................... 7 3.3. Summary............................................................................................................................................................................................... 7 4. Performance of current limiting strategies............................................................................................................................................................ 7 4.1. Transient overcurrent limitation .............................................................................................................................................................. 7 4.1.1. Current-based limiters............................................................................................................................................................... 8 4.1.2. Voltage-based limiters............................................................................................................................................................... 8 4.2. Fault current control............................................................................................................................................................................... 9 ∗Corresponding author. E-mail address: [email protected] (A. Ordono). https://doi.org/10.1016/j.rser.2024.114657 Received 23 February 2024; Received in revised form 20 May 2024; Accepted 10 June 2024 Renewable and Sustainable Energy Reviews 202 (2024) 114657 2 A. Ordono et al. 4.2.1. Current-based limiters............................................................................................................................................................... 9 4.2.2. Voltage-based limiters............................................................................................................................................................... 9 4.3. Transient synchronization stability........................................................................................................................................................... 9 4.3.1. Mode switching........................................................................................................................................................................ 10 4.3.2. Current saturation .................................................................................................................................................................... 10 4.3.3. Threshold virtual impedance ..................................................................................................................................................... 11 4.3.4. Voltage saturation .................................................................................................................................................................... 11 4.4. Summary............................................................................................................................................................................................... 12 5. Current limiting strategies for asymmetrical faults................................................................................................................................................ 12 5.1. Current-based limiters............................................................................................................................................................................. 12 5.2. Voltage-based limiters............................................................................................................................................................................. 12 6. Stability enhancing strategies.............................................................................................................................................................................. 13 6.1. Power synchronization loop-based strategies............................................................................................................................................. 14 6.1.1. Power reference modification .................................................................................................................................................... 14 6.1.2. Adaptive power synchronization................................................................................................................................................ 14 6.1.3. Freeze angular speed ................................................................................................................................................................ 14 6.2. Current saturation-based strategies........................................................................................................................................................... 15 6.2.1. Voltage-based frequency feedforward......................................................................................................................................... 15 6.2.2. Reactive power synchronization ................................................................................................................................................ 15 6.2.3. Virtual power .......................................................................................................................................................................... 15 6.2.4. Internal voltage anti-windup ..................................................................................................................................................... 15 6.3. Summary............................................................................................................................................................................................... 15 7. Open issues and challenges................................................................................................................................................................................. 16 7.1. Regulatory framework ............................................................................................................................................................................ 16 7.2. Transient stability under high penetration of GFM inverters....................................................................................................................... 17 7.3. Transient voltage stability ....................................................................................................................................................................... 17 7.4. Current limitation under other transients.................................................................................................................................................. 17 7.5. GFM inverter based protection systems .................................................................................................................................................... 17 8. Conclusions ....................................................................................................................................................................................................... 17 CRediT authorship contribution statement ........................................................................................................................................................... 17 Declaration of competing interest........................................................................................................................................................................ 17 Data availability ................................................................................................................................................................................................ 17 References......................................................................................................................................................................................................... 18 1. Introduction In the last decades, the concern about climate change and the continuous rise in power consumption have led to an increasing integration of renewable energy resources into the electrical grid. These systems have contributed to reduce greenhouse gas emissions, increase the network power capacity and enhance the overall efficiency [1]. However, unlike traditional generation, these are mainly inverter-based resources (IBR), bringing new challenges from grid operation and management perspective [2]. Electrical grids have relied on conventional power plants, based on synchronous generators (SG), to provide grid services and ensure their reliability. SGs provide inertial response, frequency and voltage support, power oscillation damping and/or load unbalance sourcing, among other functions [3]. Furthermore, the protections and fault procedures have been designed according to the characteristics of these machines [4]. As the penetration of renewable resources increase, the ratio of IBRs will exceed that of SGs, with regions with 100% penetration of IBRs [5]. In this context, IBRs should assume the services that were previously provided by SGs. The most common strategy for managing IBRs is the grid following (GFL) control [6]. In GFL, the inverter behaves as a controlled current source, requiring a synchronization mechanism to connect to an existing grid. The most common approach is the phase-locked loop (PLL), based on measuring the point of common coupling (PCC) voltage. GFL has shown good results in SG-dominated power grids, but its performance is limited as IBRs become dominant [7]. The inherent reduction of the grid strength and voltage stiffness will impact PLL stability [8]. Moreover, the lack of inertia produces fast frequency transients which cannot be tracked by the inner dynamics of PLLs [9]. In this context, grid forming (GFM) control has emerged as a solution to support future grids. Despite sharing the same hardware, GFM inverters will behave as voltage sources, synchronizing with the grid through power balance. GFM inverters could replace SGs, providing synthetic inertia, stability in low strength grids and standalone operation by establishing the frequency and voltage [10]. However, even if GFM inverters are a promising solution, they are still in an early-state development, with several pilot projects evaluating their capabilities [11]. There are several challenges that need to be faced before they can be integrated into the power grid [12]. One of these challenges is the fault ride-through capability, which has been included in the top ten power system stability challenges identified by European transmission system operators in the context of MIGRATE project [13]. Among faults, literature has extensively addressed short-circuit induced voltage sags, in which GFM inverters will suffer from high overcurrents due to their voltage source behaviour. As the transient overcurrent capability of power electronics (110%–150% of rated current) is far below SGs one (>1000%) [14], current limiting strategies are required. These strategies should not only protect inverter hardware from overcurrents, but they are also required to meet grid code requirements, by keeping the inverter synchronized with the grid (transient synchronization stability) and supporting voltage recovery through fault currents [15]. The aim of this work is to fill the gap related to low voltage ridethrough (LVRT) strategies in GFM inverters, providing an overview of the strategies that can limit the current and enhance the transient stability during these events. Current limiting strategies have already been discussed in previous reviews [12,16,17]. However, these works were not focused on LVRT, lacking a detailed comparative and evaluation. These strategies have also been evaluated attending to different criteria, such as transient current limitation capability [18,19], fault current control [20] and transient stability [19,21]. However, none of them have gathered all of these topics together and the number of evaluated strategies was limited. Additionally to current limiting approaches, strategies to improve transient synchronization stability Renewable and Sustainable Energy Reviews 202 (2024) 114657 3 A. Ordono et al. Nomenclature Abbreviations APS Adaptive power synchronization CS Current saturation GFL Grid following GFM Grid forming IBR Inverter-based resource LVRT Low voltage ride through MS Mode switching PCC Point of common coupling PLL Phase-locked loop PRM Power reference modification PSL Power synchronization loop RPC Reactive power control SEP Stable equilibrium point SG Synchronous generator TVA Threshold virtual admittance TVI Threshold virtual impedance UEP Unstable equilibrium point VPA Virtual power angle VS Voltage saturation Symbols 𝛥𝑉 Voltage magnitude difference between internal voltage reference and PCC voltage 𝛿Virtual power angle 𝛾Phase difference between the PLL output and PCC voltage 𝜔Angular frequency 𝜎Reactance to resistance ratio 𝜏Time constant of the grid impedance 𝜃Internal angle 𝜑current phase, referred to 𝑑axis 𝐷Damping coefficient 𝐸Internal voltage reference 𝐻Inertia constant 𝐼Current magnitude 𝑖Current vector 𝐿Inductance 𝑃Active power 𝑄Reactive power 𝑅Resistance 𝑣Voltage vector 𝑋Reactance 𝑍Impedance Superscripts ∗Setpoint Subscripts 𝑐Converter-side signal 𝑒𝑞 Equivalent. Value measured between inverter to grid 𝑓Filter value 𝑔Grid signal 𝑙𝑖𝑚 Limited signal 𝑚𝑎𝑥 Maximum value 𝑜Capacitor-side signal 𝑝𝑐𝑐 Point of common coupling signal 𝑡ℎ Threshold value 𝑢Unstable 𝑣Virtual during faults have been also addressed in literature. In some cases, current limiting and stability enhancing strategies were mixed without a clear differentiation [22,23]. Transient enhancing approaches were discussed in [24], but their compatibility with current limiting strategies was not addressed. Finally, [25] described some current limiting and stability enhancing strategies, but no classification was provided. Compared to previous works ( Table 1), the main contributions of this study are: •Providing a classification of LVRT strategies attending to their target: (1) current limitation and (2) transient stability enhancement. •Classifying the existing current limiting strategies into voltagebased and current-based approaches. The strategies inside each group are also categorized into subgroups. The performance from self-preservation and grid code requirements perspective is evaluated. •Describing the modified current limiting strategies that can provide positive and negative-sequence fault current contribution for asymmetrical faults. •Classifying the existing transient stability enhancing strategies. These are classified into two groups depending on their implementation, and compatibility with current limiting strategies is addressed. The research methodology was comprised of three key steps. First, the topic was discussed and existing grid code requirements were identified. Then, literature was searched and screened. The literature which was most related to GFM inverters and LVRT strategies was left, based on title, abstract and full text. Finally, the identified articles were analysed and summarized according to the structure of the review, which is presented in Fig. 1. Section 2overviews LVRT requirements for IBRs. Section 3describes and classifies GFM current limiting strategies. Following this, Section 4compares their performance attending to transient current, fault current management and stability perspective. Section 5explores the modifications that provide independent positive and negative-sequence fault current control under asymmetrical faults. Section 6classifies and compares the strategies that can enhance the synchronization stability during the LVRT event. Section 7covers some open issues, whereas the conclusions are summed up in Section 8. 2. LVRT requirements First grid codes were focused on protecting IBRs, disconnecting them under disturbances. However, as the share of IBRs increase, this approach could lead to instability and cascaded failures [27]. Current grid codes are requiring IBRs to support the grid during LVRT events. The expected behaviour of a GFM inverter during a fault, given in Fig. 2, could be summarized in three targets: (1) self-preserving the inverter, (2) keeping synchronized to the grid and (3) contributing with a fault current. 2.1. Self-preservation IBRs must limit the current magnitude during a fault to protect the semiconductors and prevent an overcurrent tripped disconnection. Renewable and Sustainable Energy Reviews 202 (2024) 114657 4 A. Ordono et al. Fig. 1. Structure of the review. Table 1 Topics covered in other reviews. References LVRT Current limiting Performance of current limiting strategies Asymmetrical Stability improving requirements strategies Current transient Fault contribution Transient stability faults strategies [13,26] x [17,22] x [23,24] x x [18] x x [20] x x x [16] x x [19] x x x [25] x x [12] x x x This review x x x x x x x Fig. 2. Converter current and grid voltage evolution of a GFM inverter during a voltage sag. Transient current limitation is critical during the first cycles after the sag. Unlike GFL inverters, GFM inverters behaving as voltage sources will be prone to overcurrents due to the voltage difference between the inverter terminal and the PCC voltage. 2.2. Grid synchronization The disconnection of IBRs during LVRT events is determined based on a voltage-time pattern, depending on both PCC voltage sag and its duration. Most countries have their own grid code requirements, including the operating voltage range, fault duration and restoration time [28,29]. International organizations like IEEE have also published relevant requirements for IBRs. For instance, IEEE 1547-2018 brought certain regulations for the interconnection and interoperability between distribution grids and distributed energy resources [30]. Regulations for interconnecting IBRs and transmission grids are covered in IEEE 2800-2022 [31]. Some voltage-time curves are shown in Fig. 3. IBRs should stay connected and synchronized with the grid if the PCC voltage transient is above the line. From synchronization perspective, the challenge in GFL inverters is linked to the instability caused by PLL dynamics, whereas GFM inverters might desynchronize due to power balance loss. It is critical for the stability of the grid that IBRs keep synchronized during the Renewable and Sustainable Energy Reviews 202 (2024) 114657 5 A. Ordono et al. Fig. 3. Voltage vs. time LVRT requirements for different standards. event. Once the fault is cleared, they should restore normal operation in a seamless approach, without power oscillations that could perturb other devices. 2.3. Fault current contribution IBRs should contribute to restore the voltage during a fault. Some specific national grid codes (Spanish [32], German [33]), and international standards (IEEE 2800-2022) are requiring IBRs to support the grid both during symmetrical and asymmetrical faults. This is achieved by injecting a positive-sequence capacitive current to increase voltage magnitude, and a negative-sequence inductive current to reduce voltage unbalance in asymmetrical faults. In all cases, fault currents should be proportional to the magnitude of the positive and negative-sequence PCC voltage. The exact proportion depends on specific system operator requirements. Grid codes are also requiring maximum utilization of IBRs current capacity. Active power exchange can also be required to meet this condition. According to [31], IBRs should have both active and reactive current priorization strategies, being the latter the default. Other requirements such as the current step time response and settling time are usually defined in each grid code. GFL inverters can achieve fault current control by modifying the current setpoint according to measured PCC voltage. However, such strategy is not straightforward in GFM inverters due to its voltage source behaviour, and new strategies are required. 2.4. Summary The trend in all the IBR-related grid codes is similar. They are invariant with respect to the type of energy source, inverter topology and control strategy [34]. Hence, GFM and GFL inverters should meet the same LVRT requirements. A long as compliance with standards is concerned, the performance at the inverter terminal is the only criterion that must be satisfied. This has lead to the development of several LVRT strategies for GFM inverters. In this context, latest UNIFI [35] and AEMO [36] reports have pointed that some requirements are not practical for GFM inverters under some circumstances, and exceptions should be warranted (under the agreement of manufacturers, developers and system operators) until standards can be updated to fully account for them. 3. Classification of current limiting strategies The simplified diagram of a grid-connected GFM inverter is shown in Fig. 4. The inverter is connected to the grid using a typical LC filter and a coupling transformer. The grid is represented as its Thévenin equivalent circuit, with a grid impedance 𝑍𝑔and a voltage source 𝑣𝑔. For the shake of simplicity, the inverter is fed with an ideal DC voltage source, representing a single-stage or a double-stage IBR with negligible DC bus dynamics. The GFM controller includes two control layers: Fig. 4. Simplified diagram of a grid-connected GFM inverter. 1. Outer loop: composed of a Power Synchronization Loop (PSL) and a Reactive Power Control (RPC). The former generates the angular frequency 𝜔using active power balance, whereas the latter will generate the internal voltage reference amplitude 𝐸 based on reactive power balance. Outer loop strategies can be classified into droop controllers, synchronous machine based controllers, and non-linear synchronization methods [37]. 2. Inner loop: It will use outer loops outputs to generate the modulation voltage 𝑣∗ 𝑐. Inner controllers include direct voltage synthesis, single voltage controller or cascaded voltage-current controller [38,39]. The latter is shown in Fig. 4. GFM current limiting strategies can be classified to two main groups: hardware-based and software-based. Hardware-based limiters are an effective and fast way to limit current, but they add extra hardware components and strong distortion due to pulse inhibition [40,41]. Software-based limiters provide high flexibility from current limitation perspective. However, they will be limited by the bandwidth and delay of the controller. This section will focus on software-based strategies, which can be classified into: (1) current-based and (2) voltage-based limiters [16]. 3.1. Current-based limiters Current-based limiters, or direct limiters, will prioritize current control over voltage one. When active, the inverter will lose voltage source behaviour, turning into a controlled current source. Currentbased limiters provide a precise control over the output current, at the cost of reduced transient stability. Moreover, they rely on the existence of an inner current controller. Two main strategies can be found: 3.1.1. Mode switching The mode switching (MS) strategy switches the operation from GFM to GFL during the fault, as shown in Fig. 5. Once the fault clearance is detected by the controller, the inverter switches back to GFM. While in GFL, the inverter is synchronized to the grid through an auxiliary PLL. Its main advantage is that active and reactive currents can be properly managed during the fault. However, apart from losing the voltage source behaviour, its performance will rely on the PLL, making it less reliable under deep sags or weak grids. MS requires an accurate trip signal to transition between modes, increasing implementation complexity. Fault detection algorithms can be based on current [42] or PCC voltage [43]. The seamless transition from GFL to GFM once the fault is cleared is critical to ensure a proper fault recovery [44,45]. 3.1.2. Current saturation In the current saturation (CS), the current limiter is embedded inside the inner control, as shown in Fig. 6. The current setpoint at the output of the voltage controller is saturated to the maximum allowable current, 𝐼𝑚𝑎𝑥. Unlike MS, the angular frequency is derived from the PSL, without an auxiliary PLL. Moreover, there is no need for a tripping signal nor mode switching. Renewable and Sustainable Energy Reviews 202 (2024) 114657 6 A. Ordono et al. Fig. 5. Mode switching (MS) simplified diagram. Fig. 6. Current saturation (CS) simplified diagram. The main drawback of CS is the need of a cascaded control structure. Cascaded controllers require sufficient separation between bandwidths, which might not be feasible in high-power and low-switching frequencies. Moreover, they have been identified as a source of instability [46]. Modified CS strategies that remove the cascaded structure have been proposed. In [47,48], the current controller is seamlessly bypassed under regular conditions. In [49], a parallel voltage and current controller structure with automatic transition is suggested. Current saturation strategies Depending on the saturation approach, three CS algorithms are identified [20]. They are represented in Fig. 7: 1. Instantaneous saturation 2. Magnitude-based saturation 3. Priority-based saturation Instantaneous saturation uses an element-wise saturation. It is usually implemented in natural reference frame 𝑎𝑏𝑐, specially in 4-wire systems, where phase currents can be controlled independently [12]. To prevent the harmonic distortion produced by sinusoidal setpoints clipping, root-mean square values can be used, but transient current limitation is worsened [13]. Instantaneous saturation in 𝛼𝛽 stationary frame or dq rotary frame require conservative limits that reduce the maximum current usage. Hence, magnitude and the priority-based saturation are preferred. Magnitude-based saturation, or circular limiter, limits the magnitude of the original setpoint while keeping the phase unaltered [50]. It can be implemented both in 𝛼𝛽 [51] and dq [52] frames. Prioritybased saturation does not only limit the magnitude, but it can also force the phase to the desired angle 𝜑. Due to its simplicity, dq frame is used [53]. Magnitude and priority-based saturation prevent clipping and maximize the current capability during fault. Priority saturation is prone to higher oscillations, but it adds an extra degree of freedom to improve transient stability [54]. 3.2. Voltage-based limiters In voltage-based limiters, or indirect limiters, the inverter keeps the voltage source behaviour. The current is controlled indirectly by actuating over the voltage setpoint. Compared to current-based limiters, they provide higher flexibility from inner controller perspective, removing the need of current regulators [55]. They also provide better transient stability, at the cost of a higher transient overcurrent. 3.2.1. Threshold virtual impedance The virtual impedance provides the ability to emulate a nonphysical impedance, and it has already been used for filter resonance damping, power flow control, load sharing, ...[56]. In the threshold virtual impedance (TVI), the equivalent impedance between the inverter and the PCC is virtually increased to limit the current. The equivalent simplified circuit is shown in Fig. 8. All the impedances but 𝑍𝑣are physical. TVIs are mainly implemented in 𝛼𝛽 or dq frames, but they have also been proposed in 𝑎𝑏𝑐 frame [57]. To prevent sudden impedance changes, TVIs are usually implemented using a linear approach, starting at a threshold current magnitude 𝐼𝑡ℎ. The linear relation between the current and the virtual impedance (resistance, 𝑅𝑣and reactance, 𝑋𝑣) [58]: 𝑅𝑣={0|𝑖𝑐|≤𝐼𝑡ℎ 𝐾𝑣(|𝑖𝑐|−𝐼𝑡ℎ)|𝑖𝑐|> 𝐼𝑡ℎ (1) 𝑋𝑣=𝐿𝑣𝜔=𝜎𝑅𝑣(2) Reactance to resistance ratio, 𝜎, is a design degree of freedom. A value between 5 and 10 provides proper decoupling of active/reactive power, and damping of synchronous oscillations [59]. The linear gain 𝐾𝑣is selected to limit current magnitude to 𝐼𝑚𝑎𝑥 under a maximum preset voltage magnitude difference, 𝛥𝑉𝑚𝑎𝑥, between 𝐸and 𝑣𝑜(3). 𝐾𝑣√𝜎2+ 1(𝐼𝑚𝑎𝑥 −𝐼𝑡ℎ)≥𝛥𝑉𝑚𝑎𝑥 𝐼𝑚𝑎𝑥 (3) The preset 𝛥𝑉𝑚𝑎𝑥 introduces a trade-off between current limitation capability and stability. Small values do not ensure current limitation under severe voltage sags, whereas large values can produce instability issues due to the high impedance. Additionally, TVI performance will depend on grid impedance, as the sag depth depends on it. Non-linear TVIs can also be implemented by adding exponential terms to (1). Non-linear TVIs operate closer to the maximum current, improving fault-current provision [60]. Threshold virtual impedance strategies TVIs can be implemented using impedance or admittance approach. Moreover, impedance can be placed at two different locations. Simplified diagrams are given in Fig. 9. 1. Impedance-based (a) External: Voltage drop is applied to the setpoints of the outer control, before inner controller. (b) Internal: Voltage drop is applied to the modulation voltage, after inner controller. 2. Admittance-based, or threshold virtual admittance (TVA) Impedance-based approaches apply a voltage drop according to the measured converter current 𝑖𝑐. The external TVI works with the hypothesis that the voltage setpoint is tracked fast by the controller. However, its bandwidth can be below 50 Hz in high power applications [61]. The internal TVI provides a faster response, but it requires an anti-windup of the inner regulators. An alternative approach is to apply both internal and external TVI to prevent windup issues [62,63]. If there is no inner controller, external and internal impedances are equivalent [64]. Impedance-based strategies are usually implemented using quasi-stationary terms, removing the derivative terms that produce noise amplification. Quasi-stationary impedance could turn synchronous oscillations into sub-synchronous, endangering stability [65]. The admittance-based approach emulates the static and dynamic behaviour of an impedance without derivative terms [66]. It is based on the output voltage 𝑣𝑜measurement and a low-pass filter [67]. The impedance is ensured within the bandwidth of the current controller, achieving a dynamic performance between the external and internal TVI. As drawbacks, it requires a current controller and a minimum impedance to operate [57]. Renewable and Sustainable Energy Reviews 202 (2024) 114657 7 A. Ordono et al. Fig. 7. Current saturation types. Fig. 8. Equivalent circuit of a GFM inverter with a threshold virtual impedance. 3.2.2. Voltage saturation Voltage saturation (VS) limits the current indirectly through the limitation of the voltage 𝐸and the angle 𝜃of the outer controllers. This is achieved by meeting Eq. (4), where the magnitude of the difference between 𝐸and 𝑣𝑝𝑐𝑐 must be lower than the voltage drop produced by 𝐼𝑚𝑎𝑥. The voltage drop includes physical and virtual impedances. A simplified diagram is shown in Fig. 10. |𝐸−𝑣𝑝𝑐𝑐 |=|(𝑍𝑡+𝑍𝑣)𝐼𝑚𝑎𝑥|(4) One of the main drawbacks of VS is that it performs the current limitation in open loop, without current measurements. Hence, it is subjected to errors due to impedance uncertainties and tolerances. This problem is minimized if the virtual impedance is predominant, but power exchange capability will be limited [20]. Voltage saturation strategies Depending on the signals which are saturated, two VS strategies are found. Their simplified diagrams are given in Fig. 11. 1. Phase & amplitude VS (PA-VS) 2. Amplitude VS (A-VS) The PA-VS (Fig. 11(a)) limits both the magnitude and angle of the internal voltage, using 𝑣𝑝𝑐𝑐 amplitude and phase information, for which a PLL is required [68,69]. Magnitude is limited to a maximum voltage drop magnitude 𝛥𝑉𝑚𝑎𝑥, whereas the phase shift between 𝐸 and 𝑣𝑝𝑐𝑐 is limited to 𝛿𝑚𝑎𝑥. These limits can be fixed according to the maximum active and reactive power at rated operation. However, adaptive limits have proved to be more effective to improve the current transient response, satisfy the grid code currents, or maximize fault current [70,71]. The performance of PA-VS might degrade under weak grids due to the PLL dynamics. A-VS can remove this element by only limiting the magnitude of the internal voltage (Fig. 11(b)) [72]. As a drawback, the current limitation is only valid against voltage sags, losing protection against other events, e.g., phase jumps. The angle can be indirectly limited using a power limiter based on 𝑣𝑝𝑐𝑐 magnitude [73]. 3.3. Summary The characteristics of current limiting strategies are summed in Table 2. These have been classified into current-based (MS and CS) and voltage-based limiters (TVI and VS). From implementation perspective, MS is identified as the most complex strategy. It requires a fault detection algorithm, an auxiliary PLL to operate during fault, a proper strategy to seamlessly switch from GFL to GFM and an anti-windup due to the saturation of the inner voltage controller. The remaining strategies will not switch from operation mode, and hence, they remove the fault detection and mode switching algorithm. CS strategies will also remove the need of an auxiliary PLL to operate, but they still require an inner current controller and anti-windup for the cascaded controller. Voltage-based limiters provide higher flexibility and less complexity, specially in the case of the external TVI and the A-VS. These strategies do not depend on a current limiter nor auxiliary PLL, acting only on the internal voltage reference with minor modifications. Exceptions are the TVA and the PA-VS. In the case of the TVA, a current controller is still required, but inner voltage controller saturation is prevented. The PA-VS removes the need of a current controller, but it relies on an auxiliary PLL to limit the phase shift during the fault. Regardless of the current-based or voltage-based approach, the strategies which rely on a PLL will be more susceptible to grid conditions, such as impedance or voltage sag depth, than those which depend on PSL. TVIs, which use the PSL during fault, will be also more sensitivity to grid conditions because they are tuned for a preset voltage sag depth. Table 3 gathers the current limiting strategies proposed in literature. CS strategies are the most common approach for LVRT, and both magnitude and priority-based approach are extensively used. In the case of voltage-based limiters, external TVI is the main strategy. Finally, some authors propose hybrid strategies, in which current-based (CS) and voltage-based (TVI) approaches are used together. 4. Performance of current limiting strategies As it has been discussed in Section 2, GFM inverters should achieve three targets during a LVRT event: (1) preventing transient overcurrents that could produce internal damage or tripping the device, (2) keeping synchronized with grid during and after the fault and (3) providing a fault current to support voltage recovery. However, the performance of the GFM inverter will vary depending on the current limiting strategy. 4.1. Transient overcurrent limitation The transient overcurrent limitation capability will mainly depend on the current or voltage source behaviour of the inverter during the fault. Renewable and Sustainable Energy Reviews 202 (2024) 114657 8 A. Ordono et al. Fig. 9. Threshold virtual impedance strategies. Table 2 Main characteristics of current limiting strategies. MS CS TVI VS External Internal Admittance PA A Behaviour Current Current Voltage Voltage Voltage Voltage Voltage Fault & mode switch Yes No No No No No No Synchronization method PLL PSL PSL PSL PSL PLL PSL Cascaded controller Yes Yes No Yes Yes No No Inner controller saturation Yes Yes No Yes No No No Sensitivity to grid conditions High Low Medium Medium Medium High Low Complexity High Medium Low Medium Medium Medium Low Table 3 Current limiting strategies in literature. Current limiting strategy References Mode switching (MS) [19,46,74–76] Current saturation (CS) Instantaneous [42,49,77–79] Magnitude-based [18,20,47,50,51,54,80–86] Priority-based [19,20,53,54,86–95] Threshold virtual impedance (TVI) External [18–20,58,60,64,86,93,96–99] Internal [62,63,100] Admittance [57] Voltage saturation (VS) Phase & amplitude [20,68–71] Phase [72,73,101,102] Hybrid strategy (CS +TVI) [103–107] Fig. 10. Voltage saturation (VS) simplified diagram. 4.1.1. Current-based limiters MS and CS will turn the inverter into a controlled current source, providing a similar performance to GFL inverters. In CS, as the current limitation is embedded in the inner controller, the transient overcurrent will depend on the bandwidth and damping of the current regulator. In this context, hysteresis-based regulators can minimize the transient, at the cost of a variable switching frequency [77]. In MS, the transient overcurrent will also depend on the delay introduced by fault detection and mode switching algorithms. During this delay, the voltage source behaviour is kept, increasing the current transient [70]. 4.1.2. Voltage-based limiters Due to the voltage source behaviour of these limiters, the transient current control is not straightforward. Fig. 12 shows the simplified equivalent circuit of a grid-connected GFM inverter, modelled using two voltage sources and an equivalent impedance 𝑍𝑒𝑞. Initially, the system is operating in the steady state conditions determined by the phasors (upper arrow) in the figure. At 𝑡0, a fault will lead to new operating conditions, identified using an apostrophe (’). The current waveforms before and during the fault are also shown. The current will be the sum of a transient and steady state term [108]: •The steady state term, 𝑖′ 𝑐𝑠, only depends on post-fault voltages and impedance (5).𝜑′is the phase shift of the current after the fault. 𝑖′ 𝑐𝑠(𝑡) = √2|||  𝐸′− 𝑉′ 𝑔  𝑍′ 𝑒𝑞 |||sin(𝜔𝑡 +𝜑′)(5) •The transient term, 𝑖′ 𝑐𝑡, depends on the instantaneous voltage values at fault time (6). It decays exponentially according to the time constant 𝜏′=𝐿′ 𝑒𝑞∕𝑅′ 𝑒𝑞, which depends on the inductance to resistance ratio during fault conditions. 𝑖′ 𝑐𝑡(𝑡) = ⎛⎜⎜⎝√2|||  𝐸− 𝑉𝑔  𝑍𝑒𝑞 |||sin(𝜔𝑡0+𝜑) + √2|||  𝐸′− 𝑉′ 𝑔  𝑍′ 𝑒𝑞 |||sin(𝜔𝑡0+𝜑′)⎞⎟⎟⎠ 𝑒−𝑡∕𝜏′ (6) Voltage-based limiters can limit the steady state term of the current, but the transient term is uncontrolled and it will naturally decay according to 𝜏′[101]. TVIs can reduce this time constant and damp overcurrents faster by increasing the virtual resistance. However, this approach will deteriorate the transient stability, coupling active and reactive powers [109]. To limit the impact on transient stability, a dynamic virtual resistance based on a high-pass filter is proposed in [58]. VSs cannot modify the impedance, and hence, will suffer from long transients, specially in highly inductive lines. Additionally, voltage-based limiters will usually react slower than current-based ones. In voltage-based limiters, the control action takes Renewable and Sustainable Energy Reviews 202 (2024) 114657 9 A. Ordono et al. Fig. 11. Voltage saturation types. Fig. 12. Current transient of a grid-connected GFM inverter using a voltage-based limiter. places at the input of the voltage controller rather than in the inner current controller. The bandwidth of voltage controller will be lower, specially in cascaded inner structures. TVA or internal TVI can provide an increased bandwidth by bypassing the voltage controller, at the cost of an increased complexity (addition of inner current controller, and anti-windup strategy in internal TVI). The transient current control will be further deteriorated in PA-VS, as its performance will also depend on the time that the PLL needs to track and settle 𝑣𝑝𝑐𝑐 . 4.2. Fault current control To meet the fault current requirements of the latest grid codes, current limiting strategies should be capable of operating at maximum current capacity, and provide independent control over active and reactive currents. They should also manage positive and negative-sequence currents. The latter requirement will be covered in Section 5. 4.2.1. Current-based limiters As GFL control, these limiters can dynamically modify the current setpoints attending to measured 𝑣𝑝𝑐𝑐 . These strategies can maximize the current usage of the inverter, but the current controllability will be determined by the synchronization mechanism. In MS, the auxiliary PLL will keep the inverter synchronized with the grid. While synchronized, active and reactive currents can be managed independently. However, the PLL dynamics might deteriorate as the voltage sag depth or grid impedance increases, introducing some coupling between currents. In CS, the PSL is kept as synchronization mechanism. Priority-based limiters have been proposed to handle the current limits according to the grid codes [54]. However, when the current limiter is triggered, the active power balance of the PSL will be lost and the internal voltage will not be aligned with the controller reference anymore. In these conditions, the angle difference between the current and the voltage cannot be specified precisely, coupling active and reactive currents. An additional strategy that ensures the PSL power balance is required to gain control over active and reactive currents. Instantaneous and magnitude-based limiters cannot be used directly to meet fault current requirements, as they will only modify the magnitude of current setpoint which is determined by the voltage controller. 4.2.2. Voltage-based limiters Preserving the voltage source behaviour provides a natural current response to voltage perturbations [80]. This is translated into a fast current injection capability during sags, with response times below 5 ms according to [110]. In TVIs, active and reactive current contribution will be determined by the internal voltage and the grid voltage magnitude and phase, and the overall impedance. As the TVIs are designed to handle the worst disturbance, small voltage sags (e.g., distant fault) will not use the full capacity of the converter. This problem might be alleviated by using non-linear TVIs, which operate closer to the rated current. Moreover, the TVI should be dynamically modified to meet fault current requirements, which could impact the stability of the grid and requires additional grid impedance estimation algorithms. In VSs, having phase and amplitude information through a PLL (PAVS) can provide a proper control active and reactive currents during faults. In A-VS, a dynamic active power limiter needs to be added to prevent power balance loss and ensure proper current injection. In general, using dynamic limitations in A-VS has shown good results in meeting fault current contribution in a simple and effective way [73]. However, the dynamics of the active power limiter might considerably reduce in high inertial systems, making it not suitable for LVRT events. As VSs limit the current in open loop, they require some current margin for component tolerances and uncertainties, reducing maximum current usage. 4.3. Transient synchronization stability Current limiting strategies will also impact transient synchronization stability of GFM inverters, that is, their capability to keep synchronized with the grid during the LVRT event. Their transient stability has been evaluated through different non-linear approaches such as Lyapunov direct method [111], phase portrait [112] or virtual power angle (VPA) [21]. This work will focus on VPA method, a quasi-static approach based on the phase difference between 𝐸and 𝑣𝑔, known as virtual power angle, 𝛿. This method can evaluate the transient stability in a graphic and intuitive approach, in a similar way to SGs. The VPA curves of a GFM inverter without current limitation are given in Fig. 13. For simplicity, a symmetrical fault is considered, with the same pre-fault and post-fault curves. In a purely inductive grid, active power is determined by (7), being 𝑋𝑒𝑞 the overall reactance between the inverter and the grid. A GFM inverter with a swing-based PSL is considered, in which the dynamics of 𝜔are determined by (8) in per unit [113]. 𝑃∗and 𝑃are the power setpoint and feedback, 𝐻the inertia constant, 𝐷𝑝the damping coefficient and 𝜔𝑔the grid angular frequency, which can be considered constant. 𝑃=𝐸|𝑣𝑔| 𝑋𝑒𝑞 sin 𝛿(7) Renewable and Sustainable Energy Reviews 202 (2024) 114657 16 A. Ordono et al. Fig. 24. Simplified diagram of CS-based transient enhancing strategies. Table 6 Main characteristics of transient improving strategies. Current limiting strategy Voltage perturbation Voltage source SEP Fault References CS TVI VS Sag Overload behaviour detection Power reference modification x x x x x Yes Yes No [48,76,80,100,133– 135,147] Adaptive power synchronization x x x x Depends on limiter No No [92,93,96,97,99, 138,139] Freeze angular speed x x x x Depends on limiter No Yes [54,86,142,143] Voltage-based frequency feedforward x x No Yes No [88,118,125,144] Reactive power synchronization x x No Yes Yes [94] Virtual power x x x No Yes No [52,145] Internal voltage anti-windup x x x No Yes No [85,128,146] 7. Open issues and challenges Transient overcurrent limitation, fault current contribution and transient synchronization stability have been identified as the three main targets that IBRs, and hence, GFM inverters, should meet during LVRT. Despite the research efforts, there are no dominant current limiting strategies in existing literature. Strategies that provide a proper transient overcurrent limitation usually have a limited transient synchronization stability and vice versa. Transient enhancing strategies have been proposed to face this issue, but the complexity of the controller is increased. Hybridization of strategies is also an interesting approach. Moreover, the control of the active and reactive currents during the fault is usually not straightforward, making it difficult to meet grid code requirements. Additionally, research on asymmetrical faults is also required for a proper deployment of GFM inverters. In this sense, prioritization strategies of positive and negative sequence support is a key topic. Further research in this topic are expected in the future years. Apart from the previously discussed topics, there are still open issues that require research and are open to improvements: 7.1. Regulatory framework GFM inverters are a new technology that does not have a clear definition in most grid codes. It is usually referred to those converters that ‘‘maintain the internal voltage phasor constant or nearly constant in the sub-transient to transient time frame’’ [148]. However, this definition is not valid during overloading conditions. A unique and clear definition must be implemented in all the grid codes to create the basis for establishing a common standard for developing these converters. Efforts for developing specific GFM codes are being carried out, such as the draft code developed by National Grid [132]. This code puts emphasis in the immediate response in LVRT, reflecting the voltage source behaviour of the GFM inverters. The same is true for the analysis in the ENTSO-E report [26] In this line, the latest draft grid code requires that the phase, magnitude and frequency of the internal voltage to remain fixed during faults. The amplitude of the current can be limited to prevent overcurrents, but keeping the phase relative to the voltage source not modified. In the meantime, GFM and GFL inverters should meet the same fault requirements. Renewable and Sustainable Energy Reviews 202 (2024) 114657 17 A. Ordono et al. 7.2. Transient stability under high penetration of GFM inverters The transient stability of GFM inverters under faults can be studied both analytically and numerically [43]. Analytical methods, such as the VPA, can be used to tune the controller parameters and optimize the transient performance. However, due to their complexity, they are limited to a single IBR connected to an ideal grid or equivalent SG. Numerical methods are a better approach to extend the study to several interconnected IBRs, but they difficult parameter optimization. Fault transient stability under different scenarios needs to be assessed more into detail, e.g., including different penetration of GFM and GFL inverters or using mixed current limiting strategies. 7.3. Transient voltage stability Most of the literature has focused on the transient stability from the angle perspective. However, transient voltage stability issues have also been identified, especially when reactive power is prioritized, such as in GFM static compensators. Unlike angle stability, voltage instability only happens in an unidirectional way, when the absorbed reactive power goes over a limit, collapsing the voltage. Even if some strategies have been proposed to face this issue, research efforts are still required on this topic [149]. 7.4. Current limitation under other transients Despite voltage sag being the most studied transient in GFM literature, there are other scenarios that require a current limitation to prevent hardware damage. Among them, frequency excursions due to sudden change in the active power balance, phase jumps due to the tripping of lines or DC power source limits in stochastic sources. Compared to fault induced voltage sags, these events differ in two main aspects: (1) voltage level is not modified largely, and (2) transient dynamics are much lower [150]. Different approaches have been suggested to force the overloaded source to transfer the load to other sources [145]. However, there is no standardized approach. Moreover, these approaches usually turn the PSL into non-linear and modify its dynamics, requiring further research on its stability. 7.5. GFM inverter based protection systems The effect of GFM inverters in AC fault protection systems is still in an early state compared to GFL inverters. Even if GFM inverters can mimic SGs due to the voltage source behaviour, the current contribution is far below conventional machines. Studies must evaluate if regular protection schemes are appropriate and effective long-term solution for a grid with significant proportion of IBRs, or whether a new protection paradigm is needed. Under large-scale integration of GFM inverters, the fault characteristics will depend on converter control. New AC protection schemes might have to consider the cooperation of converter control and protection hardware. The interaction of anti-islanding protections with IBRs is also aggravated when GFM control strategies are used. Traditional GFL inverters will shut off without the presence of an external grid signal. GFM inverters can sustain a stable islanding operation, but they could also energize islanded systems without awareness of the unintentional island situation [151]. A robust set of standards are necessary for autonomous and grid-connected mode, balancing performance and protection requirements. 8. Conclusions This work has carried out a comprehensive review of LVRT strategies for GFM inverters, focusing on those strategies that limit the current and enhance the transient stability, both under symmetrical and asymmetrical events. Current limiting strategies are required due to the voltage source behaviour of the GFM converter, which produces overcurrents during voltage perturbations. Existing strategies have been described and classified into two main groups attending to the behaviour during the fault: voltage-based or current-based. Their performance has been compared attending to LVRT requirements: self protection (transient current limitation) and fault current contribution and transient synchronization stability. Even if current-based limiters are more extended, no strategy stands out: current-based limiters are better in managing transient overcurrents, whereas voltage-based limiters provide higher stability. All in all, research efforts are still required on this topic. The modification of current limiting strategies to handle asymmetrical faults has also been discussed. During these events, both positive and negative sequence currents need to be handled to meet current limitation and fault current contribution of the operator. In most cases, due to the limited current capability of the power converters, a priorization strategy of the positive and negative sequence will be required. In this context, during an asymmetrical fault, GFM inverters could prioritize voltage amplitude and phase balancing, or voltage magnitude boosting. Regardless of the current limiting strategy, the transient synchronization stability of the GFM will be endangered during the LVRT event. This review has also covered the strategies to enhance the stability. Transient enhancing strategies will not limit the current, but they will ensure that the power converter keeps synchronized during the LVRT. These strategies have been classified into two main groups. Those based on the PSL loop modification, and which can be used with any current limiting strategy; and those which are only compatible with current saturation based strategies. This classification reveals the predominant use of current saturation strategies in the literature, which are characterized by their limited transient stability, requiring more effort than other strategies from stability perspective. Finally, open issues and challenges related to the LVRT of GFM inverters have been addressed. The need for a specific regulatory framework stands out, which will set the foundations of GFM inverters in the power grid. In the meantime, several research efforts are required to delve deeper into the impact of GFM inverters in LVRT, such as evaluating the grid performance under high penetration of these converters, the impact on the protection systems, the transient stability from voltage perspective and the evaluation of other voltage transients different from voltage sags. CRediT authorship contribution statement Ander Ordono: Conceptualization, Methodology, Investigation, Writing – original draft. Alain Sanchez-Ruiz: Supervision, Writing – review & editing. Markel Zubiaga: Supervision, Writing – review & editing. Francisco Javier Asensio: Supervision, Writing – review & editing. Jose Antonio Cortajarena: Supervision, Writing – review & editing. Declaration of competing interest The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper. Data availability Data will be made available on request. Renewable and Sustainable Energy Reviews 202 (2024) 114657 18 A. Ordono et al. References [1] Johannsen RM, Mathiesen BV, Kermeli K, Crijns-Graus W, Østergaard PA. Exploring pathways to 100% renewable energy in European industry. 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