Fuzzy controlled parallel AC-DC converter for PFC

POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 9 | NUMBER: 2 | 2011 | JUNE © 2011 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 70 FUZZY CONTROLLED PARALLEL AC-DC CONVERTER FOR PFC SUBBARAO.M1, Sai BABU.Ch2, SATYANARAYANA.S3, SOBHAN.P.V.S1 1Department of Electrical and Electronics Engineering, Vignan’s Engineering College, Vadlamudi, 522 213, India 2Department of Electrical and Electronics Engineering, College of Engineering JNTUK, Kakinada, 533 003, India 3VRS& YRN Eng. College, Chirala, 523 157, India [email protected], [email protected], [email protected], [email protected] Abstract. Paralleling of converter modules is a wellknown technique that is often used in medium-power applications to achieve the desired output power by using smaller size of high frequency transformers and inductors. In this paper, a parallel-connected singlephase PFC topology using flyback and forward converters is proposed to improve the output voltage regulation with simultaneous input power factor correction (PFC) and control. The goal of the control is to stabilize the output voltage of the converter against the load variations. The paper presents the derivation of fuzzy control rules for the dc/dc converter circuit and control algorithm for regulating the dc/dc converter. This paper presents a design example and circuit analysis for 200 W power supply. The proposed approach offers cost effective, compact and efficient AC/DC converter by the use of parallel power processing. MATLAB/SIMULINK is used for implementation and simulation results show the performance improvement. Keywords Flyback converter, PFC, power conversion, fuzzy control. 1. Introduction A number of power factor correction circuits have been developed recently [1], [2], [3], [4] and [5]. Normally a boost converter is employed for PFC with DC/DC stage to improve performance or a flyback converter is used to reduce the cost. Although both boost converter and flyback converter are capable for PFC applications [6], the main difficulty in two-stage scheme employing a PFC boost and a DC/DC converter is the high cost and lower efficiency. However, single-stage method using the simplest flyback converter is not able to tightly regulate the output voltage. Paralleling of converter power modules [7] is a well-known technique that is often used in high-power applications to achieve the desired output power with smaller size power transformers and inductors [10]. Since magnetics are critical components in power converters because generally they are the size-limiting factors in achieving high-density and/or low-profile power supplies, the design of magnetics becomes even more challenging for high-power applications that call for high power-density and low-profile packaging. Instead of designing large-size centralized magnetics that handle the entire power, low-power distributed high density lowprofile magnetics can be utilized to handle the high processing power, while only partial load power flow through each individual magnetics [10], [11]. In addition to physically distributing the magnetics and their power losses and thermal stresses, paralleling also distributes power losses and thermal stresses of the semiconductors due to a smaller power processed through the individual paralleled power stages. As a result, paralleling is a popular approach to eliminating "hot spots" in power supplies. In addition, the switching frequencies of paralleled, lower-power power stages may be higher than the switching frequencies of the corresponding single, high-power processing stages because lower-power, faster semiconductor switches can be used in implementing the paralleled power stages. Consequently, paralleling offers an opportunity to reduce the size of the magnetic components and to achieve a low-profile design for high power applications. Without increasing the number of power stages and control-circuit components, the transformer magnetics can be distributed by direct transformer paralleling. Not only that transformer paralleling distributes the processed power in each magnetics components, but also their power losses and thermal stresses are distributed at the same time. However, current sharing among the paralleled transformers needs to be maintained to ensure power balance. In its basic form, the interleaving technique can be viewed as a variation of the paralleling technique, where the switching instants are phase-shifted within a switching period [12]. By introducing an equal phase shift between the paralleled power stages, the total inductor current ripple of the power stage seen by the POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 9 | NUMBER: 2 | 2011 | JUNE © 2011 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 71 output filter capacitor is lowered due to the ripple Cancellation effect [12]. The goal of the proposed PFC scheme is to reduce the passive component size, to employ lower rated semiconductor, and to improve total efficiency. Simulation results show that the proposed topology is capable of offering good power factor correction and fast dynamic response. 2. PFC Cells 2.1 Two Stage PFC Approach A two-stage scheme shown in Fig. 1 is mainly employed for the switching power supplies since the boost stage can offer good input power factor with low total harmonic distortion (THD) and regulate the dc-link voltage and the DC/DC stage is able to obtain fast output regulation without low frequency ripple due to the regulated dc-link voltage [13]. These two power conversion stages are controlled separately. However, two-stage scheme suffers from higher cost, complicated control, low-power density, and lower efficiency. 2.2 Single Stage PFC Approach For low power applications, where cost is a dominant issue, a single-stage scheme using the flyback converter Fig. 2 is more attractive than a two-stage scheme. 2.3 Parallel PFC Approach At higher power levels, since it may be beneficial to parallel two or more DC/DC converters rather than using a single higher power unit, a parallel-connected scheme is proposed as shown in Fig. 3. This approach can offer fast output voltage regulation and high efficiency. The forward converter with DC/DC stage can offer good output voltage regulation due to the pretty dc input voltage and the flyback converter with AC/DC PFC stage fulfills input current regulation to obtain highly efficient power factor. Fig. 1: Two-Stage PFC. Fig. 2: Single stage PFC. Fig. 3: Proposed parallel-connected single-phase PFC scheme. POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 9 | NUMBER: 2 | 2011 | JUNE © 2011 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 72 Fig. 4: Parallel-connected single-phase PFC scheme. 3. Proposed Parallel PFC Scheme Figure 4 shows the proposed parallel-connected PFC scheme which employs a diode rectifier, dc-link capacitor, forward converter and flyback converter. The function of a forward converter with an electrolytic capacitor is to support output voltage regulation. A flyback converter fulfills the function of power factor correction by making input current sinusoidal and regulating dc-link voltage. The operation of the flyback converter is given in this paragraph considering that the forward converter operates ideally. The PFC Cell (forward converter) operates with continuous conduction mode in both an input inductor and a flyback transformer. The dc-link voltage in this scheme: sdc VV  2. (1) The transfer function of the flyback converter is expressed by defining a conversion ratio as the ratio of the dc output voltage to the input voltage: )1( nD D V V Mdr o   , (2) where, D is the duty ratio of the switch Qh, n (=Np/Ns), is defined as the ratio of Np to Ns, and Np and Ns denote the number of turns of primary and secondary side, respectively. To analyze the circuit parameters, basic equations for voltages and currents are given by: hpdr iii  , (3) d t di LV r dr dr L, (4) dr Ldrhi VVV  , (5) Qhhih VVV   1, (6) where idr, ip, and ih are the rectified, DC/DC Cell, and PFC Cell input currents on dc side. VLdr, Vhi, Vhi, Vdr ,Vh1, VQh, and Vo and are the input inductor, flyback converter input, rectified input, transformer primary winding, switch, and output voltages, respectively. Since the two input currents, ip and ih, are interleaved, input current, idr, ripple can be significantly reduced. The operational sequences are as follows:  t0-t1: As shown in Fig. 5(a) The current of flyback transformer does not flow simultaneously in both windings. When the switch Qh is turned ON at to, VQ becomes zero and diode Doh is turned OFF with a reverse bias. The voltage across the diode Doh equals to Vo + Vhi/n. Energy, LmhI2, is charged in the magnetic field in the primary winding of the flyback transformer. Primary current, ih, ramps up from the remaining magnetizing current and reaches Idr with the slope, (Vhi /Lmh), ip decreases with a slow current tail, and slowly decreases until ip reaches zero. At the same time the forward converter switch Qp is OFF because, as the switch Qh is ON the potential at he junction of diode Dp and input inductor Ldr i.e. VLdr>Vhi, the diode Dp is reverse biased. The diode Dop is also reverse biassed due to the polarity of the forward transformer and a negative voltage of -nVo. The voltage across the output inductor is VL= -Vo and the inductor current iLf decreases and iLf along with ioh, circulates through diode Df, and supplied to load. POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 9 | NUMBER: 2 | 2011 | JUNE © 2011 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 73 Fig. 5(a): Forward converter switch Qp is OFF and flyback converter switch Qh is ON.  t1-t2: The primary current of flyback converter increases by Vdr/(Lmh + Ldr). The voltage across switch Qp decreases from 2Vdr to Vdr. The input inductor current ramps up to till switch Qh is OFF. Fig. 5(b): Forward converter switch Qp is ON and flyback converter switch Qh is OFF.  t2-t3: As shown if Fig. 5(b), when the switch Qh is turned OFF, Doh is turned ON with forward bias. The current in the primary winding ceases to flow. The stored energy is transferred to the secondary winding. At this time, the switch voltage, VQh, becomes Vhi+nVo, ip becomes idr and decreases depending on input voltage, and the secondary current decreases with the slope (n2Vo/Lmh). When the switch Qp is ON, the diode Dp is forward biassed because the potential at junction between the diode and inductor is VLdr<Vhi+nVo. The primary current of forward transformer ramps up and the energy stored in the primary winding is instantaneously transferred to secondary, because of the same polarity of the forward transformer. The diode Dop is forward biassed and diode Df is reversed biassed. The output inductor current iLf increases along with ioh which is delivered to load. The current slope through the magnetizing inductor when the switch Qh is turned off is given as: off mh o mh T L nV i , (7) where, Toff is the turn-off time. Similarly, the change of the flyback converter input current ip through a diode is: off dr dr pT L VVdc i  . (8) Based on two slopes of imh and ip, the tailed diode current mode in which the diode current has current tail, when the slope of imh is greater than that of ip: mh drodcmh dr L LnVVL v . (9) In continuous conduction input inductor current mode, when the MOSFET is switched on, the diode Dp is forced into reverse recovery at a high rate of change in the diode current ip. In this tailed mode operation, however, the diode current slowly decreases so that the reverse recovery effect can be minimized. To analyze the flyback converter operation, an open loop duty ratio is obtained from (2) as: odr o hopen nVv nV D  ,, (10) where, input voltage tSinVv sdr  2: dr s ondr hiD T Ti i. , (11) drp iDi ).1(  , (12) where, input current tSinIi sdr  2. Therefore, two currents can be obtained: os so hnVtSinV tSinInV i    2 2, (13) hs os o sp itSinI nVtSinV nV tSinIi                 2 2 12 . (14) The instantaneous powers through the diode Dp and the transformer T2 are calculated by using the input inductance and the magnetizing inductance: ].[ 2 ,up LL LL P drmh drmh pup   , (15) ].[ 2 ,up LL L P drmh mh puh  , (16) where, Lmh and Ldr denote the magnetizing inductance of T2 and input inductance, respectively, and the input total power ].[1 ,,, upPPP puhpuppuin    . On the other hand by employing the open loop duty ratio Dopen, h, two instantaneous powers can be derived by:   hsspdcp itSinIViVP   22. , (17) POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 9 | NUMBER: 2 | 2011 | JUNE © 2011 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 74 pinh PPP  , (18) where }2cos1{ tIVP ssin   . The relations between two inductances and two input average powers of two converters are expressed as: aveh avep mh drmh P P L LL , ,  , (19)           1 , , aveh avep mhdr P P LL . (20) The output currents of the two cells are given by turns ratio: hoh fop ini ini . .  . (21) Since the output load current io may contain only dc and switching frequency components, the harmonic contents for the primary current of the flyback converterI is expressed as: o ss ohopo V IV iii  , (22) xhxf ii ,, , (23) where, x = (2 , 4, 6, etc.) is harmonic order. From (23), the dc-link capacitor current can be estimated as a second harmonic: .2cos)( 2,2,2, tiii hpdc   (24) Therefore, the voltage ripple of the dc-link capacitor is obtained as: t C ii V p hp rippledc   2sin 2 2,2, ,   , (25) where, Cp is the capacitance of the dc-link capacitor. 4. Converter Controllers To control the proposed approach, two control stages are required for PFC and output voltage regulation as shown in Fig. 6. Flyback converter is regulated by a conventional PFC controller which consists of inner input current loop and outer dc-link voltage [13] to obtain high power factor. DC-link voltage is 1,414*Vs, which is better to reduce the voltage across drain-source of MOSFET Qp . Based on the PFC controller, a feedforward control block is added to improve input current shape. Since the open loop duty ratio Dopen,h of the PFC cell is calculated from (10), the final duty ratio for the switch gate input is obtained as pihopenh DDD  ,, (26) where Dpi, is the closed loop duty ratio obtained from SR flip flop current controller. The output Dpi of the S-R flip flop current regulator containing a small amount of variations provides the correction to the final duty ratio. On the other hand, output voltage Vo control is achieved by forward converter. Figure 8 shows a Fuzzy voltage controller with a open loop duty ratio Dopen,h which is calculated similarly to Dopen,p in terms of power ratings of each converter pupodr pupo popen PnVv PnV D . . , . (27) Final duty ratio Dp is obtained by adding the duty ratio Dpi from controller with Dopen,p. The output voltage control response is much faster than single stage scheme since two converters are employed for separate control function. Fig. 6: Converter controllers. 5. Design Example The proposed PFC circuit is designed according to the following parameters:  total output power (Po) = 200 [W],  input voltage (Vs) = 230 [V],  output voltage (Vo) = 48 [V],  line frequency = 50 [Hz],  switching frequency = 37000 [Hz],  output dc capacitance (Co) = 1500 [μF],  transformer turns ratio (n) = 4,41:1. Forward Converter:  power rating = 109,4 [W],  magnetizing inductance (Lmp) = 0,5 [mH], POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 9 | NUMBER: 2 | 2011 | JUNE © 2011 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 75  DC capacitance = 660 [µF]. Flyback Converter:  power rating = 90,6 [W],  magnetizing inductance (Lmh) = 1,2 [mH]. The proposed scheme provides small input inductor since the inductor current depends on, dc-link voltage is smaller so that the voltage stress on the switch of the forward converter is less, the power rating of DC/DC stage is a bit higher than average power due to lower harmonic components, and the diode reverse recovery loss is minimized because of the tailed diode conduction mode. The membership functions of the inputs error, change in error and output are triangular as shown in Fig. 7. Fig. 7: Single stage PFC. Tab.1: FIS rule table. E/ce NB NS ZE PS PB PB NS NS NS NS NB PS ZE ZE ZE NS NS ZE ZE ZE ZE ZE ZE NS PS PS ZE ZE ZE NB PB PS PS PS PS Inference system rule table used for the design of fuzzy controller is shown in Fig. 8. Fig. 8: MATLAB/Simulink model of proposed topology. 6. Simulation and Results The proposed topology is implemented using MATLAB/Simulink is shown in Fig. 8. The results of the proposed topology are shown in Fig. 9, 10 and 11. Unity power factor and tight output voltage (48 V) regulation can be achieved. The dc-link voltage is 1,414*Vs=325 V, and the voltage ripple of the dc-link is 0,4 V which mainly depends on the dc-link capacitance. Two control systems are implemented to prove the proposed scheme 7. Conclusion A parallel-connected single phase power factor correction (PFC) topology using Fuzzy controller for forward converter and a flyback converter has been proposed. It has been shown that output voltage regulation is achieved by DC/DC cell and the input power factor correction is achieved by AC/DC PFC cell. The proposed approach offers the following advantages: smaller size passive components, lower voltage-ampere rating of DC/DC stage, and higher efficiency. Simulation results demonstrate the capability of the proposed scheme. powergui Continuous Voltage Measurement v + - Series RLC Branch 3 Series RLC Branch 2 Series RLC Branch 1 Scope7 Scope6 Scope5 Scope4 Scope1 R5 R1 Mosfet1 g m D S Mosfet g m D S Linear Transformer 1 12 Linear Transformer 12 Fuzzy Logic Controller Diode 6 Diode 5Diode 4 Diode 3 Diode 2 Diode 1Diode Derivative du/dt i +- Current Controller Iref Ia g 100 Constant 1 70 Add2 Add AC Voltage Source POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 9 | NUMBER: 2 | 2011 | JUNE © 2011 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 76 Fig. 9: Source voltage & current. Fig. 10: Output current. Fig. 11: Output voltage. References [1] RAY, F. W.; DAVIS, M. R. The definition and importance of power factor for power electronic converters. Proc. European conference on Power Electronics and Applications (EPE). 1989, pp. 799-805. [2] HUBER, L.; ZHANG, J.; JOVANOVIC, M. M.; LEE, C. F. Generalized topologies of Single-stage input-current-shaping circuits. IEEE Trans. Power Electron. July 2001, vol. 16, pp. 508– 513. ISSN 0885-8993. [3] REDL, R.; BALOGH, L.; SOKAL, O. N. A new family of singlestage isolated power-factor correctors with fast regulation of the output voltage. In: Proc. PESC’94. 1994, pp. 1137–1144. ISBN 07803-1859-5. [4] ERICKSON, R.; MADIGAN, M.; SINGER, S.Design of a simple high power factor rectifier based on the flyback converter. IEEE Applied Power Electronics Conference. 1990, pp. 792-801. [5] CHOE, G.; PARK, M. Analysis and control of active power filter with optimized injection, IEEE Power Electronics Specialists Conference. 1986, pp. 401-409. ISSN 0885-8993. [6] SEN, K. K.; EMANUEL, E. A. Unity power factor single phase power conditioning. IEEE Power Electronics Specialists Conference. 1987, pp. 516-524. [7] TANG, W.; JIANG, Y.; HUA, C. G.; LEE, C. F.; COHEN, I. Power factor correction with flyback converter employing charge control. In Proc. APEC’93. 1993, pp. 293–298. ISBN 0-78030983-9. [8] DANIELE, M.; JAIN, K. P.; JOOS, G. A single-stage powerfactor-corrected AC/DC converter. IEEE Trans. Power Electron. November 1999, vol. 14, pp. 1046–1055. ISSN 0885-8993. [9] JIANG, Y.; LEE, C. F. Single-stage single-phase parallel power factor correction scheme. In: Proc. PESC’94. 1994, pp. 1145– 1151. ISBN 0-7803-1859-5. [10] TABISZ, A. W.; JOVANOVI, M. M.; LEE, C. F. Present and future of distributed power systems. In: Proc. IEEE Appl. Power Electron. Conf. 1992, pp. 11-18. ISBN 0-7803-0485-3. [11] SURANYI, G. The value of distributed power. In: Proc. IEEE Appl. Power Electron. Conf. 1996, pp. 104-110. ISBN 0-78032482-X. [12] MIWA, A. B.; OTTEN, M. D.; SCHLECHT, F. M. High efficiency power factor correction using interleaving techniques. In: Proc. IEEE Appl. Power Electron. Conf. 1992, pp. 557568. ISBN 0-7803-0485-3. About Authors SUBBARAO.M was born in 1982. He received B. Tech from JNTUH in 2000. M. Tech from JNTUA in 2007. He is currently pursuing the Ph.D. Degree at JNTU college of Engineering, Kakinada. His research interests include Power Electronics and Drives. Sai BABU.Ch obtained Ph.D. Degree in Reliability Studies of HVDC Converters from JNTU, Hyderabad. Currently he is working as a Professor in Dept. of EEE in University College of Engineering, JNT University, Kakinada. His areas of interest are Power Electronics and Drives, Power System Reliability, HVDC Converter. SATYANARAYANA.S, obtained Ph.D. Degree in Distribution Automation from JNTU college of Engineering, Hyderabad. His research interests include Distribution Automation and Power Systems. SOBHAN.P.V.S was born in 1977. He received M.E Degree from AU, Vishakapatnam in 2002. He is currently pursuing the Ph.D. Degree at JNTU college of Engineering, Kakinada.