Citations refer to the original publication, not to a Scieee localized version.
Ginés Arteaga, A. J., Peralías Macías, E., Léger, G., & Rueda Rueda, A. (2014). Closed-loop Simulation Method for Evaluation of Static Offset in Discrete-Time Comparators. Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ICECS.2014.7050041
Ginés Arteaga, Antonio José, et al. Closed-loop Simulation Method for Evaluation of Static Offset in Discrete-Time Comparators. Institute of Electrical and Electronics Engineers, 2014. https://doi.org/10.1109/ICECS.2014.7050041.
Ginés Arteaga, Antonio José, Eduardo Peralías Macías, Gildas Léger, and Adoración Rueda Rueda. Closed-loop Simulation Method for Evaluation of Static Offset in Discrete-Time Comparators. Institute of Electrical and Electronics Engineers, 2014. https://doi.org/10.1109/ICECS.2014.7050041.
Ginés Arteaga, A. J. et al. (2014) Closed-loop Simulation Method for Evaluation of Static Offset in Discrete-Time Comparators. Institute of Electrical and Electronics Engineers. Available at: https://doi.org/10.1109/ICECS.2014.7050041.
A. J. Ginés Arteaga, E. Peralías Macías, G. Léger, and A. Rueda Rueda, “Closed-loop Simulation Method for Evaluation of Static Offset in Discrete-Time Comparators,” Institute of Electrical and Electronics Engineers, 2014, doi: 10.1109/ICECS.2014.7050041.
@misc{ginesarteaga2014closedloop,
author = {Ginés Arteaga, Antonio José and Peralías Macías, Eduardo and Léger, Gildas and Rueda Rueda, Adoración},
title = {Closed-loop Simulation Method for Evaluation of Static Offset in Discrete-Time Comparators},
year = {2014},
publisher = {Institute of Electrical and Electronics Engineers},
doi = {10.1109/ICECS.2014.7050041},
url = {https://doi.org/10.1109/ICECS.2014.7050041}
}
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