elec onics
A icle
Fine-G ain Ci cui Ha dening Th ough VHDL
Da a ype Subs i u ion
Ma ia Muñoz-Quijada, Samuel Sanchez-Ba ea, Daniel Vela-Calde on and
Hipoli o Guzman-Mi anda ∗
Depa men o Elec onic Enginee ing, Uni e sidad de Se illa, Camino de los Descub imien os s/n,
41092 Se illa, Spain; [email p o ec ed] (M.M.-Q.); [email p o ec ed] (S.S.-B.);
[email p o ec ed] (D.V.-C.)
*Co espondence: [email p o ec ed]; Tel.: +34-954-481-298
Recei ed: 30 No embe 2018; Accep ed: 23 Decembe 2018; Published: 25 Decembe 2018
Abs ac :
Radia ion e ec s can induce, amongs o he phenomena, logic e o s in digi al ci cui s
and sys ems. These logic e o s co up he s a es o he in e nal memo y elemen s o he ci cui s
and can p opaga e o he p ima y ou pu s, a ec ing o he onboa d sys ems. In o de o a oid his,
T iple Modula Redundancy is ypically used when ull obus ness agains hese phenomena is
needed. When ull iplica ion o he comple e design is no equi ed, selec i e ha dening can be
applied o he elemen s in which a adia ion-induced upse is mo e likely o p opaga e o he main
ou pu s o he ci cui . The p esen pape desc ibes a new app oach o selec i ely ha dening digi al
elec onic ci cui s by design, which can be applied o digi al designs desc ibed in he VHDL Ha dwa e
Desc ip ion Language. When he designe changes he da a ype o a signal o po o a ha dened
ype, he necessa y edundancy is au oma ically inse ed. The au oma ically ha dening ea u es ha e
been compiled in o a VHDL package, and ha e been alida ed bo h in simula ion and by means o
aul injec ion.
Keywo ds: adia ion ha dening; ha dening by design; TMR; selec i e ha dening; VHDL
1. In oduc ion
1.1. Backg ound
Ionizing adia ion a ec s he no mal ope a ion o elec onic ci cui s. Di e en kind o e ec s
may p oduce bo h physical deg ada ion o he componen s, like TID (To al Ionizing Dose) o DD
(Displacemen Damage), o co up ion o he logic alues s o ed in he ci cui , such as SEU (Single
E en Upse ), SET (Single E en T ansien ) o MBU (Mul i-Bi Upse ) [
1
]. The o me ca ego y o
e ec s, known as ha d e o s, a e des uc i e in na u e and mus be p o ec ed agains by using speci ic
echnology app oaches. So e o s, on he o he hand, induce modi ica ions in he in e nal s a es o he
ci cui s, which may o may no hen p opaga e bo h inside he ci cui a chi ec u es and o hei p ima y
ou pu s. E o s p opaga ing o he p ima y ou pu s o a ci cui may escala e o ex e nal sys ems and
p oduce de ice e o s, subsys em ailu es o e en ca as ophic mission ailu es. These so e o s can
be mi iga ed by inse ing logic p o ec ions in he designs [2,3].
1.2. P oblem o In e es
These logic p o ec ions can be inse ed a di e en s eps du ing he design low. Typically, hese
p o ec ions a e inse ed ei he du ing he syn hesis p ocess o jus a e he syn hesis p ocess has
comple ed, bu be o e he placemen and ou ing s eps. These app oaches equi e design eams o
implemen changes o hei design lows, ei he by including speci ic p op ie a y syn hesis ools o
Elec onics 2019,8, 24; doi:10.3390/elec onics8010024 www.mdpi.com/jou nal/elec onics
Elec onics 2019,8, 24 2 o 18
ex a pos -syn hesis ne lis manipula ion so wa e, bo h o which ha e o be adap ed and con igu ed
o he mission equi emen s, which demands ex a e o om he designe s.
When de eloping ha dwa e modules co es ha a e expec ed o need some selec i e p o ec ions,
bu no ull edundancy, i would be desi able o include he in o ma ion on which elemen s should be
ha dened in he module code i sel , in a non-syn hesize -speci ic way, since di e en de elope s and
p ojec s may choose o equi e di e en syn hesis ools. An ideal si ua ion would allow he designe
o easily speci y in he VHDL (Ve y High Speed In eg a ed Ci cui Ha dwa e Desc ip ion Language)
sou ce code which elemen s should be ha dened, wi h minimal code modi ica ions.
1.3. Li e a u e Su ey
The e a e mul iple ypes o p o ec ions ha can be inse ed in a digi al ci cui [
4
], om which
he mos common one is he ull iplica ion o single memo y elemen s, which is known as T iple
Modula Redundancy o TMR. TMR is ypically p e e ed o DMR (Dual Modula Redundancy) since
he o me can de ec and co ec single e o s, bu he la e has only de ec ion, bu no co ec ion
capabili ies. The adeo o his is ha TMR uses mo e a ea and powe (a ound a 3.2
×
ac o , ins ead
o a ~2.1
×
ac o o DMR, compa ed wi h he unha dened design [
5
]). TMR can be applied a bo h
lip- lop le el o module le el, bu DMR is mo e ypically applied a module le el.
Selec i e ha dening is a mo e ecen echnique ha in ol es iden i ying he mos sensi i e
modules o a design ( o example, by means o aul injec ion), and hen applying TMR only o hose
modules. This way, a be e adeo be ween a ea/powe inc ease and e o mi iga ion is achie ed,
since modules ha do no con ibu e much o he A chi ec u al Vulne abili y Fac o (AVF) o he
design [
6
] a e le unmodi ied and hei powe /a ea will no be a ec ed by he a o emen ioned ~3.2
×
ac o [7,8].
Ha dening echniques can be applied du ing he syn hesis p ocess. An example o his a e he
p o ec ions inse ed by some p op ie a y syn hesize s ha allow ha dening o ull modules, o e en
applying local TMR a ibu es o he speci ic signals ha need o be ha dened. The Synopsys Synpli y
p o [9] and Men o P ecision Hi- el [10] syn hesize s a e examples o his.
Ano he way o inse ing mi iga ion schemas in o he designs is o pe o m pos -syn hesis ne lis
manipula ion, o example using so wa e such as he Xilinx XTMR ool [
11
] and he BYU (B igham
Young Uni e si y) EDIF (Elec onic Design In e change Fo ma ) ools [
12
]. The o me allows ull
module ha dening in a Xilinx-speci ic design low, and he la e is a so wa e sui e ha can inse
bo h TMR and DWC (Duplica e Wi h Compa e) o he use -selec ed elemen s. Mi iga ion elemen s
may also be manually inse ed in he pos -syn hesis ne lis , bu his p ocess is e o -p one and hus
no ecommended.
App oaches ha inse p o ec ions du ing he syn hesis p ocess, o jus a e i , wo k a he RTL
(Regis e -T ans e Le el) ne lis abs ac ion le el and hus do no conside physical implemen a ion
aspec s ha may a ec he obus ness o he implemen ed design. Depending on whe he he a ge
echnology on which he digi al design will be implemen ed is an FPGA (Field P og ammable Ga e
A ay) o an ASIC (Applica ion-Speci ic In eg a ed Ci cui ), o he complemen a y app oaches can be
used a he place and ou e le el o imp o e he obus ness o he implemen ed design, o example
physically sepa a ing he edundan copies o a ha dened elemen , which imp o es ole ance o
Domain C ossing E o s (DCE) [
13
]. Fo he ASIC design o he ha dened mic op ocesso HERMES [
14
],
bo h DMR and TMR echniques we e implemen ed, depending on which p ocesso block was o be
ha dened, and he eplica ed edundancy domains we e physically sepa a ed du ing he ci cui layou
design phase. Ano he app oach in ine-g ain echniques is he one p oposed on [
15
], in which
design lip- lops a e eplaced by sel -co ec ing ad-ha d by design (RHBD) lip- lops a e syn hesis,
and iplica ion is pe o med on spa ially sepa a ed egions du ing he placemen phase. Fo FPGA
designs, ac ions can be aken du ing he placemen and ou ing implemen a ion s ages, such as
inse ing edundan ou ing connec ions [
16
] o using eliabili y-o ien ed place and ou e algo i hms
o physically sepa a e he edundan copies and a oid single poin s o ailu e [
17
]. Unused FPGA
Elec onics 2019,8, 24 3 o 18
esou ces may also be employed o e o de ec ion: [
18
] p oposes he use o ca y p opaga ion chains,
which is a common FPGA esou ce, as a way o c ea e ine-g ained compa a o s o de ec bi upse s,
which is complemen ed by he use o coa se-g ain checke s ha can de e mine whe he he de ec ed
upse s did ac ually p opaga e o he main module ou pu s.
1.4. Scope and Con ibu ion o This Pape
O he p e ious app oaches ha wo k a he RTL ne lis le el, he e is no single app oach ha
allows o bo h easy inse ion o mi iga ions by pe o ming minimal modi ica ions in he HDL code,
and independence om he syn hesis ool. In-code ine-g ain selec ion o which elemen s should be
ha dened, ha p opaga es o bo h a i hme ic/logic ope a ions pe o med, and lip- lops used o s o e
hem, would be desi able.
This pape p oposes a new echnique o pe o ming selec i e, ine-g ain ci cui ha dening, ha
allows designe s o include he in o ma ion on which combina o ial and sequen ial elemen s should
be ha dened in he VHDL code. In o de o be selec i e, he echnique allows designe s o indi idually
choose which elemen s o he VHDL code o ha den. To be use ul o designe s, he echnique only
implies minimal code subs i u ion and does no change he unc ionali y o he design in absence o
so e o s. The echnique is also po able be ween di e en VHDL syn hesize s and does no equi e
he use o pos -syn hesis ools o gene a e he ha dened ne lis .
The di e ence be ween he p oposed echnique and p op ie a y app oaches such as [
9
–
11
] is
ha he p oposed echnique can be used ac oss di e en syn hesize s. Also, while [
11
] mus ha den
comple e modules, ou echnique allows selec ion o which elemen s a e o be ha dened.
Since VHDL allows o bo h Beha io al and RTL desc ip ions, he echnique can wo k a bo h
abs ac ion le els and hus i s scope does no include physical layou echniques, bu i can be
complemen ed wi h hem.
1.5. O ganiza ion o he Pape
The pape is s uc u ed as ollows: Sec ion 2desc ibes he p oposed app oach, wi h he de eloped
da a ypes and ope a o s. Sec ion 3desc ibes how he app oach was e i ied, bo h in simula ion,
o check unc ional co ec ness o he ha dened designs, and by means o aul injec ion, o check he
co ec ness o he p o ec ion implemen a ions. Finally, he discussion and conclusions a e p esen ed in
Sec ion 4.
2. The T iple_logic Package
In his a icle, we p opose a new app oach o implemen ine-g ain ci cui ha dening o digi al
designs by jus changing he da a ype o he objec o be ha dened. By changing he objec ypes,
he implemen a ion changes acco dingly o in oduce he desi ed edundancy. The designe can hen
selec which nodes o he ci cui should be ha dened, hus c ea ing edundancy domains o he c i ical
pa s o he design. Figu e 1shows a edundan b anch o a design, and ep esen s g aphically how
o pass om a non-ha dened domain o a ha dened domain, whe e edundan ope a ions and da a
s o age a e pe o med, and back o he non-ha dened domain. I mus be no ed ha , in his con ex ,
domain c ossing e e s o use da a passing om he non-ha dened o he ha dened domain o ice
e sa, and no o he p opaga ion o e o s be ween edundan copies o he design elemen s.
We ha e compiled all he new da a ypes and ha dening unc ionali y in a VHDL package o
ease o use and minimal VHDL code modi ica ion. An impo an ea u e o he package is a oiding
he scena io p esen in Figu e 2, whe e he obus ness o he ha dened domain is jeopa dized by a
Single Poin o Failu e in oduced by p ema u e o ing inside he ha dened domain. To a oid his
si ua ion, ansi ions be ween ha dened and non-ha dened domains a e de e mined by he da a ypes
o he in e ening ope ands. Fo example, i an ope a ion ecei es wo ha dened ope ands and mus
e u n a non-ha dened esul , a o e will be inse ed, bu i he esul da a ype is o a ha dened ype,
no o e will be implemen ed.
Elec onics 2019,8, 24 4 o 18
Figu e 1.
Domain c ossing be ween non-ha dened and ha dened domains. Each elemen in he g aph
may ep esen ei he a combina o ial ope a ion o a memo y elemen . (
A
) Non-ha dened domain.
(
B
) C ossing o ha dened domain. (
C
) Ha dened domain. (
D
) C ossing o non-ha dened domain.
(E) Non-ha dened domain.
Figu e 2. Single Poin o Failu e in oduced inside a edundan domain by p ema u e o ing.
2.1. Da a Types
Be o e implemen ing he au oma ic ha dening unc ionali y men ioned be o e, he new ha dened
da a ypes ha will compose he ha dened domains mus be de ined. Since he mos used s anda d da a
ypes a e based on he
s d_logic
da a ype, de ined in he
s d_logic_1164
package o lib a y
IEEE
,
a
iple_logic
da a ype has been de ined ha comp ises h ee
s d_logic
alues. By de ining a ec o
o
iple_logic
alues, he
iple_logic_ ec o
is c ea ed.
iple_unsigned
and
iple_signed
a e ha dened ec o s wi h nume ic in e p e a ion, jus as hei non-ha dened coun e pa s. Finally,
a
iple_in ege
con ains h ee in ege s, whose ange can be pa ame ized i using he IEEE
S d.1076-2008 e ision o he language, mo e widely known as VHDL-2008 [
19
]. Table 1shows
he equi alence be ween ha dened and non-ha dened da a ypes.
The package de ines logic and a i hme ic ope a o s o he new da a ypes, and o mixed
ope a ions be ween hese and he al eady exis ing ones. The ope a o and unc ion o e load capabili y
o VHDL will allow an ope a ion ( o example, a sum) o ecei e any combina ion o da a ypes in i s
inpu and e u n ope ands, and he ele an implemen a ion will be au oma ically selec ed depending
on he ac ual da a ypes.
Elec onics 2019,8, 24 5 o 18
Table 1. Equi alence be ween non-ha dened and ha dened da a ypes.
Non-Ha dened Ha dened
s d_logic iple_logic
s d_logic_ ec o iple_logic_ ec o
unsigned iple_unsigned
signed iple_signed
in ege iple_in ege
2.2. Ha dened o Non-Ha dened Domain C ossing
Once all da a ypes and ope a ions ha e been de ined, special conside a ion mus be aken in o
how o pass da a be ween he non-ha dened and ha dened domains. The unc ion/ope a o o e load
capabili y o VHDL allows o his domain c ossing o be pe o med au oma ically o all ope a o
esul s, bu when making a single assignmen wi hou any ope a ions his canno be au oma ically
done, as VHDL is s ongly yped and hus he assignmen ope a o canno be o e loaded. We ha e
de eloped wo unc ions o hese cases: a
o e()
unc ion o pass om he ha dened domain o
he non-ha dened domain (Figu e 3), and a
iple()
unc ion o pe o m he opposi e ope a ion
(Figu e 4).
Figu e 3. G aphic illus a ion o o e() unc ion.
Figu e 4. G aphic illus a ion o iple() unc ion.
Bo h unc ions,
o e()
and
iple()
, a e o e loaded so ha he use can pass e e y equi alen
da a ype om he non-ha dened domain o he ha dened domain, and ice e sa, wi h he same
wo unc ions.

Elec onics 2019,8, 24 6 o 18
2.3. De eloped Func ionali y
A e he de elopmen o he da a ypes and he
o e()
and
iple()
unc ions, logic, a i hme ic
and compa ison ope a o s we e de eloped o hese da a ypes.
2.3.1. Ope a o Lis
The ope a o s de eloped o he ha dened da a ypes a e logic (AND, NAND, OR, NOR, XOR,
XNOR), compa ison (= [is equal], /= [is no equal], > [g ea e han], >= [g ea e o equal], < [lowe
han], <= [lowe o equal] and a i hme ic ope a o s (+ [addi ion], - [subs ac ion], * [mul iplica ion],
/ [di ision]). Since no e e y ope a o is a ailable o e e y non-ha dened da a ype ( o example,
s d_logic_ ec o
does no ha e nume ical in e p e a ion, and in ege s do no suppo bi wise
ope a ions), no all ope a o s ha e been implemen ed o all da a ypes. The lis o implemen ed
ope a o s is shown in Table 2.
The assignmen ope a o (<= o signals, := o a iables) may no be o e loaded since VHDL is
s ongly yped.
Table 2. Lis o implemen ed ope a o s.
Da a ype Logic Equali y/Inequali y Res o Compa ison Ope a o s A i hme ic
iple_logic yes yes yes no
iple_logic_ ec o yes yes no no
iple_unsigned yes yes yes yes
iple_signed yes yes yes yes
iple_in ege no yes yes yes
2.3.2. Ope a o Va ian s
Due o ope a o o e load, o each o he ope a o s, we ha e de eloped a numbe o a ian s.
This way, domain c ossing is pe o med by au oma ically choosing he app op ia e ope a o a ian ,
which is done by he syn hesis ools and simula o s. Fo example, he s a emen A <= B + C will assign
a ha dened o non-ha dened alue o A depending on i s da a ype. Fo una y ope a o s, he e a e ou
combina ions acco ding o whe he he ope and and esul a e ha dened o no . Fo bina y ope a o s,
he e a e eigh possibili ies. All hese possibili ies a e shown in Table 3. O cou se, he possibili ies ha
co espond o all alues in he non-ha dened domain a e al eady de ined in he
s d_logic_1164
o
nume ic_s d packages so hey do no need o be de ined again.
Table 3. Ope a o Va ian s.
Una y Ope a o s
Ope and Resul
unha dened unha dened
unha dened ha dened
ha dened unha dened
ha dened ha dened
Bina y Ope a o s
Le Ope and Righ Ope and Resul
unha dened unha dened unha dened
unha dened unha dened ha dened
unha dened ha dened unha dened
unha dened ha dened ha dened
ha dened unha dened unha dened
ha dened unha dened ha dened
ha dened ha dened unha dened
ha dened ha dened ha dened
Elec onics 2019,8, 24 7 o 18
The cu en implemen a ion o he ha dening unc ionali y includes all ope a o a ian s in he
same VHDL ile, bu hose ope a o a ian s could also be sepa a ed in o di e en iles, in case he
designe wan s o au oma e domain c ossing in one di ec ion bu no on he o he . In ha case,
he unc ions ha au oma ically c oss om he unha dened o he ha dened domain, he unc ions ha
au oma ically c oss om he ha dened domain o he unha dened one, and he unc ions ha ope a e
only on he ha dened domain would be de ined in di e en iles. This way, he use could choose one
o hese ou possibili ies, depending on which iles a e included:
1.
Au oma ically c oss domains om he unha dened o he ha dened one, bu manually use he
o e() unc ion o go back o he unha dened domain.
2.
Au oma ically c oss domains om he ha dened o he unha dened one, bu manually use he
iple() unc ion o go back o he ha dened domain.
3.
Au oma ically pe o m all domain c ossing ope a ions. In his case, quali ied exp essions o
VHDL may be needed o sol e ambigui y in some cases. Fo example, he s a emen
B <= no
(no A);
becomes ambiguous, because e en i A and B a e known ypes, he inne mos
no
ope a o does no know whe he i should e u n a ha dened o unha dened esul . This is
esol ed by speci ying he desi ed e u n ype o he in e media e ope a ions, o example:
B <=
no s d_logic’(no A);.
4. Manually pe o m all domain c ossing ope a ions.
2.3.3. Ha dening Fini e S a e Machines
Ha dening Fini e S a e Machines (FSMs) is no i ial when FSMs use an enume a ed da a ype,
which is a common p ac ice. A cus om solu ion can be implemen ed o each FSM, by de ining a
decode()
and
iple()
unc ion o he ha dened e sion o hei s a e da a ype. Bo h unc ions
a e used o domain c ossing: when decoding he s a e o he FSM, he i s unc ion e u ns he
co ec s a e, a e co ec ing e o s, and when assigning a new s a e, he second unc ion con e s
he enume a ed cons an o a ha dened alue. This is a needed adeo in o de o ha e ine-g ain
ha dening wi h minimal code modi ica ions, since on e e y possible s a e many signals may be
assigned, and he designe may no wan o ha den all o hem.
These unc ions can be made gene ic o e e y enume a ed da a ype i using VHDL-2008, and can
be used wi h he es o he package when using a VHDL-2008 capable syn hesize . When ull TMR is
no needed in he s a e egis e s, he echnique allows he use o implemen his own EDAC (E o
De ec ion and Co ec ion) unc ions o encode and decode he FSM s a e ins ead o iplica ing i , o
example by de ining he unc ions
encode()
and
decode()
o add Hamming codes o he s a e egis e s.
2.4. Usage Examples
A couple o usage examples ollow. Figu es 5and 6show a ha dened mul iplexe and a ha dened
gene ic-wid h coun e , wi h minimal code modi ica ions, which a e unde sco ed. Fo he designe , i is
clea om he signal and po da a ypes which objec s belong o he ha dened domain.
To p e en he syn hesize om emo ing he edundancy, a ibu es can be applied o he ipled
egis e s. The name o he speci ic a ibu e depends on he chosen syn hesis ool, o example,
when using Synopsys Synpli y he a ibu e
syn_p ese e
can be used, whe eas in Xilinx XST (Xilinx
Syn hesis Technology) he ele an a ibu es a e called keep and equi alen _ egis e _ emo al.
Elec onics 2019,8, 24 8 o 18
Elec onics 2019,xx, 5 8 o 19
De ec ion and Co ec ion) unc ions o encode and decode he FSM s a e ins ead o iplica ing i , o
example by de ining he unc ions
encode()
and
decode()
o add Hamming codes o he s a e egis e s.
2.4. Usage Examples
A couple o usage examples ollow. Figu es 5and 6show a ha dened mul iplexe and a ha dened
gene ic-wid h coun e , wi h minimal code modi ica ions, which a e unde sco ed. Fo he designe , i is
clea om he signal and po da a ypes which objec s belong o he ha dened domain.
en i y mux2 o1 is
po ( inpu _l : in iple_logic;
inpu _ : in iple_logic;
sel : in iple_logic;
ou pu : ou iple_logic);
end mux2 o1;
a chi ec u e a ch o mux2 o1 is
begin
comb: p ocess (inpu _l, inpu _ , sel)
begin
i (sel = ’0’) hen
ou pu <= inpu _l;
else
ou pu <= inpu _ ;
end i ;
end p ocess;
end a ch;
Figu e 5.
Ha dened 2- o-1 mul iplexe . No e ha he equali y compa ison ope a o is o e loaded, so
sel can be compa ed o ’0’.
Figu e 5.
Ha dened 2- o-1 mul iplexe . No e ha he equali y compa ison ope a o is o e loaded, so
sel can be compa ed o ’0’.
Elec onics 2019,xx, 5 9 o 19
a chi ec u e a ch o con pa am is
signal eg_i, p_ eg_i: iple_unsigned (N-1 down o 0);
begin
comb: p ocess ( eg_i, enable, updown)
begin
i (enable = ’1’) hen
i (updown = ’1’) hen
p_ eg_i <= eg_i + 1;
else
p_ eg_i <= eg_i - 1;
end i ;
else
p_ eg_i <= eg_i;
end i ;
end p ocess;
sinc: p ocess (clk, s )
begin
i ( s = ’1’) hen
eg_i <= (o he s => (o he s => ’0’));
elsi ( ising_edge(clk)) hen
eg_i <= p_ eg_i;
end i ;
end p ocess;
da a_ou <= s d_logic_ ec o ( o e( eg_i));
end a ch;
Figu e 6.
Ha dening an N-bi coun e a chi ec u e. No e ha he only modi ica ions a e he change in
he da a ype o he in e nal coun , i s ese alue, and he o ing o he p ima y ou pu , which belongs
o he non-ha dened domain.
To p e en he syn hesize om emo ing he edundancy, a ibu es can be applied o he ipled
egis e s. The name o he speci ic a ibu e depends on he chosen syn hesis ool, o example,
when using Synopsys Synpli y he a ibu e
syn_p ese e
can be used, whe eas in Xilinx XST (Xilinx
Syn hesis Technology) he ele an a ibu es a e called keep and equi alen _ egis e _ emo al.
3. Package Ve i ica ion
To check he co ec beha iou o he package, a numbe o es cases ha e been gene a ed.
Bo h basic unc ionali y and designs o inc easing le els o complexi y ha e been es ed. Syn hesis,
simula ion and aul injec ion esul s ha e been ob ained o e i y ha no only he inse ed p o ec ions
mi iga e e ec i ely agains SEU, bu also ha he added unc ionali y does no change he expec ed
ci cui unc ionali y in he absence o SEU.
Syn hesis has been pe o med wi h Xilinx ISE (In eg a ed Syn hesis En i onmen ) 14.7 and
Synopsys Synpli y 4.2. The simula ions ha e been pe o med wi h Xilinx ISim (ISE Simula o ) e sion
14.7. The aul injec ion campaigns ha e been pe o med wi h he FT-Unshades2 (Faul Tole ance
- Uni e sidad de Se illa Ha dwa e Debugging Sys em) aul injec ion pla o m [
20
], e sion 3.10,
wo king in ASIC mode, which means injec ions a e pe o med in he use lip- lops.
The Yosys Open SYn hesis Sui e [
21
] has been used o o mally e i y design equi alence be ween
he ha dened and non-ha dened e sions o he smalle designs, desc ibed below, such as coun e and
shi eg. The o mal equi alence checke ies o sol e a boolean sa is iabili y p oblem (abb e ia ed
Figu e 6.
Ha dening an N-bi coun e a chi ec u e. No e ha he only modi ica ions a e he change in
he da a ype o he in e nal coun , i s ese alue, and he o ing o he p ima y ou pu , which belongs
o he non-ha dened domain.
3. Package Ve i ica ion
To check he co ec beha iou o he package, a numbe o es cases ha e been gene a ed.
Bo h basic unc ionali y and designs o inc easing le els o complexi y ha e been es ed. Syn hesis,
simula ion and aul injec ion esul s ha e been ob ained o e i y ha no only he inse ed p o ec ions
mi iga e e ec i ely agains SEU, bu also ha he added unc ionali y does no change he expec ed
ci cui unc ionali y in he absence o SEU.
Syn hesis has been pe o med wi h Xilinx ISE (In eg a ed Syn hesis En i onmen ) 14.7 and
Synopsys Synpli y 4.2. The simula ions ha e been pe o med wi h Xilinx ISim (ISE Simula o )
Elec onics 2019,8, 24 9 o 18
e sion 14.7. The aul injec ion campaigns ha e been pe o med wi h he FT-Unshades2 (Faul
Tole ance—Uni e sidad de Se illa Ha dwa e Debugging Sys em) aul injec ion pla o m [
20
],
e sion 3.10, wo king in ASIC mode, which means injec ions a e pe o med in he use lip- lops.
The Yosys Open SYn hesis Sui e [
21
] has been used o o mally e i y design equi alence be ween
he ha dened and non-ha dened e sions o he smalle designs, desc ibed below, such as coun e and
shi eg. The o mal equi alence checke ies o sol e a boolean sa is iabili y p oblem (abb e ia ed
SAT). In his case, he sol e mus check i he e is any inpu combina ion ha would make he ou pu s
o he ha dened and unha dened design di e , and p o e by induc ion ha he design ou pu s will no
di e a any ime in he u u e, o any possible se o inpu ec o s. Fo some o he o he designs, e en
i ull o mal equi alence canno be demons a ed because o hei complexi y, hund eds o induc ion
s eps ha e been pe o med wi hou any equi alence e o being encoun e ed. The simula ions also
show ha he ou pu o he ha dened and unha dened e sions o all designs a e he same, when no
SEU a e being injec ed.
3.1. P imi i e Ve i ica ion
To alida e he smalles package unc ionali y, a numbe o es cases ha e been gene a ed, which
ha e been checked bo h in simula ion, checking co ec beha iou agains ansien e o s, and by
e iewing he gene a ed ne lis opologies. To check he p imi i es, syn hesis has been pe o med wi h
he XST syn hesize , bu esul s a e expec ed o be ep oducible wi h any o he VHDL syn hesize . No
op imiza ion o he inse ed p o ec ions has been de ec ed when syn hesizing wi h XST, bu in he
case o hese op imiza ions happening wi h o he syn hesize s, VHDL a ibu es can be added o he
ha dened signals o a oid emo al o he ha dening elemen s. Figu es 7and 8show he syn hesized
ne lis and a sho simula ion o one o he de eloped p imi i es.
Figu e 7. In e nal logic s uc u e o AND ga e wi h igh po ha dened.
Figu e 8.
Simula ion esul s o AND ga e wi h igh po ha dened, wi h a ansien e o in i s
igh inpu .
Elec onics 2019,8, 24 16 o 18
Finally, he powe consump ion inc ease o he ha dened designs is in line wi h wha is expec ed,
acco ding o he a ea inc ease o each design and an expec ed mul iplica ion by a ~3.2 ac o o each
iplica ed elemen .
4. Conclusions
A new app oach o implemen ine-g ain ci cui ha dening, using da a ype subs i u ion, has been
de eloped and alida ed. As a esul , a VHDL package o selec i e ci cui ha dening by design
has been de eloped as a new ool o mi iga ing so e o s on digi al ci cui s, wi h minimal code
modi ica ions. The designe only has o selec which signals o po s should be ha dened and change
hei da a ype acco dingly. Some use o he
iple()
and
o e()
unc ions can be needed because o
he s ongly ypedness o VHDL.
An in e es ing ea u e o his way o pe o ming ha dening by design is ha he designe , a e
iden i ying he c i ical elemen s o his/he design using aul injec ion o o he app oaches, can embed
in he sou ce code o he module he in o ma ion o which elemen s should be p o ec ed, hus
elimina ing he need o con igu e a second ool (such as a pos -syn hesis ne lis p ocesso ) wi h
he esul s o he ulne abili y analysis.
Collabo a ion wi h syn hesis ool endo s would imp o e he pe o mance o he package o
a oid some unwan ed op imiza ions ha may happen when pe o ming mul iple passes du ing he
syn hesis p ocess, o example, when TMR lip- lops ha would no be op imized, because co ec
signal a ibu es ha e been used, ge con e ed o SRL16 p imi i es (Lookup ables used as Shi
Regis e s) which in u n ge op imized away. Ano he case o his is when ha dened po s o in e nal
modules ge op imized by he syn hesize , because he a ibu es o a oid edundancy emo al ha e
been applied in he w ong objec , since some syn hesize s equi e hese a ibu es o be placed in
he po s o p ese e, and o he s equi e hem o be placed in he a ec ed a chi ec u e. The ideal
si ua ion would be ha he a ibu es ha a oid edundancy emo al could be applied o he ha dened
da a ypes and inhe i ed by all po s, signals and a iables o ha da a ype.
Fu u e wo k may also include implemen ing di e en ha dening schemas by using he da a ype
subs i u ion echnique, such as hamming encoding o FSMs o app oxima e TMR.
5. Licensing
The
iple_logic
package is licensed unde he GNU Lesse Gene al Public License (LGPL) 3.0.
The code can be downloaded om he websi e h p:// u.us.es/ iplelogic .
Au ho Con ibu ions:
Concep ualiza ion, H.G.-M.; me hodology, H.G.-M., M.M.-Q. and D.V.-C.; alida ion and
bug ixing: M.M.-Q., S.S.-B. and H.G.-M., o mal analysis (equi alence checking), H.G.-M.; simula ion, M.M.-Q.,
S.S.-B. and H.G.-M.; aul injec ion, M.M.-Q., D.V.-C.; analysis, M.M.-Q., D.V.-C.; in es iga ion, M.M.-Q., S.S.-B.,
D.V.-C. and H.G.-M.; supe ision, H.G.-M.; p ojec adminis a ion, H.G.-M.
Funding:
This wo k was suppo ed by he Spanish Minis e io de Economía y Compe i i idad, h ough he
p ojec “Diseño de sis emas digi ales obus os en e a adiación median e componen es y ecnologías come ciales”
(RENASER3), p ojec e e ence ESP2015-68245-C4-2-P. This wo k was also pa ly suppo ed by he Eu opean
Commission, h ough he p ojec “VEGAS: Valida ion o Eu opean high capaci y ad-ha d FPGA and so wa e
ools”, p ojec ID 687220.
Acknowledgmen s:
The au ho s would like o hank: Cli o d Wol om Symbio ic EDA o kindly p o iding a
VHDL-capable e sion o he Yosys Open SYn hesis Sui e. Edoua d Lepape, He é Baie and Mohamed Goun a
om NanoXplo e o kindly p o iding a e sion o NanoXmap and p omp ly answe ing ou suppo que ies.
Xilinx Uni e si y P og am (XUP) o kindly p o iding he ISE so wa e. Eu opean Space Agency o unding
he de elopmen o he FT-Unshades2 Faul Injec ion Pla o m (ESA con ac 4200022981/09/NL/JK), which
has been used o alida e he esul s o his wo k. Finally, he au ho s would like o hank José M. Hinojo om
Uni e sidad de Se illa o his suppo wi h mul iple ool se up and licensing issues, and Luis Sanz o his ad ice
on au oma ing he gene a ion o he di e en implemen a ions o he es designs and meaning ul con e sa ions
on how o be e s uc u e he ope a ion o e load capabili ies o he package.
Con lic s o In e es :
The au ho s decla e no con lic o in e es . The ounding sponso s had no ole in he design
o he s udy; in he collec ion, analyses, o in e p e a ion o da a; in he w i ing o he manusc ip , o in he
decision o publish he esul s.

Elec onics 2019,8, 24 17 o 18
Abb e ia ions
The ollowing abb e ia ions a e used in his manusc ip :
ASIC Applica ion-Speci ic In eg a ed Ci cui
AVF A chi ec u al Vulne abili y Fac o
DCE Domain C ossing E o s
DD Displacemen Damage
DMR Dual Modula Redundancy
DWC Duplica e Wi h Compa e
EDAC E o De ec ion And Co ec ion
EDIF Elec onic Design In e change Fo ma
FF Flip- lop
FIFO Fi s In, Fi s Ou
FPGA Field P og ammable Ga e A ay
FSM Fini e S a e Machine
FT-Unshades Faul Tole ance-Uni e sidad de Se illa Ha dwa e Debugging Sys em
HDL Ha dwa e Desc ip ion Language
ISE In eg a ed Syn hesis En i onmen
ISim ISE Simula o
LUT Lookup Table
MBU Mul iple Bi Upse
RHBD Rad-Ha d By Design
RTL Regis e -T ans e Le el
SET Single E en T ansien
SEU Single E en Upse
TID To al Ionizing Dose
TMR T iple Modula Redundancy
VHDL Ve y High Speed In eg a ed Ci cui Ha dwa e Desc ip ion Language
XST Xilinx Syn hesis Technology
Yosys Yosys Open SYn esis Sui e
Re e ences
1. Duzellie , S. Radia ion e ec s on elec onic de ices in Space. Ae osp. Sci. Technol. 2005,9, 93–99. [C ossRe ]
2.
Dominik, L. Sys em mi iga ion echniques o single e en e ec s. In P oceedings o he 2008 IEEE/AIAA
27 h Digi al A ionics Sys ems Con e ence, S . Paul, MN, USA, 26–30 Oc obe 2008; pp. 5.C.2-1–5.C.2-12.
3.
Kuwaha a, T.; Tomioka, Y.; Fukuda, K.; Sugimu a, N.; Sakamo o, Y. Radia ion e ec mi iga ion me hods o
elec onic sys ems. In P oceedings o he 2012 IEEE/SICE In e na ional Symposium on Sys em In eg a ion
(SII), Fukuoka, Japan, 16–18 Decembe 2012; pp. 307–312.
4.
Lima-Kas ensmid , F.; Reis, R.A. Faul -Tole ance Techniques o SRAM-Based FPGAs, 1s ed.; Sp inge :
Heidelbe g, Ge many, 2006.
5.
Gomes, I.A.C.; Kas ensmid , F.G.L. Reducing TMR o e head by combining app oxima e ci cui , ansis o
opology and inpu pe mu a ion app oaches. In P oceedings o he 2013 26 h Symposium on In eg a ed
Ci cui s and Sys ems Design (SBCCI), Cu i iba, B azil, 2–6 Sep embe 2013; pp. 1–6.
6.
Nai , A.A.; Eye man, S.; Eeckhou , L.; John, L.K. A i s -o de mechanis ic model o a chi ec u al
ulne abili y ac o . In P oceedings o he 2012 39 h Annual In e na ional Symposium on Compu e
A chi ec u e (ISCA), Po land, OR, USA, 9–13 June 2012; pp. 273–284.
7.
Ma inez-Al a ez, A.; Cuenca-Asensi, S.; Res epo-Calle, F.; Pin o, F.R.P.; Guzman-Mi anda, H.; Agui e,
M.A. Compile -Di ec ed So E o Mi iga ion o Embedded Sys ems. IEEE T ans. Dependable Secu . Compu .
2012,9, 159–172. [C ossRe ]
8.
Guzmán-Mi anda, H.; Ba ien os-Rojas, J.; López-González, P.; Baena-Lecuye , V.; Agui e, M.A. On he
S uc u al Robus ness Assessmen o Wi eless Communica ion Sys ems o In a-Sa elli e Applica ions.
IEEE T ans. Nucl. Sci. 2014,61, 3244–3249. [C ossRe ]
9. Synopsys. FPGA Syn hesis A ibu e Re e ence Manual; Synopsys: Moun ain View, CA, USA, 2018.
Elec onics 2019,8, 24 18 o 18
10.
P ecision Hi-Rel Syn hesis So wa e. A ailable online: h p://www.men o .com/p oduc s/ pga/syn hesis
(accessed on 20 Decembe 2018).
11.
Xilinx. TMRTool Use Guide. A ailable online: h ps://www.xilinx.com/suppo /documen a ion/use _
guides/ug156- m ool.pd (accessed on 20 Decembe 2018).
12.
BYU EDIF Tools Home Page. A ailable online: h p:// eliabili y.ee.byu.edu/edi / (accessed on
20 Decembe 2018).
13.
Quinn, H.; Mo gan, K.; G aham, P.; K one, J.; Ca ey, M.; Lundg een, K. Domain C ossing E o s: Limi a ions
on Single De ice T iple-Modula Redundancy Ci cui s in Xilinx FPGAs. IEEE T ans. Nucl. Sci.
2007
,54,
2037–2043. [C ossRe ]
14.
Cla k, L.T.; Pa e son, D.W.; Ramamu hy, C.; Holbe , K.E. An Embedded Mic op ocesso Radia ion
Ha dened by Mic oa chi ec u e and Ci cui s. IEEE T ans. Compu . 2016,65, 382–395. [C ossRe ]
15.
Hindman, N.D.; Cla k, L.T.; Pa e son, D.W.; Holbe , K.E. Fully Au oma ed, Tes able Design o Fine-G ained
T iple Mode Redundan Logic. IEEE T ans. Nucl. Sci. 2011,58, 3046–3052. [C ossRe ]
16.
Kas ensmid , F.L.; Filho, C.K.; Ca o, L. Imp o ing Reliabili y o SRAM-Based FPGAs by Inse ing Redundan
Rou ing. IEEE T ans. Nucl. Sci. 2006,53, 2060–2068. [C ossRe ]
17.
S e pone, L.; Violan e, M. A new eliabili y-o ien ed place and ou e algo i hm o SRAM-based FPGAs.
IEEE T ans. Compu . 2006,55, 732–744. [C ossRe ]
18.
Naza , G.L.; Ca o, L. Fas e o de ec ion h ough e icien use o ha dwi ed esou ces in FPGAs.
In P oceedings o he 2012 17 h IEEE Eu opean Tes Symposium (ETS), Annecy, F ance, 28–31 May 2012;
pp. 1–6.
19.
IEEE S anda d VHDL Language Re e ence Manual. In IEEE S d 1076-2008 (Re ision o IEEE S d 1076-2002);
IEEE Compu e Socie y: New Yo k, NY, USA, 2009; pp. 1–626.
20.
Mogollon, J.M.; Guzmán-Mi anda, H.; Nápoles, J.; Ba ien os, J.; Agui e, M.A. FTUNSHADES2: A no el
pla o m o ea ly e alua ion o obus ness agains SEE. In P oceedings o he 2011 12 h Eu opean Con e ence
on Radia ion and I s E ec s on Componen s and Sys ems, Se illa, Spain, 19–23 Sep embe 2011; pp. 169–174.
21.
Cli o d Wol . Yosys Open SYn hesis Sui e. A ailable online: h p://www.cli o d.a /yosys/ (accessed on 20
Decembe 2018).
22.
VHDL S anda d FIFO. A ailable online: h p://www.dea hbylogic.com/2013/07/ hdl-s anda d- i o/
(accessed on 20 Decembe 2018).
23.
VHDL Implemen a ion o FFT Algo i hm(s). A ailable online: h ps://gi hub.com/ has i/ (accessed on
20 Decembe 2018).
24.
FPGA4s uden . A Low Pass FIR Fil e o ECG Denoising in VHDL. A ailable online: h ps://www.
pga4s uden .com/2017/01/a-low-pass- i - il e -in- hdl.h ml (accessed on 20 Decembe 2018).
25.
I
2
S In e ace Designed o he PCM3168 Audio In e ace om Texas Ins umen s. A ailable online: h ps:
//gi hub.com/wklimann/PCM3168 (accessed on 20 Decembe 2018).
26.
Dal on P ojec , Depa men o Compu e Science, Uni e si y o Cali o nia, “Syn hesizable VHDL Model o
8051”. A ailable online: h p://www.cs.uc .edu/~dal on/i8051/i8051syn/ (accessed on 20 Decembe 2018).
27.
Le eugle, R.; Cal ez, A.; Mais i, P.; Vanhauwae , P. S a is ical Faul Injec ion: Quan i ied E o and
Con idence. In P oceedings o he Design, Au oma ion and Tes in Eu ope Con e ence, Nice, F ance,
20–24 Ap il 2009.
28.
Xilinx. XPowe Analyze . A ailable online: h ps://www.xilinx.com/suppo /documen a ion/sw_
manuals/xilinx14_7/xpa_c_o e iew.h m (accessed on 20 Decembe 2018).
c
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(CC BY) license (h p://c ea i ecommons.o g/licenses/by/4.0/).