DSP and FPGA Based Sys em o Con ol a Wind
Tu bine Gene a o Implemen ing a Va iable
Speed Vec o ial Con ol Me hod
M. Pe ales, F. Ba e o, J.L. Mo a, E. Gal ´
an, J.M. Ca asco and L.G. F anquelo
Dp o de Ingenie ´ıa Elec ´
onica, Uni . de Se illa,
A da Reina Me cedes s/n, 41012-Se illa (SPAIN)
phone: +34-5-4556873; ax: +34-5-4556849;e-mail: [email p o ec ed]
Abs ac — Thepu pose o his pape is o desc ibeaDSP and
FPGAcon ol sys em oimplemen a a iablespeed ec o ial
con ol . Two semi-sys ems, bo h o hem consis ing on a
DSP, a FPGA and A/D, D/A & digi al I/O’s a e used. Each
one will con ol an in e e : The i s in e e implemen s a
a iable speed ec o con ol o he induc ion gene a o and
hesecondonehandle hepowe injec edin o heu ili yg id.
Expe imen al esul swillbeshown o con i m he alidi y o
he p oposed con olle .
I. INTRODUCTION
Many ho izon al axes, g id-connec ed, medium o
la ge scale wind u bines a e egula ed by pi ch
con ol andmos o wind u binesso a buil ha e
p ac ically cons an speed, since hey use an AC
gene a o , di ec ly connec ed o he dis ibu ion
g id, which de e mines i s speed o o a ion.
In he las yea s, a iable speed con ol is been
added opi ch–angle con olled design ([1]–[4]) in
o de o imp o e he pe o mance o he sys em.
Va iable speed ope a ion o a wind u bine has a
numbe o ad an ages: he educ ion o elec ic
powe luc ua ionsbychanges in kine ic ene gy o
he o o , he po en ial educ ion o s essloads on
he blades and he mechanical ansmissions and
he possibili y o une he u bine o local condi-
ions by adjus ing he con ol pa ame e s.
The objec i es o a iable speed con ol sys em
a e summa ized by he ollowing gene al goals:
1. To egula e and smoo h he powe gene a ed.
2. To maximize he ene gy cap u e.
3. To alle ia e he ansien loads h oughou he
wind u bine.
4. Uni y powe ac o in he line side wi h no
ha monics cu en injec ion.
5. To educe he machine o o lux a ligh load
educing co e losses.
Objec i es o he pi ch–angle con ol a e:
1. To pe mi he s a ing blades angle o di e
om heope a ionbladepi changle,henceal-
lowing easie s a ing and op imum unning.
2. O e powe and o e speed can be dissipa ed
h ough o o pi ch egula ion.
The pape desc ibes a digi al con olle based on a
DSP and a FPGA o implemen hese con ol poli-
cies. The con olle has been e alua ed using a
he es ig including he powe ci cui s and he
con ol s a egies, ha will be desc ibed la e . The
pape hasbeeno ganizedin he ollowingsec ions:
sec ion wo desc ibes es ig implemen a ion and
con ol algo i hms applied o he induc ion gene -
a o . Nex sec iondesc ibes heimplemen a iono
he p oposed con olle . Sec ion ou shows some
expe imen al esul con i ming hepe o manceo
he p o o ype and inally, will be gi en some con-
clusions.
II. TEST-RIG DESCRIPTION
A. Powe Ci cui s
Figu e 1 shows he powe and con ol sys ems o
he es - ig. In ha igu e, wo subsys ems can be
ound: he DC mo o and he AC gene a o con-
ol. The DC mo o is con olled by a comme cial
hy is o ull b idge ec i ie wi h i s con ol sys-
embased ona mic ocompu e . In o de ocon ol
1
heinduc iongene a o , woin e e connec edby
a DC–Link capaci o ha e been used. The i s one
wo ks as a con olled ec i ie and he second one
handles he powe injec ed in o he u ili y g id.
The o e all sys ems is con olled using a pe sonal
compu e we e hewind u binemodelwasimple-
men ed by so wa e. In igu e 2 is shown he Tes –
Rig gene al iew. Cu en con olled DC mo o
000
00
0
00
0
111
11
1
11
1
+DC
AC
AC
DC
AC
DC
Mic ocompu e
Con ol D i e
Signal and Pulse D i e Condi ioning
RS232
PUBLIC GRID
AC GENERATOR DC MOTOR
ENCODER
DSP Con ol Boa d
Pe sonal Compu e
LOAD CELL TORQUE SIGNAL
Figu e 1: Powe and Con ol Diag ams o he Tes -Rig Va iable
Speed Wind Tu bine
Figu e 2: Pho og aph o he es –Rig.
is used o implemen a Va iable Speed and Pi ch-
angle Wind Tu bine. In he wind u bine model
he e e ence o que is compounded o h ee com-
ponen s: ae odynamic, oscilla o y and dynamic
o que which a e calcula ed on he PC. The e e -
ence o queissen o heDCmo o mic ocon olle
om he PC by a RS232 se ial communica ion.
B. Con ol S a egies
The con ol o he induc ion gene a o can be di-
ided in h eepa s: Powe con ol,induc iongen-
e a o con ol and powe injec ed in o he u ili y
g id con ol.
Powe Con ol Block: The powe con ol block
implemen s di e en con ol policies depending
on he wind speed and pi ch–angle posi ion. The
con ol policies a e o que, o o speed o powe
cons an e e ence.
Induc ion Gene a o Con ol Block:This con ol
is based on an indi ec ec o me hod ([5]). The
well known block diag am o his con ol sys em
is shown in igu e 3. The o o speed is added o
slip speed o ob ain he synch onous speed o he
e e ence ames:
!
e
=
p
2
!
+
KCV i
q
(
1
)
!
e
is he synch onous equency.
p
is he pole numbe .
!
is he mechanical equency.
KCV
is a ec o con ol cons an .
In ha e e ence ame, he o que and lux con ol
is pe o med. A Space Vec o echnique is used
o con ol he induc ion gene a o cu en . This
cu en con ol has been implemen ed in a syn-
ch onous e e ence ame.
Fuzzylogic echniques ([6])a e beenimplemen ed
in o de o imp o e speed con ol. In a u u e,
uzzy sel uningcon ol sys em o Induc ion gen-
e a o will be used ([7]).
Con ol o he Powe Injec ed o he Public G id:
The DC–linkcapaci o s ol agemus becon olled
o main ain a cons an e e ence ol age. This is
pe o med, injec ing he ac i e powe deli e ed o
he induc ion gene a o . The con ol block dia-
g am is ep esen ed in igu e 4. A space ec o
θ
ENCODER
GENERATOR
+
KCV ωω
ω
cos
sen θ
θ
iq
d
i
S
1
SENSE
CURR.
MEASUR.
sl e
CURRENT
S. V.
CONTROL
SPEED
Figu e 3: Indi ec Vec o Con ol Me hod Block Diag am.
echnique is used o con ol he cu en injec ed
in o he u ili y g id. In his case, cu en con ol
has been implemen ed in a s a iona y e e ence
ame.
2
θ
+
SENSE
-
+
+
+
V
P I icapac.
UTILITY GRID
POWER
CALC.
POWER
CALC.
S. V.
CURRENT
CONTROL
CURR.
SENSE
VOLT.
SENSE
VOLT.
Figu e 4: Public G id cu en injec ionBlock Diag am.
III. CONTROLLER IMPLEMENTATION
In his sec ion i will desc ibe he con ol sys em
physically. The sys em i sel is composed o wo
semi-sys ems, each one con olling a h ee-phase
ull-b idge in e e , linked oge he h u a Dual-
Po Ram. in he Figu e 5 we can see a global
desc ip ion o his sys em: In his igu e, he main
Con ol LinesCon ol Lines igge
igge
UTILITY GRID (SLAVE)GENERATOR ( MASTER)
RS- 232
DSP- 1
DP- RAM
F.P.G.A.
P.P.I.
32 bi
ROM
32 bi
RAM U.A.R.T.
12- bi
DAC.
Con .
MUX 4:1
12 bi
A/ D
MUX 4:1
12 bi
A/ DA/ D
12 bi
MUX 4:1
DSP- 2
TMS320C30
DP- RAM
F.P.G.A.
P.P.I.
32 bi
ROM
32 bi
RAM
U.A.R.T.
12- bi
DAC.
Con .
MUX 4:1
12 bi
A/ D
MUX 4:1
12 bi
A/ DA/ D
12 bi
MUX 4:1
TMS320C30
WATCH
DOG DOG
WATCH
Figu e 5: O e iew o he con ol sys em implemen ed.
componen s a e shown. They a e: a TMS320C30,
40 MHz DSP, a FPGA as co-p ocesso , a 8255 PPI,
a 16552DUART, a Wa chDog module, a Dual Po
RAM o p o ide communica ion be ween sub-
sys ems,and 32 bi RAM and EPROM. Due o eal
ime p ocess equi emen s, and con ol wo com-
plex sys ems ( wo in e e s) a loa ing poin DSP
was chosen. The FPGA used in he design was
he TPC1020BFN-068C, and pe o m he ollow-
ing asks: in e up handling, add ess gene a ion,
speed encode ead, and managing igge s o he
in e e .
IV. EXPERIMENTAL RESULTS
In hissec ion expe imen al esul sob ainedo he
es - igp o o ypea e analyzed oe alua e hepe -
o mance o he p oposed con olle based on a
DSP and FPGA. Fig. 6 show oscillog ams o he
injec ed cu en in he public g id in nominal con-
di ions using he p oposed con ol boa d, and he
mo o cu en . Fig 7 show oscillog ams o he dc
link capaci o ol age ipple, and he cu en in-
jec ed in he public g id. I should be no ed ha
he oscillog am o he dc ol age has been magni-
ied in o de o obse e i s ipple (600 V DC le el
agains 15 V pp). Fig 8 show oscillog ams o he
gene a o cu en and he o o speed o a s ep
loadchange om5kW o2kWo hewindpowe .
The inal o se , due o an unadjus ed cons an on
he PI, is being co ec ed. Fig 9 show oscillog ams
o hegene a o cu en and i s speed, when accel-
e a ing om 0 o 1500 pm.
Figu e 6: Oscillog amso he injec edcu en in hepublic g id
(channel 1) and he gene a o cu en (channel 2) in nominal
condi ions (1500 pm 380 V). Channel 1 10A/di , channel 2
5A/di and 10ms/di .
Figu e 7: Oscillog ams o he dc link capaci o ol age ipple
(channel 1),and hecu en injec edin he publicg id (channel
2) innominal condi ions (1500 pm 380V). Channel1 10V/di ,
channel 210A/di and 20ms/di .
3
Figu e 8: Oscillog ams o he gene a o cu en and he o o
speed o a s ep load change om 5 kW o 2 kW o he wind
powe . Channel110A/di ,channel2500 pm/di and1s/di .
Figu e 9: Oscillog amso he gene a o cu en (channel 1)and
i s speed (channel 2), when accele a ing om 0 o 1500 pm.
Channel 1 20A/di , channel 2 250 pm/di and .2 s/di .
V. CONCLUSIONS
A con ol boa d based on a DSP and FPGA is
p oposed in his pape in o de o e alua e some
con ol policies o wind-ene gy con e sion sys-
ems. To con i m he alidi y o he p opose con-
ol boa d and he con ol s a egies a es ig p o-
o ype has been buil in he labo a o y. A cu en
con olled DC mo o has been used o implemen
a model o a iable speed and pi ch-angle wind
u bine. The DC mo o has been used o d i e
an induc ion gene a o . The con ol o he gen-
e a o has been implemen ed using ec o con ol
me hod and space ec o cu en con ol. P elim-
ina y expe imen al esul s con i ming he alidi y
o hecon olme hodp oposedin he es – igha e
been shown.
ACKNOWLEDGMENT
This wo k has been suppo ed by he Fi s Use
P og am (FUSE) included in he ESPRIT p ojec ,
en i led “DSP-Based con ol o a iable speed
wind u bine” expe imen numbe 2063.
REFERENCES
[1] R. Da idRicha dson andGe ald M. McNe ney, “Wind En-
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1993.
[2] M. Godoy Simoes, Bimal K. Bose, “Fuzzy Logic Based In-
elligen con ol o a Va iable Speed Cage Machine Wind
Gene a ion Sys em”. IEEE, 1995.
[3] To bjon n Thi inge and Jan Linde s, “Con ol by Ro o
Speed o a Foxed–Pi ch Wind Tu bine Ope a ing ina Wide
Speed Range”. IEEE/PES Summe Mee ing, Sea le, 1992.
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Englewood Cli s, N. J., 1987.
[6] E. Gal ´
an, F. Ba e o, M. A. Agui e, A. To alba, L. G.
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based on Fuzzy Reasoning”, IAS–93 Annual Mee ing,pp
2055–2058,To on o 1993.
[7] F. Ba e o, E. Gal ´
an, A. To alba, L. G. F anquelo, “Fuzzy
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1995.
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