Abs ac
This pape desc ibes a no el cell used in ci cui s wi h
Floa ing Ga e MOS ansis o s (FGMOS) o compensa e
a ia ions in he de ice e ec i e h eshold ol ages caused
by he apped cha ge a he loa ing ga e. The pe o mance
o he ci cui is illus a ed wi h expe imen al esul s showing
a esidual e o below 1%. This coa se compensa ion makes
possible o educe cha ge e ec s o he same o de o
magni ude han he con en ional misma ching in no mal
MOS ansis o s.
Key wo ds: FGMOS analog ci cui s, Floa ing ga e cha ge
co ec ion.
1. In oduc ion
Impo an d i e s o mic oelec onics in he las yea s
has been low powe and low ol age po able sys ems
ma ke . The in e es o IC designe s has ocused in he
de elopmen o digi al and analog echniques in ended o
minimize bo h powe and ol age supply. Among he
analog me hods, he use o he Floa ing Ga e MOS
ansis o has eme ged as one o he mos p omising and
challenging as well [1]. Wo king wi h FGMOS o ces
designe s o ackle wi h se e al p oblems ela ed o he
exis ence o he loa ing node. One o i s main
sho comings in he low ol age and low powe con ex has
o do wi h he cha ge ha can s ay apped a he loa ing
ga e du ing he ab ica ion p ocess. This pape p oposes a
ou - ansis o cell which compa es he h eshold ol age
o a no mal MOS de ice wi h he one o an iden ical sized
FGMOS and p o ides an ou pu depending on he alue o
he apped cha ge. Connec ing i o he FGMOS ansis o s
in he ci cui , he change o hei h eshold ol ages caused
by ha e m can be compensa ed. Sec ion 2 will desc ibe
he mos common used echniques o apped cha ge
e asing/p ocessing in FGMOS ci cui s. In Sec ion 3, ou
p oposed ci cui is in oduced and a p ac ical ealiza ion is
epo ed whose expe imen al beha iou is explained in
Sec ion 4.
2. Cha ge Induced Co ec ion Techniques
One o he d awbacks o he use o FGMOS ansis o
has is ha he quan i y o cha ge apped a i s ga e du ing
he ab ica ion p ocess is unknown. This cha ge could be
ei he an ad an age o a disad an age depending on he
applica ion he ansis o is going o be used. The solu ions
designe s ha e adop ed o dealing wi h his p oblem could
be classi ied in: solu ions o ien ed o con ol ha cha ge, as
he unc ionali y o he ci cui is based on i s exac alue,
and solu ions ying o e ase i , since i s p esence could
spoil he block pe o mance. The mos ele an echniques
a e: 1) The use o he unnel e ec and he ho elec on
injec ion [2], [6]. 2) The applica ion o Ul aViole Ligh
(UV) o cha ge cleaning [3], [4]. 3) Fixing an ini ial
elec ical condi ion a he loa ing ga e [5].
The i s echnique con ols he cha ge ei he posi i e o
nega i e. The use o bo h p ocesses ( unnelling and ho
elec on injec ion) allows inc emen o dec emen o
cha ge. They could also be combined wi h he aim o
e asing, bu ha would b ing se e al added d awbacks as
A Cha ge Co ec ion Cell o FGMOS-based Ci cui s
Es he O. Rod íguez-Villegas, Albe o Yú e a, Ado ación Rueda
Ins i u o de Mic oelec ónica de Se illa (IMSE-CNM), Uni e sidad de Se illa,
Edi icio CICA, c/ Ta ia s/n, 41012-SEVILLA, SPAIN.
emails: [email p o ec ed], { ueda, yu e a}@imse.cnm.es
o example he need o addi ional ci cui y as well as he
use o high ol ages. Besides, hey a e no modelled in all
he echnologies. Hence, he i s s ep would be o model
hem, and his is no a simple ask. Only a ew designe s
ha e done i o ce ain echnologies [1].
The cleaning wi h ul a iole ligh is based on he ac
ha when he su ace o any semiconduc o is ligh ened
wi h ligh o any o he elec omagne ic adia ion, pa o i
is e lec ed, pa o i is abso bed, and he es is
ansmi ed. The numbe o abso bed pho ons is
p opo ional o he o al numbe o hem, and he e o e o
he ligh in ensi y. I also depends on he kind o
semiconduc o , wa e leng h o he pho ons and he applied
elec ic ield. When he loa ing ga e is ligh ened wi h UV
ligh , he elec ons apped a he ga e can a el h ough he
po en ial ba ie in he in e ace Oxide/Silicon. The main
d awback his echnique has is ha i depends on he kind
o passi a ion making mo e o less easy o elimina e he
cha ge. Howe e , his is he simples me hod as no ex a
ci cui y is equi ed.
The hi d echnique is e y use ul in ce ain examples
bu i is no as gene al as he UV cleaning. I consis s o
sho -ci cui ing he loa ing ga e o a ce ain alue (VFG(0))
ha would se he wished ope a ing poin o a ce ain
combina ion o inpu s. I would e ol e o a high impedance
s a e a e wa ds [5].
This echnique has a lo o de ac o s among some
FGMOS designe s who hink he ga e is no loa ing any
mo e. Ha ing a swi ch accessing o i has he d awback
ha , e en when his is in a high impedance s a e, he e is a
leakage cu en lowing h ough he swi ch ha will
discha ge he loa ing ga e a e some ime. I would be
needed o e esh he ga e wi h a ce ain equency, in he
o de o kHz. This would no ha e o be a p oblem in digi al
cells ha ca y ou a lo o ope a ions in ha ime. In analog
ci cui s i is no easy o use, hough, as an adequa e ese
con igu a ion has o be ound which makes he ci cui
e ol es as enough a e wa ds.
3. The Ci cui o Cha ge E o Sensing and
Co ec ion
A Floa ing Ga e MOS ansis o (FGMOS)isaMOS
ansis o whose polysilicon ga e, comple ely w apped in
silicon dioxide, has no DC pa h o a ixed po en ial. I can
modula e he channel be ween a sou ce and d ain and
he e o e i can be used in compu a ion. The coupling
capaci o s o he loa ing ga e becomes e ec i e ga es o
he de ice, depending he ga e s eng h upon he capaci o
size [7]. This is ma hema ically desc ibed by eq.(1) which
ep esen s he ol age a he loa ing ga e in an N-inpu
FGMOS ansis o , whose inpu capaci ances and ol ages
a e Ciand Vi, espec i ely, and CGD,CGS and CGB a e he
capaci i e couplings o he o he e minals: d ain, sou ce
and bulk. CTis he alue o he o al capaci ance seen om
he loa ing ga e.
(1)
being,
(2)
The las e m in eq.(1) akes in o accoun he
con ibu ion o he ga e ol age o he cha ge ha can s ay
apped on i du ing he ab ica ion p ocess. I his
exp ession is mapped o he ga e ol age in he cu en law
o a no mal MOS ansis o he new equa ions o he
FGMOS a ise, in which he e m QFG/CTcan be associa ed
o he nominal h eshold ol age, and a new e ec i e one
can be de ined. The la e di e s o he same pa ame e o
VS
VD
VB
Vn
V2
V1
VFG(0)
Fig. 1. Technique o se he ini ial condi ions a
he loa ing ga e.
VFG
Ci
CT
------- Vi
CGB
CT
-----------VB
++
i1=
N
∑
=
CGD
CT
----------- VD
CGS
CT
---------- VS
QFG
CT
-----------
+++
CTCi
i1=
N
∑CGB CGD CGS
+++=
an iden ical MOS ansis o whene e his e m is di e en
om ze o.
The ci cui p esen ed in his pape o cha ge sensing
and co ec ion is d awn in Fig. 2. The basic idea elies on
he compa ison be ween he ga e ol ages o wo
ansis o s, a MOS and a FGMOS, wi h equal aspec a ios
(M1 and M2, espec i ely). I he d ain cu en is he same
in bo h, he ga e ol age will also be he same. A e a ew
basic manipula ions, i he ansis o pai s M1-M2 and M3-
M4 a e iden ical and he de ia ions in he h eshold
ol ages (V h) and cu en ac o (β) o igina ed by
misma ching a e negligible, he VFG2 ol age a he loa ing
ga e o M2 can be exp essed as:
(3)
Subs i u ing he le hand side in eq.(3) by i s exp ession as
unc ion o he ansis o ’s e minal ol ages, he alue o
he apped cha ge a he loa ing ga e could be ob ained as:
(4)
being CGD he ga e o d ain capaci ance o ansis o M2
and Vou 2o ep esen s he alue o Vou 2’s in absence o
apped cha ge. Hence, i and
, o , . The linea
ela ionship in eq.(4) makes possible o sense ∆Qcha ge by
means o a s aigh line cu e. This p ocess is shown in Fig.
3 o he wo s aigh line pa ame e s: slope (m) and o igin
coo dina e (b).
Fo a cons an ol age Vin, he de ia ion o Vou 2 om
i s expec ed nominal alue is:
(5)
This means ha he induced cha ge e o can be measu ed
as a ol age inc emen in he ou pu e minals. Le us
conside now he ci cui in Fig. 4. All he ansis o s ha e
he same sizes, and he inpu capaci ances ha e he same
alues in he wo FGMOS. One o he inpu s in he wo
FGMOS ansis o s (M2 and M5) is connec ed o Vou 2. The
o he h ee a e connec ed o Vin, bu hey could in gene al
ha e di e en ol ages. I we Conside ha he ∆Qinduced
e o is he same in M2 and M5 and he ol age a he
loa ing ga e o he second FGMOS ansis o , VFG5, hen:
(6)
which has a nominal alue, VFG5o, gi en by he i s wo
e ms o he igh hand side in eq.(6), and an e o e m
which is cancelled hanks o he connec ion o he ou pu o
he p e ious block (eq.(5)):
(7)
The ou pu o his block will be he ol age VG6. I s alue
will sense he ol age a VFG5. Hence he e o due o he
apped cha ge a a loa ing ga e can be co ec ed by
connec ing he ansis o o he ou pu o a block like he
VFG2Vin
≈
∆Q
Cox
--------- Vin
Cin
CT
---------Vin
Cou CGD
+()
CT
-------------------------------------Vou 2=––≈
1
Cin
CT
---------
–



Vin
Cou
CT
------------
CGD
CT
------------
+



Vou 2o∆Vou 2
+()–
CGD CGS CGB
,, Cou
«
Cou Cin
=∆Q0=Vou 2oVin
≈
Fig. 2. Basic ci cui o sensing he apped
cha ge.
V
in
M1 M2
M3 M4
V
DD
V
ou 2
(C
ou
)
(C
in
)
Fig. 3. G aphic ep esen a ion o eq. (4) o ex ac
∆
Q
ela ed pa ame e alues.
Vou 2
Vin
b
∆Q
Cox
----------
–
Cin
CT
---------
CGD
CT
-------------+
------------------------------=
m
1
Cin
CT
---------
–
Cin
CT
---------
CGD
CT
-------------+
------------------------------=
∆Vou 2
CT
Cin
-------- ∆Q
Cox
---------
–≈
VFG5
3Cin
CT
----------- Vin
Cin
CT
-------- Vou 2o
Cin
CT
-------- ∆Vou 2
∆Q
CT
--------
++ +==
VFG5o∆VFG5VG6
=+
∆VFG5
∆Q
Cox
---------1Cin
Cin
--------
–


≈0=
one in Fig. 4, in he way ha has been p e iously p esen ed.
The ansis o s in his block ha e o be designed wi h he
same aspec a io as he one’s whose de ia ions a e wan ed
o be co ec ed, and he inpu capaci ances mus be much
la ge han he ga e o d ain pa asi ic.
4. Expe imen al Resul s
To p o e his idea, a ci cui p o o ype has been
ab ica ed and es ed. This p o o ype consis s in wo
ci cui s: one wi h he con igu a ion in Fig. 4, and ano he
wi h he schema ic in Fig 5. The mic o pho og aph o he
chip is shown in Fig. 6. I has been ab ica ed in a 0.8µm,
double polysilicon CMOS echnology. Aspec - a ios o
NMOS ansis o a e (W/L)=(4µm/1µm), while inpu
capaci o s a e equals o 100 F. In he es p ocess, o he
i s con igu a ion, Vin is se o 1.5V. The loa ing-ga e
ol age alues a e sensed h oughou he ga es o M2 and
M6, gi ing he Vou 2 and VG6 signals. The M4 and M7
ansis o s a e equals, so load e ec is he same. The alues
ob ained o he ou pu ol ages a e Vou 2 =V
G6 =1.03V.
These a e nea ly equal, so hese means ha ∆Qis e y low
o his un o echnology. Ci cui in Fig. 5se es us o
p o e eq. (5). A ol age signal, Ve o , has been connec ed
o one o he inpu ga es o M2 and M5. This allows o
gene a e an equi alen e o on bo h ansis o ha will
ep oduce he ∆Qe ec s. The esponses o he wo ci cui s
a e shown in Fig. 7. I can be no iced how Vou 2 is a ec ed
by his e o while VFG6 is nea ly cons an , and equal o he
alue measu ed be o e. This p o es he e o co ec ion
mechanism. The VG6 ol age changes only 1% a ound
1.03V when Ve o goes om 0.4V o 1.5V.
The p oposed cell can be used o cha ge con ol in
con inuous ime FGMOS based il e s, as o example he
epo ed in [8]. Figu e 8 shows he FGMOS e sion o a
ansconduc o . Cha ge apped a each M1 and M2
ansis o s can be cancelled by adding an ex a inpu and
connec ing i o he p oposed cell in his pape . The esul s
o his applica ion example will be shown a he
con e ence (o a he inal e sion o he pape ).
Vin M1 M2
M3 M4
VDD
Vou 2
M6
M5
M8M7
V
G6
VDD VDD VDD
Fig. 4. Ci cui o sensing and compensa ing he
apped cha ge e ec s.
Fig. 5. ∆
Q
simula ion e o ci cui by means o
Ve o
signal in he p oposed con ol es ci cui .
Ve o
Vin M1 M2
M3 M4
VDD
Vou 2
M6
M5
M8M7
V
G6
VDD VDD VDD
Fig. 6. Mic opho og aph o cha ge con ol
ci cui .
5. Conclusions
A ou - ansis o cell, in ended o coa sely co ec
e ec i e h eshold ol age o se s due o apped cha ge
du ing he ab ica ion p ocess in he FGMOS ansis o s has
been p esen ed in his pape . I s unc ionali y has been
p o en The esidual e o a e applying he co ec ion
mechanism become smalle han 1% he alue o he ini ial
induced e o e m in FGMOS de ices wi h W/L=4µm/1µm
and inpu capaci ances in he o de o 100 F.
6. Re e ences
[1] P. Hasle and T. S. Lande: “Special Issue on Floa ing-Ga e
De ices, Ci cui s, and Sys ems,” IEEE T ansac ion on
Ci cui s and Sys ems, Pa II: Analog and Digi al Signal
P ocessing, ol. 48, n. 1, Jan., 2001.
[2] M. Lenzlinge and E. H. Snow, “Fowle -No dheim
unneling in o he mally g own SiO2”, J. Appl. Phys.,
ol.40, no.1, pp. 278-283, 1969.
[3] L. A. Glasse , “A UV w i e-enabled PROM,” Chapel Hill
Con e ence on VLSI (1985), H. Fusch, El. Rock ille, MD:
Compu e Science P ess, pp.61-65, 1985.
[4] D. A. Ke ns, J. Tanne , M. Si ilo i, and J. Luo, “CMOS
UV-w i able non- ola ile analog s o age,” Ad anced
Resea ch in VLSI, C. H. Sequin, Ed. Camb idge, MA:MIT
P ess, pp. 245-261, Uni. o Cali o nia San a C uz, 1991.
[5] K. Ko ani, T. Shiba a, M. Imai, T. Ohmi, “Clock-Con olled
Neu on-MOS Logic Ga es,” IEEE T ansac ions on Ci cui s
and Sys ems-II: Analog and Digi al Signal P ocessing,
ol.45, pp. 518-522, Ap . 1998.
[6] P. Hasle , “Founda ions o lea ning in analog VLSI,” Ph.D.
Disse a ion, Cali o nia Ins i u e o Technology, Pasadena,
CA, 1997.
[7] E. Rod íguez-Villegas: “Low Vol age and Low Powe
Analog and Digi al Design wi h he Floa ing Ga e MOS
ansis o (FGMOS),” Ph.D. Thesis, U. o Se ille, Sep.
2002.
[8] E. Rod íguez-Villegas, A. Rueda, A. Yú e a. “A 1.5V
23MHz Low Powe FGMOS Fil e ” In e na ional
Con e ence on Elec onics, Ci cui s and Sys ems
(ICECS’2001), pp. 337-340, 2001.
[9] B. A. Minch, “Analysis, Syn hesis, and Implemen a ion o
Ne wo ks o Mul iple-Inpu T anslinea Elemen s,” Ph. D.
Thesis, Cal ech, Pasadena, CA, 1997.
1.4
1.41
1.42 1.43
1.44 1.45
1.46 1.47
1.48
1.49 1.5
0.8
0.85
0.9
0.95
1
1.05
1.1
1.15
1.2
V
ou 2
V
G6
1.2
0.8
1.0
Vol age (V)
0.4 1.50.9
(050mV/di )
Ve o (V)
(50mV/di )
Fig. 7. E olu ion o
Vou 2
and
VG6
when a ol age
signal (
Ve o
) is applied o simula ing a ∆
Q
cha ge on
M2
and
M6
loa ing ga es.
VCM
V
CM
V
DD
gnd
Vi2
VCM
V
DD
V
CM
VCM
V
CM
V
DD
gnd
Vi1
VCM
V
DD
V
CM
ISS
Fig. 8.
FGMOS
-based T ansconduc o .
I1I2
Vou
M
1
M
2
V
DD
V
DD