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Smart-Pixel Cellular Neural Networks in Analog Current-Mode CMOS Technology

Abstract

This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. These chips consist of regular arrangements of elementary units, called smart pixels. Light detection is made with vertical CMOS-BJT’s connected in a Darlington structure. Pixel smartness is achieved by exploiting the Cellular Neural Network paradigm [1], [2], incorporating at each pixel location an analog computing cell which interacts with those of nearby pixels. We propose a current-mode implementation technique and give measurements from two 16 x 16 prototypes in a single-poly double-metal CMOS n-well 1.6-µm technology. In addition to the sensory and processing circuitry, both chips incorporate light-adaptation circuitry for automatic contrast adjustment. They obtain smart-pixel densities up to 89 units/mm2, with a power consumption down to 105 µW/unit and image processing times below 2 µs.

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Smart-Pixel Cellular Neural Networks in Analog Current-Mode CMOS Technology

Author: Espejo Meana, Servando Carlos; Rodríguez Vázquez, Ángel Benito; Domínguez Castro, Rafael; Huertas Díaz, José Luis; Sánchez Sinencio, Edgar
Publisher: Institute of Electrical and Electronics Engineers
Year: 1994
DOI: 10.1109/4.297693
Source: https://idus.us.es/bitstreams/59fe024a-04b6-4ed9-97d9-5da1eecc76cc/download
IEEE
JOURNAL
OF
SOLID-STATE
CIRCUITS.
VOL. 29,
NO.
8,
AUGUST
1994
895
Sma -Pixel Cellula Neu al Ne wo ks
in
Analog Cu en -Mode CMOS Technology
S.
Espejo,
A.
Roddguez-Vazquez,
Membe ,
ZEEE,
R. Domhguez-Cas o,
J.
L.
Hue as,
and
E.
Shnchez-Sinencio
Abs ac -This pape p esen s a sys ema ic app oach o design
CMOS chips wi h concu en pic u e acquisi ion and p ocess-
ing capabili ies. These chips consis o egula a angemen s o
elemen a y
uni s,
called
sma pixels.
Ligh de ec ion is made
wi h e ical CMOS-BJT’s connec ed in a Da ling on s uc u e.
Pixel sma ness is achie ed by exploi ing he Cellula Neu al
Ne wo k pa adigm [l], [2], inco po a ing a each pixel loca ion
an analog compu ing cell which in e ac s wi h hose o nea by
pixels. We p opose a cu en -mode implemen a ion echnique
and gi e measu emen s om wo
16
x
16
p o o ypes in a single-
poly double-me al CMOS n-well 1.6-pm echnology. In addi ion
o he senso y and p ocessing ci cui y, bo h chips inco po a e
ligh -adap a ion
ci cui y o au oma ic con as adjus men . They
ob ain sma -pixel densi ies up o
89
uni s/mm2, wi h a powe
consump ion down o
105
pW/uni and image p ocessing imes
below
2
ps.
I.
INTRODUCTION
OMMON a chi ec u es o image-p ocessing sys ems use
C
a
on -end senso y plane wi h digi al-encoding o he
pixel alues, and se ial ansmission o hese digi al da a o
subsequen p ocessing using ei he ASIC’s o gene al-pu pose
compu e s. Con a y o his app oach,
sma -pixel
chips [3]
inco po a e an analog compu ing cell a each senso y poin ,
achie ing high speed and low a ea occupa ion in he combined
senso ylp ocessing unc ions by ully exploi ing
pa allelism.
The combined spa ial dis ibu ion o senso y and p ocessing
ci cui y elimina es he ime equi ed o da a ansmission
om he senso y o he p ocessing plane du ing he image
acquisi ion p ocess. In addi ion, in some image-p ocessing
applica ions, he ele an in o ma ion con ained in he ou pu
image can be desc ibed by
a
educed numbe o a iables,
allowing
a
as downloading o he esul s o subsequen
e alua ion.
CMOS echnologies o e unique ea u es o he design
o sma -pixel chips. On one hand, MOS ansis o ope a ion
unde no mal biasing in s ong in e sion is no d as ically
a ec ed by inciden ligh ; on he o he , pho osensi i e CMOS
de ices can be buil by exploi ing he many junc ion de ices
a ailable in CMOS echnologies [4]. Howe e , p e ious ap-
p oaches o CMOS design o sma -pixel chips lack gene ali y,
as
hey ely on implemen a ion me hods sui able o speci ic
Manusc ip ecei ed Decembe 1993; e ised Ap il
6,
1994.
S.
Espejo,
A.
Rod iguez-VBzquez, R. Domlnguez-Cas o, and
J.
L.
Hue as
a e wi h he Cen o Nacional de
Mic oelec 6nica-Uni e sidad
de Se illa,
Edi icio CICA, Cma ia
sn,
41012-Se illa, Spain.
E. Sinchez-Sinencio is wi h he Depa men
o
Elec ical Enginee ing,
Texas A&M Uni e si . College S a ion. TX
77843
USA.
applica ions. In some cases, he p ocessing- ask pe o med a
each pixel does no imply collec i e compu a ion [3], while
mos o he app oaches o “pixel-sma ness’’ a e based on
ac i e implemen a ions o esis i e-g id ne wo ks [5], [6].
The pa adigm o Cellula Neu al Ne wo ks (CNN) [l], [2]
is
a
e y sui able amewo k o
sys ema ic
design o pa allel
senso y-p ocessing chips. On one hand, CNN’s consis o
egula a angemen s o
cells-
- opologically iden ical o sma -
pixel chips. On he o he , hei cells a e only locally connec ed,
and hus, equi e simple ou ing. Also, he as body o li e a-
u e on CNN heo y and applica ions demons a es ou s anding
ea u es o his pa adigm o a ay-p ocessing [7]. In pa icula ,
esis i e g ids ha e ecen ly been demons a ed
as
a
pa icula
CNN class [8].
No expe imen al sma -pixel CNN chips ha e been epo ed
o da e. This pape ou lines
a
design app oach using Da ling on
pho o ansis o s and cu en -mode p ocessing ci cui y. I is
based on
a
modi ied e sion
o
he o iginal CNN model which
enables op imum speedlpowe and a ea occupa ion in VLSI
design
[9],
[IO]. The senso s include an au oma ic adjus men
ci cui y which ensu es p ope beha io unde di e en illu-
mina ion condi ions. Ou p oposals a e demons a ed ia wo
wo king sma -pixel chips, in
a
single-poly, 1.6-pm, n-well
CMOS echnology. In addi ion o hei op ical inpu , hese
chips exhibi much be e a ea and speed/powe igu es han
p e ious CNN implemen a ions
[
111,
[
121.
Sec ion I1 desc ibes some gene al aspec s o sma -pixel
chips, and Sec ion I11 ou lines he p oposed compu a ion algo-
i hm. Sec ions IV and V discuss he senso y and p ocessing
ci cui y, espec i ely, and he expe imen al p o o ypes a e
desc ibed in Sec ion VI.
11.
SMART-PIXEL
CHIPS
In his pape ,
pixel
deno es he elemen a y senso y uni
used o de ec poin wise ligh signals. These senso y uni s a e
ealized in CMOS echnology using any compa ible junc ion
de ice o gene a e
a
cu en whose alue is an inc easing
unc ion o he ligh in ensi y [3],
[
131,
[
141. The acquisi ion o
wo-dimensional
scenes equi es pixels a anged on o egula
g ids,
as
shown in Fig. 1. Each pixel in his senso y plane
gene a es
a
cu en
I,
which codi ies
a
co esponding poin o
he inpu image, whe e he index
c
(i.,j) indica es he pixel
a he i h ow and j h column on he g id and a ies o e he
whole g id domain
GD(c
E
GD).
Thus, he whole image is
IEEE
Log
Numbe 4402 142;
cap u ed in o
a
ma ix o cu en s
[Ic].
0018-9200/94$04.00
0
1994 IEEE
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896 IEEE JOURNAL
OF
SOLID-STATE CIRCUITS, VOL. 29.
NO.
8, AUGUST 1994
om o he
cells
J
Fig.
1.
Illus a ing he co e a chi ec u e
o
sma -pixel chips.
Fig. 1 illus a es he a chi ec u e o sma -pixel chips: each
uni (also called
sma -pixel
o
cell
)
senses
a
poin o he inpu
image and
in e ac s
wi h he o he uni s in he a angemen o
pe o m pa allel-p ocessing asks on he inpu cu en ma ix
Sma -pixel chips a e o s ong p ac ical in e es o pa e n
[IC].
ecogni ion p oblems, o de ec ea u es o he inpu image. Fo
example, Fig.
2
illus a es he ask o de ec ion o connec ed
componen s (DCC), which consis s o coun ing he numbe
o
Fig.
2.
Connec ed componen de ec ion in ou di e en di ec ions.
-
connec ed pieces encoun e ed by scanning an inpu image in
a
gi en di ec ion [15]. Pa e n ecogni ion can be ealized by
p ocessing he da a ob ained a e pe o ming his ask in he
di ec ions shown in Fig.
2
[16], [17]. This da a is con ained in
a ew ows and columns a he g id bo de s. In addi ion o hei
usage o p ep ocessing asks, sma -pixel chips a e also use ul
as s and-alone uni s o nonin ensi e compu a ion asks such
as hal oning
[
181,
mo ion de ec ion
[
191-[21], ange- inding
[3], e c.
111.
THE CNN PARALLEL PROCESSING PARADIGM
As
Fig.
1
illus a es, sma -pixel CNN chips consis o
egula a angemen s o
iden ical
uni s, each including
a
pho osenso
and an analog compu ing
cell.
Such an en i y
ans o ms he inpu image
[I,]
in o an ou pu ma ix
[y,]
ia
a
dynamic
p ocess o in e ac ions among he compu ing
cells. The dis inc i e ea u e o he CNN pa adigm is ha hese
in e ac ions a e
local,
limi ed o each cell o a educed se o
neighbo s, loca ed wi hin
a
dis ance
T
in he g id. In pa icula ,
he e is
a
wide ca alog o image p ocessing asks a ailable
o ne wo ks whe e pa ame e
T
(called
neighbo hood adius)
is uni y- e y appealing o
VLSI
implemen a ions because
connec ion among uni s
is
made by abu men , equi ing no
ex a ou ing.
The dynamic compu a ion p ocess o CNN's, as p oposed
in [1], in ol es h ee a iables pe cell:
(a)
cell
s a e:
xc( ),
which con eys cell ene gy in o ma ion as a unc ion o ime;
(b) cell
ou pu :
yc( ),
ob ained om he cell s a e ia
a
so -
limi e
piecewise-linea
ans o ma ion,
(1)
Yc
=
(G)
=
;(I.c
+
11
-
15,
-
11)
d awn in Fig. 3(a); and (c) cell
ex e nal-inpu :
U,.
P ocessing
i sel
is
go e ned by a se o coupled nonlinea di e en ial
equa ions, one pe cell. We use equa ions ha di e om hose
o iginally p oposed by Chua-Yang
[
13, and which enable he
op imiza ion o he speedlpowe a io and a ea occupa ion o
VLSI
CNN chips. The p oposed equa ions a e gi en by [9],
[lo]:
dz,
d
-
=-
+
{A,dYd( )
+
&dud)
dE
A',
(c)
Vc
E
GD
(2)
whe e
g(
.)
is a nonlinea dissipa i e e m de ined
as,
m(5,
+
1)
-
1
2,
<
-1
g(z,)
=
.c
o he wise (3)
{
m(5,
-
1)
+
1
5,
>
1
whe e
m
>
1
is a pa ame e o he model. Func ion
g(.)
is
d awn in Fig. 3(b). Summa ions in
(2)
ex end o e he
neigh-
bo hood
o he c h cell, deno ed by
NT(c),
which con ains
adjacen cells loca ed wi hin a dis ance
T
in he g id, and
includes cell
c
i sel .
P ocessing asks pe o med by CNN's a e de e mined by
he
con e gence
o
(2)
o bina y
(y,
=
*l,Vc
E
GD)
equilib ium s a es ollowing he ansien ini ialized by
[xc(
O)],
d i en by
[U,],
and unde he bounda y condi ions imposed
by cells a he ne bo de . Depending on he applica ion, he
cu en
1,
gene a ed a each cell's pho osenso is used as
ini ial alue o he s a e a iable
zc(0)
o as ex e nal inpu
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ESPEJO
e
al.:
SMART-PIXEL
CELLULAR
NEURAL
NETWORKS
IN
ANALOG CURRENT-MODE
CMOS
TECHNOLOGY
(b)
Fig.
3.
CNN cell nonlinea i ies. (a) Ou pu nonlinea i y;
(b)
dissipa i e e m.
U,.
In he la e case, he ini ial s a es a e usually se o
a
cons an alue. The ou come o he ask depends on pa ame e s
Bcd,Acd
and
D,
o
(2),
called
con ol, eedback,
and
o se
pa ame e s, espec i ely, and on he bounda y condi ions.
The con ol and eedback pa ame e s can be a anged in o
ma ices, which p o ide
a
pic o ial iew o he in e ac ions
wi hin each cell’s neighbo hood. Fo uni o m ne wo ks hese
ma ices a e in a ian h oughou he g id domain- hey a e
empla es.
The unc ionali y o uni o m CNN’s is de e mined
by i s con ol,
B,
and eedback,
A,
empla e ma ices, and i s
o se pa ame e ,
D.
Fo illus a ion pu poses, Table
I
sum-
ma izes he empla es used o some signi ican p ep ocessing
asks.
To gua an ee co ec ope a ion o sma -pixel CNN chips,
an impo an ma hema ical issue is o de e mine condi ions o
he empla e pa ame e s ha yield con e gence o he ou pu
ma ix
[yC]
o bina y s a es o any inpu . Such
a
ma hema ical
analysis o he model p oposed in his pape , gi en by (2)
and (3), is ou o his pape ’s scope and has been epo ed
elsewhe e [9] o any
m
2
1.
Ou ci cui s use he pa icula
~
891
TABLE
I
SOME
CNN
TEMPLATES
Applica ion
A
B
D
Noise
Fil e ing
[!
1
PI
[!
!
?I
0
PI
000
010
Hole Filling [28]
Con ex Come s
Ex ac ion [2]
Bo de s
Ex ac ion [2]
Connec ed
Componen
De ec ion [15]
Shadow C ea ion
1291
-11.1
-11.1
-114
2
-114
-11-2
-114
2
-114
-114
-114
-114
-1
-11.1
-3
-1141
-1
14
-1
1.1
-2
0
0
case
m
-+
00,
in which he nonlinea dissipa i e e m o ces
he s a e a iable
zc
o emain wi hin he in e al
[-l>
11.
Consequen ly,
zc( )
=
yc( ),
and he implemen a ion o he
nonlinea ope a o in (1) is no equi ed.
IV.
SENSORY
CIRCUITRY
A.
Pho osenso s
The simples pho osensi i e de ices o CMOS n-well ech-
nologies a e e e se-biased
pho odiodes,
o med ei he di ec ly
be ween n+-di usion and subs a e [3] o be ween well and
subs a e [13]. Cu en le el o bo h de ices is an inc easing
unc ion o he junc ion a ea. In pa icula , we ha e measu ed
cu en s up o
20
nA o well-subs a e pho odiodes wi h well
a ea o 100
x
100pm2, in
a
1.6-pm single-poly echnology,
unde en i onmen al labo a o y ligh ing. This cu en le el
inc eases signi ican ly using
a
e ical CMOS-BJT
as
pho o-
senso . Fig.
4(a)
shows
a
concep ual layou and c oss-sec ion
o his de ice, whose cu en is app oxima ely p opo ional
o he a ea o he wellhubs a e junc ion,
A,
in he igu e.
Cu en gene a ed by his de ice is
p
+
1
imes la ge han
ha
o
a
pho odiode wi h he same well a ea
whe e
IT
deno es he pho o ansis o cu en ,
Il
is he
co esponding cu en o he well-diode, and is he ansis o
cu en -gain; measu ed
in
o his echnology is 37.7
0.8,
basically independen o ansis o geome y [22].
We ha e measu ed cu en s up o 430 30 nA (unde no mal
labo a o y illumina ion) o pho o ansis o s wi h passi a ed
well a ea o
60
x
60pm2.
Consequen ly, and since cu en
and well a ea a e app oxima ely linea ly ela ed, i ex apola es
cu en le els
o
20
nA o minimum a ea de ices (13.6
x
13.6 pm2)-needed o inc eased densi y sma -pixel chips.
Howe e , o some c i ical asks [7] hese le els p o ided by
minimum pho osenso s may no be la ge enough o gua an ee
he
ma ching le el equi ed by he signal p ocessing ci cui y,
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898
IEEE
JOURNAL
OF
SOLID-STATE
CIRCUITS,
VOL.
29,
NO.
8,
AUGUST
1994
I'
I
i
0
0
Fig.
4.
igu a ion
o
wo e ical p-n-p ansis o s.
(a)
CMOS compa ible e ical p-n-p an sis o .
(1
J)
Da
ling on con-
hus equi ing some ampli ica ion. Simples s a egies use
ei he la ge wells o cascaded cu en ampli ie s- e y cos ly
in e ms o a ea occupa ion and, o he la e , inaccu a e. In-
s ead, we use
an
addi ional e ical BJT o achie e Da ling on
ampli ica ion by
a
ac o o
p
+
1,
wi h p ac ically no a ea
o e head. Fig. 4(b) shows he concep ual layou and c oss-
sec ion o his Da ling on pho o ansis o . Cu en o his
de ice is
1,
N
(P
+
1)1T
N
(P
+
1)21w.
(5)
while i s a ea occupa ion is sca cely inc eased by ha o
a
minimum-size e ical BJT. Measu emen s wi h
A,
in
Fig. 4(b) equal o
60
x
60pm2
esul in cu en s up o
18
*
2pA.
Fig.
5(a)
shows he
ou pu
cha ac e is ic measu ed om
a
Da ling on pho o ansis o wi h
A,
=
60
x
60pm2
unde
cons an en i onmen al illumina ion (b igh -cu en ), while
Fig. 5(b) shows he esul ob ained when he en i onmen ligh
is g adually educed o comple e da kness. Da k-cu en was
215+
10
PA, which means ha he b igh - o-da k cu en - ange
is close o
100
dB o en i onmen al labo a o y illumina ion.
The same ange is obse ed o
a
single p-n-p de ice, while
simple pho odiodes yield abou
80
dB. Al hough hese esul s
a e op imis ic in he sense ha in eal images he e will be
(b)
Fig.
5.
Measu ed ou pu cha ac e is ics
o a
Da ling on pho o ansis o wi h
A +
=
GO
x
GO
pm2:
(a)
unde cons an en i onmen illumina ion;
(b)
e ec
o g adual educ ion o illumina ion du ing he sweep o
I
;.E.
no comple ely da k a eas, he b igh - o-da k cu en - a ios
measu ed p o ide
a
wide enough ange o da a acquisi-
ion. The ampli ica ion o he Da ling on s uc u e p o ides
a su icien cu en le el e en i de ice a ea is subs an ially
dec eased.
B.
Au oze o S a egy
Al hough pho osenso s p oduce unidi ec ional cu en low,
double- ail signals a e easily ob ained by bias-shi ing,
as
shown in Fig.
6(a).
Cu en sou ce
ITH
se s he ze o-le el o
he double- ail signal. To gua an ee good con as , i s alue
should be se somewhe e be ween he maximum and he
minimum ligh -induced cu en s among all pho osenso s. I
ligh ing condi ions o all possible inpu scenes a e uni o m
and known
a
p io i,
ITH
can be se o
a
ixed alue. In
a
mo e
gene al case whe e he chip mus handle scenes wi h di e en
ligh ing condi ions, some kind o au o-ze o s a egy mus be
de ised o gene a e
ITH
app oxima ely equal o he a e age
o he pho osenso cu en s o e he whole a ay.
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ESPEJO e
al.:
SMART-PIXEL CELLULAR NEURAL
NETWORKS
IN
ANALOG CURRENT-MODE CMOS TECHNOLOGY
899
(b)
Fig.
6.
cu en
ou pu ;
(b) au o-ze o ci cui y.
Th eshold ci cui y o pho osenso s.
(a)
Bias-shi ing o double- ail
A simple, ye con enien , au o-ze o s a egy uses ou
ex a ansis o s a each senso . Fig. 6(b) shows he schema ic
o
a
senso including he au o-ze o ci cui y. All p-channel
ansis o s ha e equal size; he same applies o n-channel
ansis o s. The low-impedance node labelled
SUM
is
a
global
node, common o all pixels. No e ha he cu en
I,
a he c h
pho osenso is eplica ed wice. One o he eplicas in e aces
he p ocessing ci cui y, while he o he is oo ed o he global-
node
SUM,
and agg ega ed o he emaining senso cu en s.
Thus, calcula ion o he cu en
ITH
h ough ansis o
MTH
ob ains he ollowing
whe e
gOp
is he ou pu conduc ance o he p-channel ansis o ,
gmn
is he ansconduc ance o he n-channel ansis o , and
N
he numbe o pixels. Fo simplici y (6) assumes equal
ansconduc ances and conduc ances o all pixels. The i s
ac o in (6) e lec s he cu en di ision pe o med a node
SUM,
while he second co esponds o he gain
o
he mi o
o med by he pa allel combina ion o he
Msuh
ansis o s
and
MTH.
Assuming
gmn
>>
go,,
(6) gi es
ITH
equal o he
a e age o he pho osenso cu en s, and he ligh - h eshold is
au oma ically adjus ed o he a e age illumina ion.
Fig.
7.
sma pixel.
Concep ual block diag am
o
he p ocessing ci cui y
o
a CNN
V.
PROCESSING
CIRCUITRY
A.
Basic Ci cui Building Blocks
Fig.
7
is
a
block diag am o he p ocessing ci cui y o he
c h uni in
a
sma -pixel CNN chip, acco ding o
(2).
This
igu e shows
a
co e in eg a o wi h nonlinea losses and
an
ou pu s uc u e o gene a e weigh ed eplicas o he c h inpu
U,
and s a e
x,,
o ansmission o he neighbo sma -pixels.
The in eg a o is d i en by weigh ed eplicas o he inpu and
s a e signals o he sma pixels in he neighbo hood
N,(c),
plus an o se e m, ob aining he ollowing signal o d i e he
co e in eg a o
Jc( )
=
D,
+
{Acdxd( )
+
Bcd~d}.
(7)
Cu en -mode p o ides
a
con enien choice o ealize he
p ocessing ci cui y
o
sma -pixel CNN's. On one hand, i
enables di ec in e ace wi h he senso s, whose ou pu s a e
cu en s. On he o he , cu en summa ion a he in eg a o
inpu node is di ec ly achie ed by ou ing signals o
a
common
node. Finally, analog ope a o s in ol ed in Fig.
7
(weigh ed-
eplica ion, in eg a ion, and limi a ion)
a e
ealized by simple
cu en mi o ci cui s.
Fig.
8(a)
ealizes he co e in eg a o . Inpu cu en
J,*( )
is
an unno malized e sion o
Jc( )
in
(7),
wi h no maliza ion
ac o
IQ:J:(~)
=
IQJc( ).
Ou pu cu en
z ( )
is he
co esponding unno malized e sion o
x,
( ).
The pa allel
combina ion o he diode-connec ed inpu ansis o
A41
and
capaci o
C
yields a ime cons an
=
GIs,,
whe e
gm
is
he ansconduc ance pa ame e o
MI.
On he o he hand, no e
ha cu en
x:
canno swing beyond he alues o he cu en
sou ces which d i e he common ou pu node
o
ansis o s
and M3-meaning ha
IxZI
<
IQ.
Thus, analysis o his
ci cui esul s in:
dE
A',
(c)
as
equi ed o ealize
(2),
and whe e
g(.)
is he unc ion de ined
in
(3)
wi h
m
i
CO.
In p ac ice
7
does no emain cons an ,
bu a ies wi h inpu cu en le el. Howe e , mos p ocessing
asks ole a e his a ia ion wi h no deg ada ion o he ne wo k
unc ionali y
[9].
Fig. 8(b) shows
a
ci cui o ealize he ou pu s uc u e
o
Fig.
7
om ol age
V,,
and using he basic cu en mi o
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900
IEEE JOURNAL
OF
SOLID-STATE CIRCUITS,
VOL.
29,
NO.
8,
AUGUST
1994
""'I6
;d(
6 Cd'IQ
I
1
(b)
Fig.
8.
sma
pixels.
(a)
Co e
in eg a o ;
(b)
ou pu s uc u e.
Cu en -mode ci cui
blocks
o
he
p ocessing ci cui y
o
CNN
p inciple o weigh ed eplica ion [23]. No e ha Fig. 8(b)
con ains wo di e en subs uc u es o co e each possible sign
o he weigh
Acd.
Posi i e weigh s a e ob ained using a single
ou pu ansis o whose geome y ac o is
lAcdl
imes ha o
ansis o
MI.
Thus, a cu en
A,,x;
is sou ced o he ou pu
node. Nega i e weigh s equi e an addi ional cu en mi o
wi h uni y weigh o sign in e sion.
B.
Some Ci cui Design
Issues
The ollowing is a b ie commen o dominan nonideali ies
encoun e ed in he p ac ical implemen a ion o sma -pixel
CNN chips and associa ed ci cui s.
I)
Cu en Gain E o :
A majo sou ce o e o is he ini e
a io o he inpu conduc ance
yi,
o he ou pu conduc ance
yo
o he cu en mi o s, which causes cu en gain e o due
o spu ious cu en di ision. I is especially signi ican a he
inpu node o he in eg a o , whe e he gain e o
,
is gi en
app oxinia ely by [9]:
egula ed mi o s, o a combina ion
o
bo h
mus
be used
[23].
In
pa icula ,
analysis
shows ha he
cascode
mi o
o
Fig. 9(a) ob ains alues o
g0/gi L
se e al o de s
o
magni ude
lowe han ha o single mi o s, wi h smalle a ea occupa-
ion. Chips epo ed in Sec ion
VI
a e ealized using hese
mi o s, and sized o handle he whole inpu cu en ange
wi h minimum dis o ion and smalles possible de ices. Fo
mi o s biased by a cu en
IQ,
we ob ain he ollowing sizing
equa ions
whe e
k,
=
pC0,/2.
V,,
is he h eshold ol age, and
Vc.4~
is he cascode ol age, which can be gene a ed as shown in
Fig. 9(b). We assume he same geome ies
W,
and
Ln
o
all n-channel ansis o s in he cascode mi o .
W
alues
o la ge cu en s (associa ed
o
weigh ed eplica ion) a e
calcula ed by imposing he cons ain ha all ansis o s ha e
equal cu en densi y. Al e na i ely, o a gi en aspec a io
W,/L,,
(10)
es ablishes a bound o he maximum bias
cu en o he de ice.
2)
Misma ch e o ; a ea, powe and eliabili y:
T ansis o
geome y a ios, s a ic gain e o due o nonnull
go/gzn,
and
powe dissipa ion inc ease wi h
IQ.
Hence, a bias cu en as
small as possible should be chosen. The issue is o iden i y he
minimum easible ail cu en alue. A lowes limi is ce ainly
es ablished by leakage, which in ou case is inc eased by ligh
e ec s. Howe e , a mo e es ic i e bound exis s due o MOS
ansis o misma ch and Ea ly ol age
(V,)
deg ada ion wi h
channel leng h.
Misma ch is p oduced mainly by a ia ions o
V,
and
/3
=
pCo,W/L,
whose s anda d de ia ions
~(VT)
and
o(@)/p
o de ices wi h equal layou show a componen in e sely
p opo ional o he squa e oo o he channel a ea, and
ano he p opo ional o he dis ance be ween de ices [24].
Howe e , in he echnology used and o ansis o pai s close
han abou 2.5 mm, he dis ance-dependen componen is
negligible o de ices wi h channel a ea o less han
100
piii2
[24]-la ge han he alues ob ained using
(10)
o bias
cu en below
-50
pA
and channel leng hs o
3.2
/mi.
Lowe
channel leng hs ha e no been conside ed o se e al easons,
like sho -channel e ec s, ea ly- ol age deg ada ion, and in-
c eased misma ch e ec s due o he associa ed low channel
a eas.
In
addi ion, lowe ansis o geome ies do no esul in
app eciable a ea educ ions due o he minimum con ac size
(4
pm
wi h su ounding me al and di usion in he echnology
used).
Ano he impo an conside a ion is ha o a gi en
o(V'+)
and
g(/?)//?,
he a io
a(I)/I
in
MOS
ansis o s ope a ing in
s ong in e sion and a e pinch-o has an in e se dependency
wi h
iigs
-
V,.
This means ha once geome ies ha e been se
o achie e accep able misma ch le els, bias cu en canno be
EM
(N+
I)*
(9)
Sin
whe e
N
deno es he numbe o mi o s d i ing his node-up
o
18
o empla es wi h no ze o en ies on a ec angula
g id ne wi h uni y neighbo hood pa ame e . Fo imp o ed
go/gin
igu es wi h sho channel de ices, cascode mi o s,
dec eased oo a below he bound gi en by
(lo),
since his
would p oduce a low
ugs
ol age a he bias poin , wi h he
co esponding la ge
o(I)/I.
Hence, misma ch conside a ions
es ablish bounds o bo h minimum a ea and powe ends.
3)
Ligh e ec s on he p ocessing ci cui y:
Op ical image
acquisi ion o ces he p ocessing ci cui y o be exposed o
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ESPEJO e al.: SMART-PIXEL CELLULAR NEURAL NETWORKS IN ANALOG CURRENT-MODE CMOS TECHNOLOGY
YO1
-
W
L
-
.....
. . .
....
lin
io
+
W
L
-
-
W
L
-
W’
L
W
L
-
‘W
-
L
W
L
-
(b)
Fig.
9.
and e e ence ci cui y,
(b)
cascode ol age gene a ion.
CMOS bias-shi ed mi o s and biasing de ices. (a) Cascode mi o
ligh , which esul s in an inc ease o he leakage cu en s
a he e e se-biased subs a e-di usion junc ions. Uni a y
bias cu en s mus be su icien ly la ge in o de o neglec
his e ec . Also, MOS h eshold ol age depends on ligh
in ensi y, inc easing he misma ch e ec on cu en mi o s
and sou ces. Cu en mi o ansis o s a e commonly placed
nea by, and hence ligh -in ensi y g adien s ha e a educed
e ec . On he con a y, cu en sou ces in di e en cells,
biased by common global ol ages, can exhibi la ge
dispe sions. The ole ance o a pa icula applica ion o
a ia ions in he uni a y bias cu en mus be e alua ed
in gene al, and local e e ences should be used when
equi ed.
Fig.
10.
Mic opho og aph
o
he
DCC p o o ype.
VI.
EXPERIMENTAL
RESULTS
A.
16
x
16
DCC
P o o ype
The ollowing measu emen s we e aken om a
16
x
16 sma -pixel CNN chip in ended o ho izon al connec ed
componen de ec ion
[15]
(see Fig. 2)-a basic p ep ocessing
s ep o pa e n ecogni ion. Fig.
10
shows a mic opho og aph
o he p o o ype, which in addi ion o he sma -pixel a -
ay con ains bounda y cells, ou pu bu e s, bias s ages, and
some
digi al con ol ci cui y o he ou pu image download-
ing p ocess. The dimensions o he co e a ay a e 1890
x
1530
pm2,
and i s powe dissipa ion is 27 mW. The o al chip
dimensions, including he bonding pads, a e 2480
x
2500
p n2,
wi h a o al powe dissipa ion o 42 mW and a o al o 24 pins.
Fig.
11
shows he schema ic and layou o one elemen a y
uni . Uni dimensions a e
118
x
96pm2,
which include he
senso and associa ed egula ion ci cui y
(-30%
o he a ea),
he p ocessing ci cui y, an addi ional cu en eplica ion o
ou pu e alua ion, and all equi ed ou ing (cells
a e
connec ed
o each o he by abu men ). Senso is ealized wi h wo
minimum-size p-n-p de ices in a Da ling on con igu a ion, o
p oduce a b igh -cu en unde labo a o y ligh ing o abou
lpA,
la ge enough o he ma ching equi emen s o his
applica ion. Cascode s uc u es a e used o bo h cu en
sou ces and mi o s, and excep o con ol swi ches, all
MOS
ansis o s ha e
W
=
4p n
and
L
=
3.2pm.
Powe
dissipa ion wi h a
5
V
supply and unde en i onmen al ligh
in he labo a o y is lO5bW pe cell, uni a y cu en being
We ha e ob ained 100% success (ou o
30
ials) o
ull de ice le el Mon eca lo simula ion
o
his chip. These
Mon eca lo simula ions a e based on he expec ed a ia ions
o he h eshold ol ages
VTo
and he la ge signal anscon-
duc ance
p
(body e ec pa ame e
y
in luences only he
cascode ansis o s). Global biasing ol ages a e used o
cu en e e ence gene a ion, and bias s ages a e included in
he simula ion. Dispe sion due o misma ch among ansis o s
o di e en cu en sou ces did no p oduce c i ical esul s.
Thus, global biasing is a ai app oach o his applica ion.
Fig. 12(a) illus a es he chip measu emen se up and
Fig. 12(b) shows i e inpu images (le column) and he
IQ
=
2pA.
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902
IEEE
JOURNAL
OF
SOLID-STATE CIRCUITS,
VOL.
29,
NO.
8,
AUGUST
1994
SET!
VPB!VCP!VCN! Objec D.U.T.
(Film Nega i e)
(Chip)
Wo k
S a ion
Digi al
De ice
Tes ing
Equipmen
Regulable Focusing
Ligh
Sou ce
(a)
VTH!
START!
(a)
io
6
/ai*
9
.*'(
a
111"
(b)
Fig.
11.
elemen a y uni o
DCC
p o o ype.
(a)
Schema ic
( e e
o ex
o
dimensions) and (b) layou o
measu ed ou pu images ( igh column). The p o o ype
was exhaus i ely es ed wi h 1200 inpu images. Fig. 12(c)
con ains he ou pu wa e o ms obse ed om he cells in
a pa icula ow o he a ay du ing a p ocessing example.
The inpu pixels a e displayed a he le side column,
while he ou pu ones a e a he igh . The signals display
he measu ed ansien e olu ion o he ou pu o he cells
in he ow. Measu ed con e gence ime is
1.6~~.
Ou pu
image downloading equi es
8ps,
using a
2
MHz
digi al
clock equency o he se ial downloading p ocess. Ci cui
ope a ion emains co ec , wi h no speed deg ada ion, i he
ol age supply is educed om he nominal
5
V
down o 2.7
V.
This is ano he posi i e consequence o using cu en -mode
echniques.
1w
I
I
B.
16
x
16
Radon T ans o m P o o ype
This p o o ype pe o ms he Radon T ans o m [25] o
16
x
16
pixels inpu images. This chip accep s elec ical, as well as
op ical, inpu . The p ocessing ci cui y is based on a modi ied
e sion o (2), whe e ime has been disc e ized, and he
nonlinea i y is ha d
x,(n
+
1)
ime
1,
o
D,
+
{Acd~d(n)
+
Bcdud}
>
0. (C)
d€N,(c)
Fig. 12. (a) Measu emen se up, (b) i e inpu images and he ou pu
measu ed
om
DCC,
and
(c)
measu ed ansien esponse
on
a
ow
o
cells.
-
1,
o he wise
(1
1)
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ESPEJO
e
al.:
SMART-PIXEL
CELLULAR NEURAL
NETWORKS
IN
ANALOG
CURRENT-MODE
CMOS
TECHNOLOGY
903
FOT!LOAD!LOAD!
VTH!
CI!
c2!
Fig.
14.
Radon T ans o m p o o ype.
Fi e inpu images and he co esponding ou pu measu ed
om
he
(b)
Fig.
13.
Radon T ans o m p o o ype.
(a) Schema ic o elemen a y uni and (b) mic opho og aph o he
Also, his applica ion equi es signal-dependen weigh s [26].
In pa icula , he weigh s o he con ibu ions going om a
pa icula cell
c
o i s neighbo s depend on
5,.
The comple e
se
o
CNN coe icien s can be desc ibed using unidimensional
empla es as ollows
i
(z,
2
0)
A
=
{
[l
0
01, i
(zc
<
0)
[0
0
11,
B=[OOO]
D=O
(12)
which e lec he scaling ac o s applied o he con ibu ions
o a pa icula cell o i s neighbo s.
Fig. 13(a) shows a simpli ied schema ic o a cell, which uses
pass ansis o s o ealize he delay equi ed in
(1
1)
and a high-
esolu ion cu en compa a o [27] o he ha d nonlinea i y.
The design echnique and he algo i hm used in his ci cui y is
desc ibed in de ail in [9]. Fig. 13(b) shows a mic opho og aph
o he p o o ype. Cell dimensions
a e
121
pm
x
124
pm,
and
he powe dissipa ed by each cell is
1
mW-signi ican ly la ge
han o he DCC due o he ci cui y used o implemen he
ha d nonlinea i y.
The sys em con ains a numbe o blocks loca ed in he
pe iphe y o he cell a ay, like ou pu bu e s, bias s ages,
and digi al con ol ci cui y dedica ed o he uploading and
downloading p ocesses. This addi ional ci cui y, oge he wi h
he bonding pads, esul in a o al sys em a ea o
2670pm
x
2680
pm,
and a o al sys em dissipa ion o 330 mW. The chip
equi es a o al o 43 pins. This numbe is signi ican ly highe
han ha o he p e ious p o o ype due o 16 inpu pads used
o elec ical inpu image uploading.
Using a
2
MHz digi al clock equency, image p ocessing
ime is
8
ps.
The se ial downloading p ocess also equi es
8
ps.
As an example, Fig. 14 shows i e inpu images (le column)
and he co esponding ou pu images measu ed om he chip
( igh column). The comple e es o he p o o ype in ol ed
1200 images.
VII.
CONCLUSIONS
Summa izing, his pape has ou lined a basic model and
some design issues ela ed o a me hodology o design CNN
sma -pixel chips in digi al CMOS p ocesses, and has p e-
sen ed measu emen s om wo wo king p o o ypes in a 1.6-
pm n-well CMOS echnology. One calcula es he numbe o
connec ed pieces (DCC) o an inpu image in he ho izon al
di ec ion, and he o he e alua es he Radon T ans o m o
an inpu image. The DCC chip ob ains a densi y o
-89
sma -pixels pe mm2 (each including senso y, egula ion and
p ocessing ci cui y), wi h a powe consump ion o 105
pLw
pe sma pixel and image p ocessing imes below
2ps.
A ea
and speed igu es o he RT chip
a e
simila . Al hough powe
dissipa ion is la ge o his p o o ype, his can be co ec ed
wi h a ca e ul design o he cu en compa a o [27].
As compa ed o p e ious CNN implemen a ions, he
p oposed echnique makes he equi ed syne gy be ween
sensing and p ocessing, and signi ican ly imp o es a ea and
speed powe igu es. In pa icula , when compa ed o p e ious
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