THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 15 |NUMBER: 5 |2017 |DECEMBER
A No el Realiza ion o Low-Powe and
Low-Dis o ion Mul iplie Ci cui wi h Imp o ed
Dynamic Range
Ali NADERI SAATLO1, Abol azl AMIRI 2
1Depa men o Elec ical-Elec onics Enginee ing, Facul y o Enginee ing,
U mia B anch, Islamic Azad Uni e si y, U mia, I an
2Depa men o Elec onics Enginee ing, Facul y o Enginee ing,
IAU Uni e si y o Busheh , Alishah , Busheh , I an
[email p o ec ed], [email p o ec ed]
DOI: 10.15598/aeee. 15i5.2433
Abs ac . A no el opology o ou -quad an analog
mul iplie ci cui is p esen ed in his pape . The ol -
age mode echnique is employed o design he ci cui
in CMOS echnology. The dynamic inpu and ou pu
anges o he ci cui a e imp o ed owing o he ac
ha he ci cui wo ks in he sa u a ion egion no in
weak in e sion. Also he p oposed mul iplie is sui able
o low ol age ope a ion and i s powe consump ion is
ela i ely low. In o de o e i y he pe o mance o
he p oposed ci cui , pe o mance o he ci cui a ec ed
by second o de e ec s including ansis o misma ch
and mobili y educ ion is analyzed in de ail. I will be
shown ha any concei able misma ch in he ansis o
pa ame e s leads o second ha monic dis o ion. Ad-
di ionally, he e ec o mobili y educ ion in he hi d
ha monic dis o ion will be compu ed. In o de o sim-
ula e he ci cui , Cadence and HSPICE so wa e a e
used wi h TSMC le el 49 (BSIM3 3) pa ame e s o
0.18 µm CMOS echnology, whe e unde supply ol -
age o 1.5 V, o al powe consump ion is 44 µW, he
co esponding a e age nonlinea i y emains as low as
1 %, and he inpu ange o he ci cui is ±400 mV.
Keywo ds
CMOS design, ou quad an , low dis o ion,
modula ion, mul iplie ci cui .
1. In oduc ion
In ecen yea s, analog mul iplie s a e widely used in
many applica ions such as phase-locked loops, adap i e
il e s, modula o s, au oma ic gain con olling, image
p ocessing, a i icial neu al ne wo ks and uzzy in e-
g a ed sys ems [1], [2], [3] and [4]. Di e en me hods
o implemen a ion o his building block ha e been e-
cen ly p esen ed based on he use o bulk d i en MOS
[5], Floa ing Ga e MOS (FGMOS) [6] and class-AB
mode [7]. In he pas decade, he demand o po able
ope a ion o elec onic sys ems has led o he end o
designing ci cui s o be ea u ed wi h low powe con-
sump ion and ope a e o low supply ol ages. One
possible echnique o design he low-powe dissipa ion
mul iplie ci cui is o use MOSFETs in sub- h eshold
egion [8], [9] and [10] in which mos o hem ollow
he Gilbe cell opology and modi ied Gilbe cell [11].
The d awback o designs in his egion has been e-
e ed o poo dynamic ange, limi ed bandwid h and
low ol age swing. Ano he app oach o designing low
powe mul iplie ci cui s is o use he anslinea p in-
ciple o MOS ansis o s ope a ed in he weak in e -
sion [12] and [13]. Al hough his app oach has he ad-
an age o low powe consump ion, he dynamic ange
o hese ci cui s is e y small and ope a ion speed is
slow. On he con a y, p esen ed mul iplie s based on
he anslinea loop in sa u a ion egion exhibi wide
bandwid h, highe dynamic ange and lowe dis o ion
and hus hey a e mo e p e e ed han hose ope a ing
in weak in e sion [14]. None heless, he channel leng h
modula ion and body e ec a e he impo an issues
in he ci cui s based on anslinea loop p inciple. An-
o he salien ea u e o he ci cui s is he ou -quad an
ope a ion capabili y, an impo an asse e y use ul in
a ious applica ions [15] and [16]. Some o he well-
known mul iplie ci cui s ope a e only in one [17] and
[18] o wo quad an s [19] and [20], which was discussed
in [21] and no sui able o many o men ioned appli-
ca ions.
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Ano he ac o , which is impo an in he mul iplie
ci cui , is non-linea i y ac o , because o he ac ha
he mul iplica ion ope a o is a linea map be ween in-
pu and ou pu . The e o e his ac o is a se ious chal-
lenge in he mul iplie ci cui s, which is commonly a -
ec ed by body e ec , mobili y educ ion and misma ch
in he ci cui de ices. In some exis ing analog mul i-
plie s, he e ec s o hese non-ideali ies we e p ope ly
s udied and a ew echniques we e p oposed in o de
o educe he non-linea i y [22] and [23]. Howe e ,
hey su e om low accu acy and/o low bandwid h.
Mo eo e , single supply ol age ci cui s a e p e e ed
o hose in dual mode [24], whe e he mul iplie s e-
po ed in [8] and [20] equi e dual supply ol age. As
such hese ci cui s a e no sui able o oday’s wo ld o
po able equipmen .
In his pape , a no el design o ou quad an analog
mul iplie is p esen ed which bene i s om ad an ages
o di e en ial ou pu opology. The dynamic inpu and
ou pu anges o he ci cui a e signi ican ly imp o ed.
High linea i y and high accu acy a e u he ad an-
ages o he ci cui . Also he p oposed mul iplie is
sui able o low ol age ope a ion and i s powe con-
sump ion is ela i ely low. The pe o mance o he p o-
posed mul iplie is cha ac e ized using HSPICE wi h
TSMC in 0.18 µm CMOS echnology. The pape is o -
ganized in 5 sec ions: The p oposed ci cui is p esen ed
in Sec. 2. , ollowed by he pe o mance analysis in
Sec. 3. In Sec. 4. , HSPICE simula ion esul s o
p oposed mul iplie ci cui a e p esen ed o p o e he
e iciency o he design. Finally, Sec. 5. concludes he
mos impo an achie emen o he p oposed ci cui .
2. The P oposed Mul iplie
The p oposed ou -quad an mul iplie ci cui is shown
in Fig. 1, which is based on he squa e-di e ence alge-
b aic iden i y as:
(x+y)2−(x−y)2= 4xy. (1)
Acco ding o his, o ealize his equa ion, wo squa -
ing unc ions should be designed in which hei ou -
pu s need o be sub ac ed. Le us conside he p o-
posed ci cui o Fig. 1. Assume ha all o he ansis-
o s ope a e in sa u a ion egion (excep o M17 and
M18), hus he d ain cu en o ansis o s by neglec -
ing he second o de e ec such as mobili y educ ion
and channel-leng h modula ion can be exp essed as:
ID=K(VGS −VT)2,(2)
whe e K= 0.5µ0COX (W/L)is ela ed o ans-
conduc ance pa ame e , VGS is ga e- o-sou ce ol age
and VT ep esen s he h eshold ol age o MOS an-
sis o which can be a ec ed by body e ec . The body
e ec e e s o change in he ansis o h eshold ol -
age esul ing om a ol age di e ence be ween he
ansis o sou ce and subs a e, which can be cha ac-
e ized by:
VT=V 0+γhpVSB +|2ϕF| − p|2ϕF|i,(3)
whe e V 0is he ze o-bias h eshold ol age, γis he
body-e ec coe icien and ϕF is he Fe mi po en ial.
Conside ing he igu e, wo squa ing ci cui s a e shown
in le hal and igh hal o he s uc u e. Focusing
on he le side squa ing ci cui , since ansis o s M1
and M2a e biased in he sa u a ion egion and also
ID1=ID2, he ela ionship can be w i en as:
KN(Vin −V1−VTN)2=KN(V1−VTN)2.(4)
Simpli ying equa ion abo e we ha e:
V1=2Vin1VTN −V2
in1
(−2Vin1+ 4VTN)=Vin1
2.(5)
One can ind he ol age o V2a he same way as:
V2=−Vin1
2.(6)
The ol ages o V1and V2a e u ilized o u n on M9
and M10 ansis o s, espec i ely. In his case, hei
Vin1
_
Vin1
+Vin2
_Vin2
+
Vou _
+
M1
M2
M9M10
M13
M3
M4
M14 M16
M11 M12
M7
M5
M15
M6
M8
VDD
V1V2V4
V3
VBp M17 M18
Fig. 1: The p oposed ou -quad an analog mul iplie ci cui .
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cu en s a e added oge he and low o ansis o M13:
ID13 =ID9+ID10 =
KP(VDD −V1− |VTP|)2+ (VDD −V2− |VTP|)2.
(7)
Replacing Eq. (5) and Eq. (6) in Eq. (7); a e ew
ma hema ical manipula ions we ha e:
ID13 = 2KP"Vin1
22
+ (VDD − |VTP|)2#.(8)
I can be clea ly seen om Eq. (8) ha he cu en
ID13 is he squa e o he inpu ol age plus some con-
s an ol ages. The same p ocedu e can be ollowed o
he igh hal o he ci cui o ob ain ID15:
ID15 = 2KP"Vin2
22
+ (VDD − |VTP|)2#.(9)
The cu en s o ID13 and ID15 a e ans e ed o he
ou pu h ough ansis o s M14 and M16, espec i ely.
T ansis o s M17 and M18 a e biased in he iode egion
(by se ing VBp =−1) and pe o m as he esis o s in
which hei esis ance alues can be ep esen ed by:
Rn≈[µnCox(W/L)n(VSGn − |VTP|)]−1.(10)
By se ing R17 =R18 =R, he ou pu ol age o
p oposed ci cui can be de i ed as:
Vou =R(ID14 −ID16) =
= 2RKP"Vin1
22
−Vin2
22#.(11)
Acco ding o Eq. (11), by es ablishing Vin1=Vx+Vy
and Vin2=Vx−Vy he ul ima e ol age is e en ually
wha would be expec ed as ollows:
Vou = 2RKP(VxVy).(12)
Take no ice ha summa ion o he signals is p o-
ided by se ies connec ion o he ol age sou ces (Vx
and Vy). Also sub ac ion o he inpu signals was e-
alized in he same way excep o changing he pola i y
o Vy, which we e pe o med using a well-known in e -
ing ampli ie . Also, he e is no need sub ac ion a he
ou pu node, because he ou pu is di e en ial.
3. Pe o mance Analysis
In his sec ion, pe o mance o he ci cui a ec ed by
second o de e ec s including ansis o misma ch and
mobili y educ ion is analyzed in de ail. I will be
shown ha any concei able misma ch in he ansis-
o pa ame e s leads o second Ha monic Dis o ion
(HD). Addi ionally, he e ec o mobili y educ ion in
he hi d ha monic dis o ion will be compu ed. Fol-
lowing ha , he e ec o co esponding pa ame e s de-
i ed in each sec ion as well as imp o emen me hod-
ology will be ho oughly discussed.
3.1. Second HD Due o he
Misma ch
In Sec. 2. , he well-ma ched pa ame e s including
ans-conduc ance and h eshold ol age o he ansis-
o s we e assumed o ob ain he ou pu o he ci cui .
Conside ing Eq. (5), due o he ac ha he ol age o
V1is esul ed by supposing hese ma ched pa ame e s,
any possible misma ch in he p oposed ci cui will a -
ec he ol age o his node. Simila ly, he ol ages o
V2,V3and V4ge a ec ed by he misma ch acco dingly.
Since hese ol ages ha e di ec p opo ion o Vin1and
Vin2, consequen ly he o al misma ch is e e ed o he
inpu signals and can be modeled as:
V1=Vin1
2+ ∆ in1Vin1,(13)
V2=−Vin1
2−∆ in1Vin1,(14)
V3=Vin2
2+ ∆ in2Vin2,(15)
V4=−Vin2
2−∆ in2Vin2,(16)
whe e ∆ in1and ∆ in2a e misma ch pe cen ages o
Vin1and Vin2, espec i ely. By applying Vin1=Vx+Vy
and Vin2=Vx−Vy o he mul iplie ci cui , he ou pu
ol age is gi en by:
Vou = 2RKPVxVy+ (2∆ 2
in1)(Vx+Vy)2. . .
. . . −(2∆ 2
in2)(VxVy)2.(17)
I can be clea ly seen ha he e ms o ∆ 2
in1and
∆ 2
in2a e e y small (because ∆ in1and ∆ in2<1),
he e o e he esul ed e o will be negligible. I is
wo hwhile o calcula e he ha monic dis o ion o he
ci cui a he ou pu conside ing he me hod p esen ed
in [25], i one o he inpu s (Vx) is kep cons an and
he o he one is sinusoidal in he o m o Vy=b msin ,
second ha monic dis o ion can be de i ed as ollows:
HD2=∆ 2
in1−∆ 2
in2
2Vx(4∆ 2
in1+ 4∆ 2
in2+ 1)b m.(18)
The equa ion implies ha when he misma ch pe cen -
age o ∆ 2
in1and ∆ 2
in2inc eases, second ha monic dis-
o ion dec eases. Also, i dec eases wi h dec easing Vx
as well.
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3.2. E ec o Mobili y Reduc ion in
Thi d HD
I he mobili y educ ion is aken in o calcula ions, he
d ain cu en o a MOS ansis o ope a ed in sa u a-
ion is gi en by [26]:
ID=K(VGS −VT)2
1 + θ(VGS −VT),(19)
whe e θis he mobili y deg ada ion pa ame e which
a ies ypically om 0.001 o 0.1 V−1. This equa ion
may be expanded in a Taylo se ies:
ID=K(VGS −VT)2·
·1−θ(VGS −VT) + θ2(VGS −VT)2+. . ..(20)
To simpli y he calcula ions, jus he i s o de o θ
is used, and he highe -o de e ms a e igno ed. Re-
placing he expansion in Eq. (4), one can each V1and
V2as:
V1≈Vin1
2+θVin1(V2
in1−3Vin1VT P + 3V2
T P )
4VT P
,(21)
V2≈ −Vin1
2+θVin1(V2
in1+ 3Vin1VT P + 3V2
T P )
4VT P
.(22)
The same p ocedu e can be ollowed o ob ain V3and
V4. In his case, he ou pu o he mul iplie ci cui can
be ep esen ed as ollows:
Vou ≈RKPV2
in1−V2
in2+. . .
. . . θVDD(2V3
in2−2V3
in1−3V2
in2VTP + 3Vin1VTP)
VTP .
(23)
By applying Vin1=Vx+Vyand Vin2=Vx−Vy, he
inal ou pu will be ob ained. Since he ou pu ol age
includes hi d-o de o he inpu s, hi d ha monic dis-
o ion is achie ed by keeping one o he inpu s (Vx)
as a cons an and he o he one as sinusoidal. Again
using he me hod p esen ed in [25] we ha e:
HD3=θVDD
2VxVT P −4θ(3VTP −V2
x+ 2VxVTP)b 2
m.(24)
4. Pos Layou Simula ion
Resul s
In his sec ion, simula ion esul s a e p esen ed us-
ing HSPICE wi h TSMC le el 49 (BSIM3 3) pa am-
e e s o 0.18 µm CMOS echnology so as o e i y
he pe o mance o he p oposed ci cui . The simu-
la ion esul s a e ca ied ou a e ex ac ing he lay-
ou , which is d awn by Cadence so wa e using single
poly and wo me als (Me al1 and Me al2). Figu e 2
shows he ull layou o he ci cui , in which he a ea is
66.35 µm×58.2 µm. The aspec a io o ansis o s is
gi en in Tab. 1 and he supply ol age is 1.5 V. Consid-
e ing he condi ion o iode egion o PMOS ansis-
o s o M17 and M18, choosing VBp =−1V gua an ies
ha hese ansis o s ope a e in he iode egion and
wo k as he ac i e esis ances. DC ans e cha ac-
e is ic o he ci cui o e a conside able ange o he
inpu s is shown in Fig. 3, in which one o he inpu s
(Vy) is kep cons an and he o he one (Vx) swep om
−400 mV o +400 mV. By changing he cons an ol -
age o Vyand hen sweeping o Vx, desi ed ou pu s will
be ob ained. Wi hin his ange, he a e age o mea-
su ed nonlinea i y e o is 0.94 %.
Tab. 1: T ansis o aspec a ios.
T ansis o name W/L (µm/µm)
M1-M810/0.18
M9-M12 12/0.18
M13-M16 4/0.18
M17-M18 15/0.18
Fig. 2: Layou o he p oposed mul iplie ci cui .
0
50
100
150
200
250
-250
-200
-150
-100
-50
0-100-200-300-400 100 200 300 400
Vou (mV)
Vx (mV)
Vy (mV)
400
-400
0
Fig. 3: Simula ion esul o DC ans e cha ac e is ic.
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Figu e 4 shows he mul iplie being used o balance
modula o as well as he e o quan i y. Vxand Vya e
500 kHz and 50 kHz, 800 mVP-P sinusoidal ca ie and
modula ion signals, espec i ely ed o inpu s o he
p oposed mul iplie . Also Fig. 5 demons a es how he
mul iplie ci cui can be employed as a equency dou-
ble . In his simula ion, i bo h equencies o he inpu
ol age a e 500 kHz, he igu e shows he co espond-
ing ou pu wa e o m wi h double equency o 1 MHz.
F equency esponse in Fig. 6 shows ha bandwid h o
he ci cui is 196 MHz when he inpu signal is applied
o Vx, and Vy= 400 mV. The same esul is ob ained
o cons an alue o Vxand AC signals o Vy.
400
-400
0
250
-250
0
5
-5
0
s
Ou pu Signal (mV)
E o (mV)
0 10 20 30 40
Time (µs)
Inpu Signals (mV)
Fig. 4: P oposed mul iplie as an ampli ude modula o .
500 kHz ca ie sinusoid and 50 kHz modula ing sig-
nal (uppe wa e o m); AC modula ed ou pu (middle
wa e o m); E o measu emen (lowe wa e o m).
400
-400
0
250
-250
0
5
-5
0
0 10 20 30 40
Time (µs)
Ou pu Signal (mV)
Fig. 5: The p oposed mul iplie as a equency double , inpu
signals (uppe wa e o m); ou pu signal (middle wa e-
o m); E o measu emen (lowe wa e o m).
0
-2
-4
-6
-8
-10
-12
-14
10
0
10
2
10
4
10
6
10
8
10
10
F equency (Hz)
Ou pu Vol age (dB)
Fig. 6: F equency esponse o he ci cui .
The To al Ha monic Dis o ion (THD) e sus inpu
signal a 100 kHz and 1 MHz is shown in Fig. 7. THD
simula ions a e ca ied ou o bo h o Vxand Vy, when
one o hem is cons an and ano he one is sinusoidal.
In he wo s case, an inpu signal o 1 Vp-p a a e-
quency o 1 MHz esul ed in a THD o less han 1.2 %.
0 0.2 0.4 0.6 0.8 1
Vx P-P and Vy P-P (V)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
THD (%)
1 MHz (Vy=cons .)
100 kHz (Vy=cons .)
1 MHz (Vx=cons .)
100 kHz (Vx=cons .)
Fig. 7: Rela ion be ween THD, Vxand Vy.
In o de o e alua e he obus ness o he ci cui
agains he p ocess a ia ion, he Mon e Ca lo anal-
ysis wi h 100 samples is pe o med by applying ±5%
Gaussian dis ibu ion a ±3σle el in he a ia ion o
all ansis o s aspec a io and h eshold ol age si-
mul aneously. Two sinusoidal signals wi h he equen-
cies o 500 kHz and 1 MHz and also 400 mVp-p and
800 mVp-p ampli udes a e applied o he ci cui unde
he a o esaid a ia ions and hen he ou pu s a e com-
pa ed wi h he ideal alues. The a e age o e o in
each sample is conside ed as he ela i e e o . The
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-4 -3 -2 -1 0 1 2 3 4
Rela i e e o (%)
0
2
4
6
8
10
12
Numbe o samples
Fig. 8: Mon e Ca lo analysis o he ci cui o ±5% misma ch
in h eshold ol age and ansis o s aspec a io.
esul is shown in Fig. 8, in which 68 % o he o al
samples occu ed wi h he ela i e e o o less han
±1%.
To analyze he pe o mance o he p oposed ci cui
ega ding empe a u e a ia ions he simula ions a e
ca ied ou in di e en empe a u es. The h eshold
ol age is he mos impo an pa ame e in he analy-
sis o empe a u e dependence o CMOS ci cui s [27].
The e o e, a small a ia ion in h eshold ol age causes
a la ge change in he ou pu . Al hough single-ended
ou pu o he squa ing ci cui s (see Eq. (8) o Eq. (9))
includes he h eshold ol age, he ou pu o he com-
ple e ci cui (see Eq. (12)) does no depend on he
h eshold ol age, he e o e no ema kable change oc-
cu s a he inal ou pu .
Figu e 9 shows he ela i e e o o he ci cui in
di e en empe a u es, whe e he maximum e o oc-
cu ed a −40 ◦C wi h 1.18 %. In his simula ion, he
ob ained ou pu a he empe a u e o 25 ◦C is consid-
e ed as he e e ence alue ( ela i e e o = 0), hen he
esul ed ou pu s in o he empe a u es a e compa ed
wi h ha alue and he ela i e e o is compu ed. I
should be poin ed ou ha he inpu signals a e he
same as he signals ha we e applied in he Mon e
Ca lo analysis. The cha ac e is ics o he ci cui a e
-40 -20 0 20 40 60 80
Tempe a u e (°C)
0
0.2
0.4
0.6
0.8
1
1.2
Rela ice e o (%)
Fig. 9: Rela i e e o o he ci cui e sus di e en empe a-
u es.
summa ized in Tab. 2 and compa ed wi h he o me
wo ks o p o e he e iciency o he ci cui .
5. Conclusion
A new CMOS ol age-mode analog mul iplie ci cui
was p esen ed in his pape . The key ea u es o he
ci cui a e i s high accu acy and high linea i y as well
as i s body e ec - ee ope a ion, owing o he ac ha
he ci cui was designed based on a new symme ical
con igu a ion. Compa ed o he p e iously epo ed
wo ks, he dynamic inpu and ou pu anges o he ci -
cui a e conside ably imp o ed, since he ci cui wo ks
in he sa u a ion egion no in weak in e sion. To p o e
he e iciency o he p oposed ci cui , i was employed
as a modula o and equency double , and he simu-
la ion esul s we e compa ed wi h ideal pe o mance
o hese applica ions. The pe o mance o he p o-
posed mul iplie was cha ac e ized using HSPICE wi h
TSMC le el 49 (BSIM3 3) pa ame e s o 0.18 µm
CMOS echnology.
Tab. 2: Compa a i e pa ame e s o he p oposed mul iplie wi h o he ecen wo ks.
[9] [10] [22] [24] This wo k
Powe supply (V) 0.5 1.5 1.4 1.5 1.5
Inpu ange (mV) ±80 ±120 ±560 ±200 ±400
Ou pu ange (mV) ±10 ±150 ±10 µA±2±250
Powe consump ion (µW) 0.714 6.7 72.6 32 44
THD (%); 100 kHz, 400 mV 4.11 4.2 1.3 1.7 0.58
Nonlinea i y (%) 5.6 3.2 1.9 5.3 0.94
−3 dB bandwid h (MHz) 0.221 0.268 249 1980 196
Tech. (µm) 0.18 0.35 0.25 0.35 0.18
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Acknowledgmen
The au ho s would like o hank P o . Khay ollah Ha-
didi o his aluable ema ks and ui ul discussions in
imp o ing he p esen a ion o he pape .
Re e ences
[1] BLAKIEWICZ, G. Analog mul iplie o a low-
powe in eg a ed image senso . In: 16 h In e na-
ional Con e ence Mixed Design o In eg a ed Ci -
cui s and Sys ems. Lodz: IEEE, 2009, pp. 226–
229. ISBN 978-1-4244-4798-5.
[2] NADERI, A., A. KHOEI, K. H. HADIDI and
H. GHASEMZDEH. A new high speed and
low powe ou -quad an CMOS analog mul-
iplie in cu en mode. In e na ional Jou -
nal o Elec onics and Communica ions. 2009,
ol. 63, iss. 9, pp. 769–775. ISSN 1434-8411.
DOI: 10.1016/j.aeue.2008.06.002.
[3] CHOI, J., J. PARK, W. KIM, K. LIM and
J. LASKAR. High mul iplica ion ac o capaci-
o mul iplie o an on-chip PLL loop il e . Elec-
onics Le e s. 2009, ol. 45, no. 5, pp. 239–240.
ISSN 0013-5194. DOI: 10.1049/el:20092874.
[4] SAATLO NADERI, A. and I. S. OZOGUZ. De-
sign o high-linea , high-p ecision analog mul-
iplie ee om body e ec . Tu kish Jou nal
o Elec ical Enginee ing &Compu e Sciences.
2013, ol. 24, iss. 1, pp. 820–832. ISSN 1300-0632.
DOI: 10.3906/elk-1307-159.
[5] BHAWNA, A. and G. MANEESHA. Low- ol age
bulk-d i en class AB ou quad an CMOS cu en
mul iplie . Analog In eg a ed Ci cui s and Signals
P ocessing. 2010, ol. 65, iss. 1, pp. 163–169.
ISSN 0925-1030.
[6] KELES, S. and H. KUNTMAN. Fou quad an
FGMOS analog mul iplie . Tu kish Jou nal o
Elec ical Enginee ing &Compu e Science. 2011,
ol. 19, no. 2, pp. 291–301. ISSN 1300-0632.
DOI: 10.3906/elk-1001-377.
[7] OLIAEI, O. and P. LOUMEAU. Fou -quad an
class AB CMOS cu en mul iplie . Elec onics
Le e s. 1996, ol. 32, iss. 25, pp. 2327–2329.
ISSN 0013-5194. DOI: 10.1049/el:19961553.
[8] CHANG, C. C. and S. I. LIU. Weak in e sion ou -
quad an mul iplie and wo-quad an di ide .
Elec onics Le e s. 1998, ol. 34, iss. 22, pp. 2079–
2080. ISSN 0013-5194. DOI: 10.1049/el:19981496.
[9] PANIGRAHI, A. and K. P. PRASHANTA.
A no el bulk-inpu low ol age and low powe
ou quad an analog mul iplie in weak in e sion.
Analog In eg a ed Ci cui s and Signals P ocessing.
2013, ol. 75, iss. 2, pp. 237–243. ISSN 0925-1030.
DOI: 10.1007/s10470-012-9951-3.
[10] LIU, W. and S. LIU. Design o a CMOS low-powe
and low ol age 4-quad an analog mul iplie .
Analog In eg a ed Ci cui s and Signals P ocessing.
2010, ol. 63, iss. 2, pp. 307–312. ISSN 0925-1030.
DOI: 10.1007/s10470-009-9382-y.
[11] COUE, D. and G. WILSON. A 4-quad an sub-
h eshold mode mul iplie o analog neu al-
ne wo k applica ions. IEEE T ansac ions on Neu-
al Ne wo ks. 1996, ol. 7, iss. 5, pp. 1212–1219.
ISSN 1045-9227. DOI: 10.1109/72.536315.
[12] RUIQI, W. and X. JIANLI. MOS T anslin-
ea P inciple Based Analog Fou -Quad an
Mul iplie . In: IEEE In e na ional Con-
e ence on An i-Coun e ei ing, Secu i y
and Iden i ica ion (ASID). Taipei: IEEE,
2012, pp. 1–4. ISBN 978-1-4673-2144-0.
DOI: 10.1109/ICASID.2012.6325304.
[13] GRAVATI, M., M. VALLE, G. FERRI, N. GUER-
RINI and L. REYES. A no el cu en -mode e y
low powe analog CMOS ou quad an mul i-
plie . In: P oceedings o he 31s Eu opean Solid-
S a e Ci cui s Con e ence (ESSCIRC). G enoble:
IEEE, 2005, pp. 495–498. ISBN 0-7803-9205-1.
DOI: 10.1109/ESSCIR.2005.1541668.
[14] MENEKAY, S., R. C. TARCAN and H. KUNT-
MAN. No el high p ecision cu en -mode mul i-
plie /di ide . Analog In eg a ed Ci cui s and Sig-
nal P ocessing. 2009, ol. 60, iss. 3, pp. 237–248.
ISSN 0925-1030. DOI: 10.1007/s10470-009-9289-7.
[15] RYAN, C. Applica ions o a ou -quad an mul-
iplie . IEEE Jou nal o Solid S a e Ci cui s.
1970, ol. 5, no. 1, pp. 45–48. ISSN 0018-9200.
DOI: 10.1109/JSSC.1970.1050065.
[16] PROMMEE, P., M. SOMDUNYAKANOK,
K. ANGKAEW, A. JODTANG and K. DEJHAN.
Single Low-Supply and Low-Dis o ion CMOS
Analog Mul iplie . In: In e na ional Symposium
on Communica ions and In o ma ion Technolo-
gies. Beijing: IEEE, 2005, pp. 12–14. ISBN 0-
7803-9538-7. DOI: 10.1109/ISCIT.2005.1566843.
[17] DE LA CRUZ-BLAS, C., A. LOPEZ-MARTIN
and A. CARLOSENA. 1.5-V MOS anslin-
ea loops wi h imp o ed dynamic ange and
hei applica ions o cu en -mode signal p ocess-
ing. IEEE T ansac ion on Ci cui s and Sys ems
II: Analog and Digi al Signal P ocessing. 2003,
c
2017 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 786
THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 15 |NUMBER: 5 |2017 |DECEMBER
ol. 50, iss. 12, pp. 918–927. ISSN 1057-7130.
DOI: 10.1109/TCSII.2003.820230.
[18] MENEKAY, S., R. TARACAN and H. KUNT-
MAN. No el high p ecision cu en mode ci cui s
based on he MOS anslinea p inciple. AEU
- In e na ional Jou nal o Elec onics and Com-
munica ions. 2009, ol. 63, iss. 11, pp. 992–997.
ISSN 1434-8411. DOI: 10.1016/j.aeue.2008.08.010.
[19] LOPEZ-MARTIN, A., C. DE LA CRUZ BLAS,
J. RAMIREZ-ANGULO and R. CARVAJAL.
Cu en mode CMOS mul iplie /di ide ci cui
ope a ing in linea /sa u a ion egions. Analog In-
eg a ed Ci cui s and Signal P ocessing. 2011,
ol. 66, iss. 2, pp. 299–302. ISSN 0925-1030.
DOI: 10.1007/s10470-010-9552-y.
[20] SIRIPRUCHYANUN, M. and W. JAIKLA.
A cu en -mode analog mul iplie /di ide based
on CCCDTA. AEU - In e na ional Jou nal
o Elec onics and Communica ions. 2008,
ol. 62, iss. 3, pp. 223–227. ISSN 1434-8411.
DOI: 10.1016/j.aeue.2007.03.009.
[21] AMIRI, A. and A. NADERI SAATLO. Vol -
age mode implemen a ion o highly accu a e ana-
log mul iplie ci cui . In: 23 d I anian Con e -
ence on Elec ical Enginee ing. Teh an: IEEE,
2015, pp. 1059–1062. ISBN 978-1-4799-1972-7.
DOI: 10.1109/I anianCEE.2015.7146368.
[22] CHAISAYUN, I., S. PIANGPRANTONG and
K. DEJHAN. Ve sa ile analog squa e and mul-
iplie ee om body e ec . Analog In e-
g a ed Ci cui s and Signals P ocessing. 2012,
ol. 71, iss. 3, pp. 539–547. ISSN 0925-1030.
DOI: 10.1007/s10470-011-9701-y.
[23] IBARAGI, E., A. HYOGO and K. SEKINE.
A CMOS analog mul iplie ee om mobil-
i y educ ion and body e ec . Analog In e-
g a ed Ci cui s and Signals P ocessing. 2000,
ol. 25, iss. 3, pp. 281–290. ISSN 0925-1030.
DOI: 10.1023/A%3A1008377914605.
[24] CHUNHONG, C. and L. ZHENG. A low-powe
CMOS analog mul iplie . IEEE T ansac ions on
Ci cui s and Sys ems II: Exp ess B ie s. 2006,
ol. 53, iss. 2, pp. 100–104. ISSN 1549-7747.
DOI: 10.1109/TCSII.2005.857089.
[25] TOUMAZOU, C., F. J. LIDGEY and D. G.
HAIGH. Analogue IC design: he cu en -mode
app oach. London: The Ins i u ion o Elec ical
Enginee s, 2008. ISBN 978-0863412974.
[26] WONG, S. and C. A. SALAMA. Impac
o scaling on MOS analog pe o mance.
IEEE Jou nal o Solid-S a e Ci cui s. 1983,
ol. 18, iss. 1, pp. 106–114. ISSN 0018-9200.
DOI: 10.1109/JSSC.1983.1051906.
[27] FILANOVSKY, I. M. and A. ALLAM. Mu ual
compensa ion o mobili y and h eshold ol age
empe a u e e ec s wi h applica ions in CMOS
ci cui s. IEEE T ansac ions on Ci cui s and Sys-
ems I: Fundamen al Theo y and Applica ions.
2001, ol. 48, iss. 7, pp. 876–884. ISSN 1057-7122.
DOI: 10.1109/81.933328.
Abou Au ho s
Ali NADERI SAATLO was bo n in U mia, I an, in
1982. He ecei ed his B.Sc. deg ee in Communica ion
Enginee ing om U mia Azad Uni e si y, in 2005,
he M.Sc. deg ee in Elec ical Enginee ing om
U mia Uni e si y, U mia, I an in 2008, and he Ph.D.
in Elec onics Enginee ing om Is anbul Technical
Uni e si y, Is anbul, Tu key in 2014. Since 2011, he
has been a acul y membe o elec ical enginee ing
depa men o U mia Azad Uni e si y. His esea ch
in e es s a e analog and digi al in eg a ed ci cui
design o uzzy applica ions, uzzy se s and sys ems,
high pe o mance analog ci cui s, and digi al signal
p ocessing. He is he au ho o coau ho o mo e han
30 pee - e iewed pape s in in e na ional and na ional
jou nals and con e ence p oceedings.
Abol azl AMIRI was bo n in Bo azjan, I an,
in 1987. He ecei ed his B.Sc. and M.Sc. deg ees
in Elec onics Enginee ing om he depa men
o Elec ical and Elec onics Enginee ing, Busheh
Azad Uni e si y, Busheh , I an, in 2009 and 2012,
espec i ely. He is cu en ly a Ph.D. s uden o Islamic
Azad Uni e si y o Teh an, I an. His a eas o in e es
include cu en -mode ci cui s design, low powe VLSI
ci cui s, and CMOS analog in eg a ed ci cui design.
He is he au ho o 15 echnical pape s in elec onics.
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