POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 13 |NUMBER: 5 |2015 |DECEMBER
Comphe ensi e Design o a 100 kW/400 V High
Pe o mance AC-DC Con e e
Ghasem ESFANDIARI, Hadi ARAN, Mohammad EBRAHIMI
Depa men o Elec ical and Compu e Enginee ing, Is ahan Uni e si y o Technology, Is ahan 84156-83111,
I an
[email p o ec ed], [email p o ec ed], [email p o ec ed]
DOI: 10.15598/aeee. 13i5.1313
Abs ac . In his pape , a comp ehensi e design o
a 100 kW/400 V, h ee-phase pulse-wid h modula ed
(PWM) AC-DC con e e is p esen ed ha se es as
he on -end powe supply o wide- ange a ying ac-
i e load. This powe supply includes wo se ies s ages;
a six-swi ch AC-DC boos con e e and a DC-DC buck
con e e o egula e 400 VDC a load side. The design
o all induc o s and capaci o s is ul illed using ma h-
ema ical exp essions. In addi ion, small signal mod-
elling and con olle design a e p esen ed in o de o
aise he design e iciency o he p oposed con e e .
Also, due o he high powe applica ion, imp o ed so -
swi ching echniques a e applied. Fu he mo e, sys em-
a ic app oach o design an inpu EMI il e o DC-
DC con e e is explained. The simula ion esul s pe -
o med by PSCAD so wa e show ha high pe o mance
o he p oposed powe supply is ob ained in e ms o s a-
bili y, high powe ac o , high e iciency and low o al
ha monic dis o ion (THD).
Keywo ds
AC-DC con e e , con olle design, small sig-
nal modelling, so -swi ching echnique.
1. In oduc ion
Th ee-phase AC-DC elec ic powe con e sion is widely
employed in di e se applica ions such as adjus able-
speeds d i e, unin e up ible powe supplies, HVDC
sys ems, e c. [1], [2], [3]. Con en ionally, AC-DC con-
e e s known as ec i ie s a e de eloped using diodes
and hy is o s o p o ide uncon olled and con olled
DC powe . They ha e poo powe quali y, low powe
ac o , high THD and low e iciency. Besides, hey
need la ge size o AC and DC il e s. Nowadays, i
is a common conce n o use con e e s which p o ide
educed size, high powe ac o , high e iciency, low
THD and well con olled DC ol age o p esen lexible
sys em ope a ion. The e o e, wi h he ad en o new
solid-s a e sel -commu a ing de ices such as IGBTs,
MOSFETS, GTOs, e c., new con e e s a e known as
swi ch-mode ec i ie s (SMRs), powe ac o co ec o s
(PFCs), PWM ec i ie s, mul ile el and mul i-pulse
ec i ie s [4], [5].
App op ia e modeling and con ol o PWM con e -
e s a e inc easingly being ega ded in high powe ap-
plica ions. As design o induc o s and capaci o s in
powe con e e s a e based on he equi emen s o ap-
plica ion, p ope analy ical exp essions should be ul-
illed. Also, in mos cases o con e e s’ con olle de-
sign, he e a e wo s eps: selec ion o modula ion s a -
egy, which co esponds o open-loop con ol, and de-
sign o dynamic closed-loop con ol. The e o e, de el-
opmen o con e e s’ small signal models is he bes
well-known app oach o design p ope con olle [6],
[7], [8].
High-powe con e e s su e conside ably om low
swi ching equency due o he high swi ching losses.
Thus, ad e se con ol bandwid h and la ge passi e
componen s a e achie ed by low swi ching equency.
On he o he hand, since high swi ching noise is mo e
in ense in high powe con e e s, so swi ching ech-
niques a e he bes op ions o imp o e swi ching noise
as well as swi ching equency. In high powe con e -
e s, ze o-cu en - ansi ion (ZCT) echnique is a pleas-
ing me hod, whe e he IGBTs a e powe de ices [9],
[10]. The opology o he p esen ed 100 kW/400 V
AC-DC con e e is shown in Fig. 1. I includes wo
s ages: a six-swi ch AC-DC boos con e e equipped
wi h so swi ching echnique in se ies wi h a so
swi ched DC-DC buck con e e . The p oposed con-
e e is connec ed o a h ee-phase, 50 Hz u ili y g id
wi h V ms = 220 V.
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This pape is o ganized as ollows: Sec ion 2.
gi es ma hema ical exp essions o design passi e com-
ponen s o he p oposed opology which a e essen ial
o ex ac con e e s’ small signal model and hen o
design con olle . Sec ion 3. p esen s heo e ical ex-
p essions o design auxilia y ci cui s o imp o ed so
swi ching echniques o bo h s ages. Also, Sec ion 4.
includes he de ails o designed EMI il e s o DC-DC
buck con e e . Simula ion esul s a e shown in Sec-
ion 5. . Finally, in Sec ion 6. he conclusion is
d awn.
Va
Vb
VcL
S1
S4
LxCx
S4x
S1x
S3
S6
S6x
S3x
S5
S2
S2x
S5x
C
In
EMI
Fil e
L 2
C 2
DFCb
Lb
Ou
EMI
Fil e
Load
Fig. 1: The opology o p oposed AC-DC con e e .
2. Small Signal Modelling and
Con olle Design
In his sec ion, i s ly passi e componen s o bo h AC-
DC boos and DC-DC buck con e e s a e designed
based on he equi emen s o he p esen ed applica-
ion. Then, small signal models o bo h con e e s a e
ex ac ed o design p ope con olle s.
2.1. Design o Passi e Componen s
1) Six-Swi ch AC-DC Boos Con e e
To ob ain op imal alue o boos induc o and DC-link
capaci o , single-inpu -single-ou pu (SISO) model o
six-swi ch AC-DC boos con e e by sepa a ing he d-
axis and he q-axis dynamics is used [11]. Being non-
minimum phase as an inhe en ea u e in men ioned
con e e is e ealed by a simple igh -hal -plane ze o
(RHPZ) in he small signal con ol- o-ou pu ans-
e unc ion ~ dc(s)/~
d(s). The desi able pe o mance
o con e e is la gely a ec ed by RHPZ which com-
ple ely depends on he boos induc o alue. Since he
loca ion o he RHPZ is closes o imagina y axis in he
complex s-plane unde he wo s ope a ing condi ions,
he main aim is o design boos induc o o achie e
a o able pe o mance. On he o he hand, he alue
o DC-link capaci o depends on he alue o he boos
induc o . High alues o boos induc o s esul s in low
alues o DC-link capaci o s. Thus, he e is a adeo
be ween selec ion o boos induc o and DC-link capac-
i o s. Figu e 2 is used o gain con ol- o-ou pu ans-
e unc ion by SISO model. The di e en ial equa ions
n
ea
eb
ec
L,R
L,R
L,R
ea
eaia
ib
ic
m
Load
SaSb
Sc
icidc
dc
C
S'c
S'b
S'a
an
bn
cn
Fig. 2: A six-swi ch AC-DC boos con e e .
o he sys em in he synch onous o a ing d-q ame
a e as ollows:
Ldid
d +RLid−Lωiq=ed− d,(1)
Ldiq
d +RLiq−Lωid=eq− q.(2)
Cd dc
d =3
4(udid+uqiq)−idc,(3)
whe e edand eqa e sou ce ol ages and idand id ep e-
sen he inpu cu en s in d−q ame. Also, he con ol
inpu s dand qa e ela ed o he ddc by Eq. (4).
d=ud dc
2,
q=uq dc
2,
(4)
whe e udand uqa e swi ching unc ions. Decoupling o
idand idin Eq. (1) and Eq. (2) is achie ed by de ining
dand qas Eq. (5).
d
q= d1+ d2
q1+ q2.
d1
q1=
ud1
dc
2
uq1
dc
2
=Lωiq
−Lωid.
(5)
Applying decoupling con ol a iables, di e en ial
Eq. (1), Eq. (2) and Eq. (3) a e con e d o Eq. (6),
Eq. (7) and Eq. (8).
Ldid
d +RLid=ed− d2=ed−ud2 dc
2.(6)
Ldiq
d +RLiq=eq− q2=−uq2 dc
2.(7)
C dc
d dc
d + dcidc =3
2( d2id+ q2iq) =
=3
4ud2 dcid.
(8)
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In no mal condi ions, he e m q2iqcan be igno ed,
due o ze o alue o iqc ea ed by con ol sys em. By
subs i u ing ud2= 1 −d=D0−~
d, ed=Ed+~ed, idq =
Idq +~
idq, dc =Vdc +~ dc, c=Vc+~ cand D0= 1 −D
in Eq. (6) and Eq. (8), small signal and dc models can
be w i en as Eq. (9), Eq. (10), Eq. (11), Eq. (12) and
Eq. (13).
Ld~
ld
d +RL~
ld=~ed−(D0~ dc − dc ~
d)
2.(9)
Cd~ c
d +~ dc
Rdc
=3
4D0~
ld−Id~
d. (10)
~ dc =~ c+RcCd~ c
dc.(11)
Vdc =
3
4D0Ed
RL
Rdc
+3
8D02
.(12)
Id=Ed
RL+3
8RdcD02
.(13)
The e o e, small signal model o Fig. 2 in d-axis ame
is shown in Fig. 3.
3/2 e( )
3/2 L 3/2 RL3/4 Rdcd( )
id( )
3/4 D:1
3/4 Did( )
3/4 Idd( )
c( )
( )
Rdc
C
Fig. 3: Small signal model o Fig. 2 in d-axis ame.
Equa ion (12) and Eq. (13), exp ess he ela ion
be ween Vdc and Idwi h s eady s a e du y cycle
D, RL, Rdc and Ed. Using Eq. (12), he minimum
and maximum amoun o ou pu ol age is p o ided
by Dmin = 0 and Dmax = 1 − 8RL
3Rdc
, espec i ely.
The e o e, he bounda ies o Vdc can be de ined by
Eq. (14).
2RdcEd
8RL
3+Rdc
≤Vdc ≤
3
4(1 −Dmax)Ed
RL
Rdc
+3
8(1 −Dmax)2
.
(14)
The ou pu - o-con ol ans e unc ion ~ dc(s)
~
ds
is cal-
cula ed based on Fig. 3 as ollowing.
~ dc(s)
~
d(s)=KDC
1 + N1s+N2s2
1 + M1s+M2s2,
N1=(D0VdcRcC−2LId−2RLRcIdC)
D0Vdc −2RLId
,
M1=C(8RL(Rc+Rdc)+3D02RdcRc)+8L
8RL+ 3D02Rdc
,
N2=−2LCRcId
D0Vdc −2RLId
,
M2=8LC(Rc+Rdc)
8RL+ 3D02Rdc
,
KDC =6RdcEd(3D02Rdc −8RL)
(8RL+ 3D02Rdc)2.
(15)
To calcula e boos induc o alue, suppose ha he
ol age d op ac oss he induc o a ull load is x %
o he sou ce ol age Ed, and hen using Eq. (16) he
alue o Lis ob ained.
pR2
L+ (Lω)2Id=x
100Ed⇒
(pR2
L+ (Lω)2)
RL+3
8RdcD02
=x
100,
L=sx
100 RL+3
8RdcD022
−R2
L
2π .
(16)
In Eq. (16), o ha e eal alues o L, he e m un-
de adical mus be posi i e. Thus, ol age d op on
he boos induc o has a minimum alue p esen ed in
Eq. (17).
x≥100RL
RL+3
8RdcD02
.(17)
Also, he alue o D0in Eq. (16) can be acqui ed by
quad a ic Eq. (18) ob ained om Eq. (12).
(RdcVdc)D02−(2EdRdc)D0+8
3RLVdc = 0.(18)
To sol e Eq. (18), he cons ain ∆≥0mus be
sa is ied. Consequen ly, he alue o boos induc o
esis ance has a maximum alue gi en in Eq. (19).
RL≤3E2
dRdc
8V2
dc
.(19)
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To dic a e desi able pe o mance o he p oposed
con e e , he capaci y od DC-link capaci o is se-
lec ed such ha co ne equency ( p) o complex
poles in he ans e unc ion ~ dc(s)
~
d(s) o be app oxi-
ma ely h ee o ou imes less han he equency o
RHPZ. The complex poles o Eq. (15) which a e as
1 + 2ξ
ω0s+1
ω2
0s2= 0, ha e co ne equency p
and damping ac o ξw i en by Eq. (20) and Eq. (21).
p=1
2πs8RL+ 3D02Rdc
8LC(Rc+Rdc).(20)
ξ=C(8RL(Rc+Rdc)+3D02RdcRc)+8L
2p(8LC(Rc+Rdc))(8RL+ 3D02Rdc).(21)
The e o e, Eq. (22) gi es he alue o C.
C=8RL+ 3D02Rdc
8L(Rc+Rdc)(2π p)2.(22)
In his pape , he e e ence ou pu ol age o six-
swi ch AC-DC boos con e e is conside ed Vdc =
650 V. The e o e, o Rdc =4Ωand Ed= 311.1V,
he maximum pe missible alue o boos induc o esis-
ance is RL≤0.343 Ω. Suppose ha RL= 0.1 Ω, hen
Dmax = 0.74 o D0
min = 0.26. Also, using Eq. (18), D0
can be ound as (2600)D02−(2488.8)D0+173.33 = 0 ⇒
D0= 0.88.
Consequen ly using Eq. (17), he minimum accep -
able alue o xwould be 8 %. Finally, conside -
ing x= 12 %, he designed alue o boos induc-
o by Eq. (16) is L= 350 µH. Wi h his induc o
alue, he equency o RHPZ is 485 Hz. Conside ing
p= RHP Z /3and RC= 0.1, he selec ed alue o C
would be 860 µF.
2) DC-DC Buck Con e e
E alua ing DC-DC buck con e e ci cui in Fig. 4 du -
ing ime in e als 0< ≤DT (posi ion 1, swi ch on)
and DT < ≤T(posi ion 2, swi ch o ), he maximum
peak- o-peak ipple cu en o induc o Lis as ollows
[12]:
∆iLmax = 0(1 −Dmin)
sL,(23)
whe e Tis swi ching pe iod, Dis du y cycle, S=
100 kHz is swi ching equency and VO= 400 V is
con e e ou pu ol age.
The minimum induc ance equi ed o main ain he
con inuous conduc ion mode ope a ion o he du y cy-
Ron
ig( )
Vg( )
1
2
L RL
V0( )
R0
c( )
c
RD
C
i( )
VD
Fig. 4: Equi alen ci cui o PWM DC-DC buck con e e .
cle wi h he ange o [Dmin, Dmax]is gi en by Eq. (24).
Lmin =R0max(1 −Dmin)
2 s
,(24)
whe e R0max co esponds o he lowes le el o con-
e e load which is conside ed o be 1.5 kW. The peak-
o-peak ipple ol age is independen o he ol age
ac oss Cand will be de e mined only by he ipple ol -
age ac oss he equi alen se ies esis ance i Eq. (25) is
sa is ied.
Cmin =max(Dmax,1−Dmin)
2 s c
.(25)
V = c∆iLmax.(26)
Usually, V is allowed o be 1 % o ou pu ol age. In
he p oposed opology, he inpu and ou pu ol age o
he buck con e e is se o be 650 V and 400 V, espec-
i ely. The e o e, conside ing 100 V inpu ol age ip-
ple and 90 % e iciency, minimum and maximum alue
o du y cycle is as: Dmin =V0
ηVgmax
=400
0.9·750 =
0.592,Dmax =V0
ηVgmin
=400
0.9·550 = 0.807 ⇒
∆iLmax = 6.5A⇒ cmax =0.01 ·V0
∆iLmax
= 0.615.
Suppose, c= 0.1 Ω, inally, he ob ained minimum
alues o induc o and capaci o o buck con e e a e
217.6 µH and 40.35 µF. In his pape , selec ed passi e
componen s o DC-DC buck con e e a e 250 µH and
100 µF.
2.2. Small Signal Modelling
1) Six-Swi ch AC-DC Boos Con e e
The i s s ep o design a p ope con olle o AC-
DC con e e s is he ex ac ion o di e en ial equa-
ions in he d-q ame o o m con e e ’s a e age
model. Then, small signal analysing should be ul illed
o ob ain con e e ’s small signal model. Nex , a i-
ous ans e unc ions should be calcula ed using small
signal model. The con ol me hod used in his pape
is based on he e e ence [6]. Figu e 5 shows s anda d
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con ol scheme o he con e e in d-q ame. The e-
o e, Eq. (27), Eq. (28) and Eq. (29) which ep esen
he a e age model o a six-swi ch AC-DC boos con-
e e based on line- o-line quan i ies a e used o small
signal modelling.
V e
Vdc
H (s) - Vol age
Compensa o
id e
id
iq
iq e
Kp+Ki/S
Kp+Ki/S
dd1 dd
dq1 dq
3Lω/V e
3Lω/V e
Fig. 5: S anda d con ol scheme o six-swi ch boos con e e
in d-q ame.
did
d
=ω1− dc
e iq−RL
Lid+
1
3LVd−1
3Ldd1 dc.
(27)
diq
d
=−ω1− dc
e id−RL
Liq−1
3Ldq1 dc.(28)
d c
d
=3
2C(dd1id+dq1iq)−1
cidc.(29)
whe e id,iqa e line- o-line cu en s, dd1,dq1a e du y
cycles in d-q ame, Vdis inpu line- o-line ol age in
d-axis and V e is desi ed ou pu ol age. In hese
equa ions, c oss-coupling be ween idand iqcu en s is
educed by e m 1− dc
V e , when wo e ms 3Lω
V e
and −3Lω
V e
a e added o du y cycles dd1,dq1. In a
simila way, by subs i u ing idq =Idq +~
idq, dd1=Dd1+
~
dd1, dq1=Dq1+~
dq1, dc =V e +~ dc and idc =Idc +~
idc
in Eq. (27), Eq. (28) and Eq. (29), small signal and dc
models a e w i en by Eq. (30), Eq. (31), Eq. (32),
Eq. (33) and Eq. (34).
3Ld~
ld
d + 3RL~
ld=−3LωIq
V e −Dd1~ dc−
−~
dd1V e .
(30)
3Ld~
lq
d + 3RL~
lq=3LωIq
V e −Dq1~ dc−
−~
dq1V e .
(31)
Cd~ c
d
= 1.5(~
dd1Id+Dd1~
id+~
dq1Iq+Dq1~
lq)−
−~ dc
Rdc
.
(32)
Dd1=Vd−3RLId
V e
, Dq1=−3RLIq
V e
.(33)
Id=
d−q 2
d−8RLIdcV e −36R2
LI2
q
6RL
.(34)
A e small signal modelling, in his con ol me hod
wo main ans e unc ions ~
lq(s)
~
lq, e (s)and ~ dc(s)
~
ld, e (s)
should be acqui ed. Acco ding o Fig. 5, he i s ans-
e unc ion is used o design a PI con olle o powe
ac o co ec ion. The designed gains o PI con olle
a e KP=40 and Ki=1·105. The second ans e unc-
ion is ob ained o design ol age compensa o . Equa-
ion (35) and Eq. (36) ep esen s he main ans e
unc ions.
Figu e 6 illus a es he con ol diag am used o de-
sign cu en and ol age compensa o s. The con ol
gains a e de e mined in a way ha con ol loops in
Fig. 6 p esen s able pe o mance wi h adequa e phase
and gain ma gins.
Con e e + PI Compensa o
Gi(s)
id, e (s) id(s)
iq, e (s) id(s)
(a)
H (s) G (s)
PI Compensa o Con e e
Vdc, e (s) Vdc(s)
id, e (s)
(b)
Fig. 6: Con ol diag am o (a) cu en and (b) ol age loops o
a six-swi ch AC-DC boos con e e .
In his pape , a h ee-pole one-ze o compensa o
(HV(s)) is used o egula e ou pu ol age.
H (s) = K (s) = K 1 + s
ZV
s1 + s
PV1 + s
PC.(37)
The gain KVshould be su icien ly la ge o ha e
p ope phase ma gin. On he o he hand, o ha e as
ansien esponse, ZVis de e mined based on Eq. (38).
Z ≤1
4ZRHP .(38)
Also, pole PVis ela i ely placed close o ZRHP a e
he c osso e equency, which leads o p ope damp-
ing and gain ma gin in con ol sys em. In addi ion,
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~
lq(s)
~
lq, e (s)=~
ld(s)
~
ld, e (s)=
1 + KP
Ki
s
1 + 3RL+KpV e
KiV e
s+3L
KiV e
s2
.(35)
G (s) = ~ dc(s)
~
ld, e (s)=1.5(RdcKiH+ (RdcX+RpCKiH)s+ (RpCX −3RdcKpL)s2−(3RpCKpL)s3)
KiV e + (KiV e R C+Q)s+ (3L+QR C)s2+ (3LCR )s3,
H=Dd1V e −3RL, X =KpH−3KiL, Q = 3RL+KpV e , R =Rc+Rdc, Rp=RcRdc.
(36)
pole PCis close o equency 1
Rc·C o compensa e
he e ec o capaci o equi alen se ies esis ance. All
con ol gains o designed con olle o h ee di e en
le els o ou pu powe a e depic ed in Tab. 1.
Tab. 1: Con ol gains o HV(s).
Ou pu powe Con ol gains
K Z P Pc
1.5 kW 137 169.5 3030.3 11628
50 kW 100 3125 7142.8 11628
100 kW 300 3125 7142.8 11628
2) DC-DC Buck Con e e
A ypical way o gene a e small signal model o DC-DC
con e e s is he s a e-space desc ip ion, which w i es
he di e en ial equa ions ha desc ibe he con e e
[8]. Gene ally, he s a e equa ions o a sys em can be
w i en in he compac ma ix o m o Eq. (39).
Kdx( )
d =A~x( ) + B~u( ),
~y( ) = C~x( ) + E~u( ).
(39)
Conside ing Fig. 4 as ou sys em, ~x( )is a ec o con-
aining [i( ), c( )], ~u( )con ains [Vg( ), VD] and ~y( )
includes [ig( ), O( )]. Equa ion (39) is w i en wi h
index “1” when swi ch is on, and wi h index “2” when
swi ch is o . A e wa d, Eq. (40) and Eq. (41) ep e-
sen small signal model o he sys em.
Kd~x( )
d =A~x( ) + B~u( ) + ((A1−A2)X+
+(B1−B2)U)~
d( ),
(40)
~y( ) = C~x( ) + E~u( ) + ((C1−C2)X+
+(E1−E2)U)~
d( ),
(41)
whe e A=DA1+D0A2, B =DB1+D0B2, C =
DC1+D0C2, E =DE1+D0E2. In hese equa ions,
Dis s eady s a e du y cycle and D0= 1 −D. The
alue o s a e ec o and ou pu a iables in s eady
s a e a e as ollows:
X=−A−1BU,
Y= (−CA−1B+E)U.
(42)
The small signal ci cui s o analyzed DC-DC buck
con e e is shown in Fig. 7.
c( )
0( )
R0
C
i( )
L
g( )
id( )
ig( ) 1:D
RL+DRon+D'RD
(Vg+VD+(RD-Ron)I)d( )
Fig. 7: Small signal model o a non-ideal DC-DC buck con-
e e .
To con ol he DC-DC buck con e e , he main
ans e unc ion G d(s) = ~ O(s)
~
d(s)should be calcula ed
based on Fig. 7, while ~ g= 0 and ~
iload = 0.
G d(s) = R0·Vi + (Vi R0CRC)s)
(M0)+(M1)s+ (M2)s2,
Vi =Vg+Vd+ (RD−Ron)I,
M1=L+R0CRC+ROU ·RLnC,
M2=ROU ·LC,
M0=R0+RLn,
ROU =R0+RC,
RLn =RL+D0RD+DRon.
(43)
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Then, using con ol diag am o Fig. 8, compensa o
GC(s)is designed in a way ha ou pu ol age is egu-
la ed wi h wide bandwid h and ze o s eady s a e e o .
Gc(s) G d(s)
Compensa o Con e e
V e =0 V0(s)
d(s)
Fig. 8: Con ol diag am o a DC-DC buck con e e .
The e o e, he bes op ion o compensa o seems o
be a PID con olle p esen ed by Eq. (44).
Gc(s) = GC01 + ωL
s1 + s
ωz
1 + s
ωp11 + s
ωp2.(44)
Fo abo e compensa o designed pa ame e s a e:
GC0= 0.3,ωL= 1695,ωZ= 8333.3,ωp1= 117647
and ωp2= 3.45 ·1011.
3. So -Swi ching Techniques
As in high powe con e e s ha d-swi ching echniques
p oduce high swi ching losses and in ense conduc i e
EMI, so -swi ching echniques d aw mo e a en ion in
his ega d. I is well known ha in high powe con-
e e s whe e powe swi ches a e IGBTs, ZCT ech-
niques a e a ac i e. Thus, in his sec ion wo di e -
en imp o ed ZCT (IZCT) echniques a e p esen ed o
bo h s ages o p oposed opology.
3.1. IZCT Technique o Six-Swi ch
AC-DC Boos Con e e
Figu e 9 shows one leg o IZCT ci cui implemen ed o
phase a. I includes wo main swi ches (S1and S2), wo
auxilia y swi ches (S1xand S2x) and one LC esonan
ank (Lxand Cx). In his ci cui , no only each phase
leg has an independen so swi ching, bu also ol age
s esses ac oss all de ices a e p ese ed o he le el o
DC-link ol age [9].
Vdc C0
S2x
S1x
D2x
D1x
Lx
IxVcx
Cx
D1
D2
L
IL
Vsa
Fig. 9: IZCT ci cui o phase a leg.
In Fig. 9, he ela ionship be ween main swi ches and
co esponding auxilia y swi ches is diagonal. I means
S1xis u ned on and u ned o when S1is going o
be u ned on. Also, S1xhas ano he simila ope a ion
when S1is u ned o . The ga ing me hod o bo h main
and auxilia y swi ches is clea ly depic ed in Fig. 10.
S1
S1x
S2x
S2
S1x
S2x
Fig. 10: Ga ing me hod in IZCT echnique o six-swi ch AC-
DC boos con e e .
In o de o design LC esonan ank using Eq. (45),
h ee s eps should be pe o med o ob ain he alues
o T0and Z0.
Lx=Z0T0
2π,
Cx=LxT0
Z2
0
.
(45)
Fi s , no maliza ion ac o s such as maximum DC-
link ol age (Vdcm) and maximum phase cu en (ILm)
a e de e mined and no malized quan i ies a e w i en
as: ILn =IL
ILm
, Vdcn =Vdc
Vdcm
, Z0n=Z0
ILm
Vdcm
, whe e
ILis phase cu en , Vdc is ol age o DC-link and Z0is
esonan ank impedance. Second, in o de o achie e
so swi ching ope a ion, pa ame e ko should sa is y
Eq. (46).
ko =3Vdcn
Z0n·ILn −
−s4−Vdcn
Z0n·ILn 2
+ 1 ≥1.
(46)
The alue o Z0and ko is de e mined by Eq. (46).
In he hi d s ep, pa ame e T0is de e mined by
Eq. (47).
T0=πTo
cos−11
ko .(47)
whe e To is de ice dependen and i should be mo e
han main IGBT cu en all ime (i.e. 0.8 µs). A e -
wa d, he pulse wid h o auxilia y swi ches in on/o
ope a ion can be se by Eq. (48), whe e ko is equal
o ko when Vdcn=1 and ILn=1.
PWsx =T0
21 + ko
2ko m
ILn.(48)
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In his pape , he alue o maximum DC-link ol age
and line cu en a e Vdcm = 650 V and ILm = 240 A.
Then, by designing esonan ank in his load le el,
we can w i e Iln = 1,Vdcn = 1,Z0n=Z0
2.7. On he
o he hand, om Eq. (46) he maximum alue o Z0n
is 0.833. Suppose Z0n= 0.6, hus, o he pa ame e s
can be ound as ollowing: Z0= 2.7·Z0n= 1.62 Ω ⇒
ko = 1.52 ⇒T0= 2.95 µs⇒Lx= 0.76 µH⇒Cx=
0.29 µF, PWSx = 2.2µs.
3.2. IZCT Technique o DC-DC
Buck Con e e
The scheme o IZCT o a DC-DC buck con e e is
shown in Fig. 11. This me hod includes an ac i e
snubbe cell ha is speci ically sui able o IGBT-based
PWM con e e s a high powe and high equency le -
els [10].
Fig. 11: DC-DC buck con e e wi h IZCT echnique.
The con e e wi h ac i e snubbe cell can success-
ully ope a e unde di e en load le els. To design a
sui able esonan ank (L and C ), he ollowing s eps
o maximum load cu en a e conside ed. Fi s , eso-
nan induc o and capaci o a e chosen o le he eso-
nan cu en peak (IRM ) be wice he maximum load
cu en ; he e o e, Eq. (49) should be sa is ied.
IRM =Vg C
L
= 2IOmax.(49)
In he second s ep, L and C a e selec ed such ha
he one hal esonan cycle R o be equal o wice he
all ime o he main IGBT. Thus, Eq. (50) is me .
R
2=π√L C = 2 ,S1.(50)
A e designing esonan ank o ac i e snubbe cell,
auxilia y swi ch is ga ed by a signal wi h he wid h
equal o in e se o main swi ch pulse. Bu , acco ding
o Fig. 12, i should be delayed by TD.
Ma hema ical analysis o he con e e ci cui
demons a ed in Fig. 11, shows ha he alue o TD
is abou a qua e esonan cycle.
TD= R
4=π
2√L C .(51)
Fig. 12: Ga ing me hod in IZCT echnique o DC-DC buck
con e e .
As in his pape he maximum alue o ou pu powe
is 100 kW, consequen ly he alue o IOmax is equal
o 250 A. The e o e, using Eq. (49) we can w i e
Vg C
L
= 2IOmax ⇒ C
L
=2·250
650 = 0.77 ⇒
C = 0.6·L . Also, he second equa ion o ind sui -
able alues o passi e componen s in ac i e snubbe
cell using Eq. (50) is: √L C =2 ,S1
π⇒L C =
2·400 ns
π2
= 6.48 ·10−14. The e o e, he alue o
esonan ank induc o and capaci o and he ime de-
lay equi ed o con ol o auxilia y swi ch a e: L =
330 nH, C = 200 nF, TD= 0.4µs.
4. EMI Fil e s o DC-DC
Buck Con e e s
I is always essen ial o p o ide EMI il e s a he inpu
and ou pu o swi ching con e e s. Inpu EMI il e s
no only a enua e he swi ching noises bu also p o ec
con e e and i s load om inpu ol age dis u bances
[8]. Also, ou pu EMI il e s a e p o ided o a enua e
high- equency DC ol age ipples a load side.
4.1. Inpu EMI Fil e Design
By a enua ing high- equency inpu cu en s, inpu
EMI il e in a DC-DC con e e can limi he a ia-
ion o inpu impedance; consequen ly, i can p o ide
us wi h he oppo uni y o connec a DC-DC buck con-
e e a load side o an AC-DC con e e . Due o he
wide a ia ion o DC-DC con e e s’ inpu impedance,
wi hou inpu EMI il e s an ins abili y in he con ol
sys em can occu by he connec ion o DC-DC con-
e e s in se ies wi h AC-DC one. Al hough by adding
EMI il e s he o me p oblem can be sol ed, a new
p oblem appea s; he inpu il e s change he dynamic
o he con e e s and i leads o ins abili y o he con-
ol sys em again [8]. Conside ing Fig. 13 when inpu
il e is added, he new ans e unc ion o con e e
(G d(s)) is calcula ed by Eq. (52) and Eq. (53).
G d(s) = (G d(s)|z0(s) = 0) ·co ec ion ac o ,(52)
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co ec ion ac o =1 + ZO(s)
ZN()s
1 + ZO(s)
ZD(s).(53)
The e m G d(s)|zO(s)=0is he o iginal con ol-
Fig. 13: Adding an inpu EMI il e o a con e e .
o-ou pu ans e unc ion, ZO(s)is he ou pu
impedance o he il e , ZN(s)is he con e e inpu
impedance Zi(s)unde no mal ope a ion o eedback
con olle which means ~ O(s)=0, and ZD(s)is equal
o Zi(s)when ~
d(s)=0. The e o e, inpu EMI il e is
designed in a way ha he alue o co ec ion ac o o
be app oxima ely uni y. To each his aim, wo ollow-
ing inequali ies should be sa is ied.
kZO(s)kkZd(s)k,kZO(s)kkZN(s)k.(54)
The opology o he used il e in his pape is p e-
sen ed in Fig. 14. The s anda d alues o R and Cb
a e 1 Ωand 4700 µF. These alues comple ely sa is y
abo e cons ain s.
Fig. 14: The opology o inpu EMI il e .
Fo p oposed opology, he inequali ies Eq. (54) can
be ew i en as gene al o m o Eq. (55). On he o he
hand, since ZOhas he highes alue in i s co ne e-
quency and Zihas he leas alue in he co ne e-
quency o ZD, he cons ain Eq. (55) may be insu i-
cien ; he e o e, o ha e he co ec ion ac o s close o
uni y, cons ain Eq. (56) should be also me .
sL
C kZikmin.(55)
1
pL C ≤ω0
4.(56)
The bode diag am o inpu impedances o de-
signed DC-DC buck con e e is d awn in Fig. 15.
The minimum alue o Ziis 2.8 Ωo 8.91 dB a
ω0=5320 ad·s−1. The e o e using inequali y Eq. (55),
we can w i e L <7.84·C . In addi ion, om inequal-
i y Eq. (56) ollowing exp ession can be concluded.
L C ≥14300 ·10−12. The e o e, o design inpu EMI
il e di e en alues can be conside ed o sa is y abo e
cons ain s. In his pape , C =470 µFand L =330 µH
a e selec ed.
Fig. 15: Bode diag am o Ziand di e en inpu EMI il e s.
4.2. Ou pu EMI Fil e Design
In o de o educe high- equency ol age ipples in
ou pu side, he use o one-s age low-pass LC il e s
o Fig. 16 is ecommended [13]. The co ne equency
o his il e should be signi ican ly lowe han he con-
e e swi ching equency. Usually, he Eq. (57) is
ega ded in he design o ou pu EMI il e s.
c= (1 % −10 %) · s=1
2πpL 0C 0
.(57)
In his pape , he co ne equency o il e is a bi-
a ily se 3 % o he swi ching equency. Thus, as a
ypical solu ion, he alue o capaci o C o is equal o
56 µF o an a ailable induc o 50 µH.
Fig. 16: The connec ion o a low-pass il e o a DC-DC con-
e e .
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