elec onics
A icle
To al Ionizing Dose E ec s on a Delay-Based Physical
Unclonable Func ion Implemen ed in FPGAs
Hono io Ma in 1,* , Ped o Ma in-Holgado 2, Yolanda Mo illa 2, Luis En ena 1
and En ique San-Millan 1
1Depa emen o Elec onics Technology, Uni e sidad Ca los III de Mad id, 28911 Leganés, Spain;
[email p o ec ed] (L.E.); [email p o ec ed] (E.S.-M.)
2Cen o Nacional de Acele ado es (CNA, Uni e sidad de Se illa, CSIC), 41092 Se illa, Spain;
[email p o ec ed] (P.M.-H.); [email p o ec ed] (Y.M.)
*Co espondence: [email p o ec ed]; Tel.: +34-91-624-8390
Recei ed: 6 Augus 2018; Accep ed: 23 Augus 2018; Published: 24 Augus 2018


Abs ac :
Physical Unclonable Func ions (PUFs) a e ha dwa e secu i y p imi i es ha a e inc easingly
being used o au hen ica ion and key gene a ion in ICs and FPGAs. Fo space sys ems, hey a e a
p omising app oach o mee he needs o secu e communica ions a low cos . To his pu pose, i is
essen ial o de e mine i hey a e eliable in he space adia ion en i onmen . In his wo k we e alua e
he To al Ionizing Dose e ec s on a delay-based PUF implemen ed in SRAM-FPGA, namely a Ring
Oscilla o PUF. Se e al majo quali y me ics ha e been used o analyze he e olu ion o he PUF
esponse wi h he o al ionizing dose. Expe imen al esul s demons a e ha o al ionizing dose has a
pe cep ible e ec on he quali y o he PUF esponse, bu i could s ill be used o space applica ions
by making some app op ia e co ec ions.
Keywo ds:
physical unclonable unc ion; FPGA; o al ionizing dose; Co-60 gamma adia ion;
ing-oscilla o
1. In oduc ion
Secu ing sensi i e in o ma ion on low-cos sa elli e applica ions has become a majo challenge
o he space indus y. Typical app oaches ha include e y expensi e c yp og aphic p imi i es,
non- ola ile memo y and analogous blocks canno be a o ded in hese small space sys ems. In his
con ex , comme cial Field P og ammable Ga e A ays (FPGAs) ha e u ned ou o be a good solu ion
due o hei lexibili y and cos . Among hei many uses, FPGAs can be dedica ed o ensu ing secu e
sa elli e da a.
A popula solu ion o p o ide secu i y in esou ce cons ained applica ions, such as hose using
FPGAs, is on-chip Physical Unclonable Func ions (PUFs). PUFs a e a e y p omising secu i y p imi i e
used o au hen ica ion and key gene a ion in IC and FPGAs. These secu i y p imi i es a e based
on he impossibili y o c ea ing wo physically exac ly iden ical ICs due o he in luence o andom
and uncon ollable e ec s du ing he manu ac u ing p ocess. These uncon ollable in luences lea e
measu able andom ma ks on some ea u es which possess he po en ial o gene a e enc yp ion keys
di ec ly associa ed o a de ice [
1
]. Thus, PUFs wo k as an unclonable speci ic ea u e ha can iden i y
a ci cui , jus as a inge p in can iden i y a human being. Among he a ious de ice p ope ies ha
can be used o his pu pose, delay-based PUFs dese e special a en ion due o hei s aigh o wa d
implemen a ion. A delay-based PUF exploi s he delay dependency on he andom p ocess a ia ions [
2
].
Well-known examples o his ype o PUF a e he A bi e PUF [3] and he Ring Oscilla o PUF [2].
PUFs can be used o sol e an impo an issue ela ed o he gene a ion o secu e enc yp ion keys
in sa elli e communica ions, emo ing he necessi y o key s o age. None heless, as PUF esponse
Elec onics 2018,7, 163; doi:10.3390/elec onics7090163 www.mdpi.com/jou nal/elec onics
Elec onics 2018,7, 163 2 o 11
depends on some ci cui ea u es ha may be a ec ed by he ope a ional condi ions; i is impo an o
asse he sui abili y o hese p imi i es in ha sh en i onmen s subjec ed o ionizing adia ion. Ionizing
adia ion induces cha ges in he semiconduc o ma e ial ha can be apped in he oxide, al e ing
he elec ical cha ac e is ics o elec onic de ices. This e ec , known as To al Ionizing Dose (TID),
is cumula i e and p oduces a g adual deg ada ion o majo elec ical pa ame e s, such as h eshold
ol age and leakage cu en , ha can e en ually esul in de ice ailu e a a ce ain dose. To he bes
o ou knowledge, he e ec s o TID in delay-based PUFs ha e no been s udied be o e. The e is one
wo k ha s udies he TID e ec s in a CMOS silicon PUF based on ansis o b eakdown [4].
In his wo k, we e alua e he e ec s o ionizing adia ion on a well-known delay-based PUF [
2
]
implemen ed in a SRAM-FPGA. To ha end, we ha e pe o med an ex ensi e es wi h wo di e en
de ices exposed o a adia ion sou ce, pe iodically collec ing he PUF esponse as TID inc eased.
All he ex e nal in luences ha can a ec he PUF esponse ( empe a u e, humidi y, ol age, e c.) we e
con olled. Se e al majo quali y me ics ha e been used in o de o assess he impac o adia ion in
he PUF esponse.
The emainde o his pape is o ganized as ollows. Sec ion 2in oduces he RO-PUF unde s udy
and he ypical e ec s o ionizing adia ion on SRAM-FPGAs. Sec ion 3desc ibes he implemen a ion
o he RO-PUF and he TID es se up. Sec ion 4 epo s he impac o he ionizing dose on he
RO-PUF. Se e al me ics a e p esen ed and analyzed in his sec ion. Finally, Sec ion 5summa izes he
conclusions o his wo k.
2. Backg ound
2.1. Ring Oscilla o Based PUF
A Ring Oscilla o (RO) is a delay loop ha oscilla es a a pa icula equency. Thanks o i s
s aigh o wa d implemen a ion in FPGAs, ROs ha e been widely used in he implemen a ion o secu e
p imi i es such as ue andom numbe gene a o (TRNG). RO-PUFs a e delay-based PUFs ha use
Challenge-Response scheme as a chip au hen ica ion mechanism. A adi ional RO-PUF [
2
] makes use
o many iden ically laid ou ROs o quan i y he manu ac u ing a iabili y. RO oscilla ion equencies
depend on (i) ixed condi ions es ablished a he design phase (i.e., numbe o s ages, place& ou e, e c.);
(ii) andom p ocess a ia ions ( ha once manu ac u ed a e ixed o each single de ice); (iii) dynamic
condi ions de i ed om he ope a ion en i onmen (i.e., supply ol age, empe a u e, su ounding
logic, e c.). Figu e 1depic s he adi ional RO-PUF scheme [
2
] ha consis s o many iden ical ROs,
coun e s and compa a o s.
MUX MUX
Inpu s
C
Coun e
Coun e
Ou pu s
Figu e 1. Ring Oscilla o Physical Unclonable Func ion (RO-PUF) gene al scheme.
Du ing he au hen ica ion p ocess, a pai o ROs (selec ed by a use challenge) a e quan ized by
measu ing and compa ing he RO equencies ( a, b)and gene a ing a esponse bi :
Elec onics 2018,7, 163 3 o 11
=(1 i a> b
0o he wise (1)
An n-bi signa u e o he chip is compu ed om n di e en compa isons be ween RO equencies.
The quali y o he PUF is e alua ed by analysing he signa u es. In mos o he li e a u e, majo secu i y
me ics like uni o mi y, eliabili y and uniqueness a e used o assess he PUF quali y [5].
•Uni o mi y
is a me ic ela ed o he en opy o he sys em. This me ic es ima es he a io o
‘1’ s. ‘0’
in all he esponse bi s gene a ed by a PUF. The uni o mi y is compu ed as ollows o
an n-bi PUF esponse:
Uni o mi y =1
n
n
∑
l=1
i,l×100% (2)
whe e
i,l
is he l- h bi o an n-bi PUF esponse. An uni o m dis ibu ion o 0’s and 1’s (50%) is
expec ed in PUFs ha ha e ull en opy.
•Reliabili y
is a me ic ha quan i ies how s able he PUF esponse is o e a ying ope a ing
condi ions ( ol age, empe a u e, aging, e c.). To ha end, a speci ic challenge is applied o
he RO-PUF in o de o ob ain an n-bi e e ence esponse
( i)
o no mal condi ions ( oom
empe a u e, ideal powe supply ol age). The same n-bi esponse is collec ed a di e en
ope a ing condi ions
( 0
i)
. Finally, he eliabili y is ob ained using he Hamming dis ance (HD)
analysis o esponses.
Reliabili y =1
x
x
∑
y=1
HD( i, i,y0)
n×100% (3)
whe e xis he numbe o samples o each condi ion and
i,y0
is he y- h sample o
( 0
i)
. A lowe
alue o in a-die HD leads o a highe eliabili y.
•Uniqueness
is a measu e o how di e en he PUF esponses o di e en chips among a se o
chips a e. The uniqueness o a popula ion o k-chips is ob ained by compu ing he in e -HD o
he n-bi esponses o he same challenge:
Uniqueness =2
k(k−1)
k−1
∑
i=1
k
∑
j=i+1
HD( i, j)
n×100% (4)
whe e
i
and
j
a e he PUF esponses o chips iand j(
i6=j
). An ideal uniqueness o 50% is
desi ed o he comple e se o chips.
2.2. TID on SRAM FPGAs
TID e ec s on SRAM-based FPGAs, including non- adia ion ha dened, ha e been widely s udied
in ecen yea s [
6
–
8
]. TID causes a deg ada ion o he ansis o s as ionizing adia ion accumula es on
he componen . This deg ada ion leads o c ea ing apped cha ges ha will slowly a ec he elec ical
pa ame e s o he de ice ( h eshold ol age
(V h)
and leakage cu en ) [
9
]. In his con ex , NMOS and
PMOS ansis o s beha e di e en ly. The apped cha ges will nega i ely a ec he h eshold ol age
inc easing he leakage cu en in NMOS ansis o s. Con e sely, in PMOS ansis o s he h eshold
ol age will be inc eased and he leakage educed. In addi ion, a de e io a ion o noise pa ame e s
can be obse ed [
10
]. All hese e ec s a e dependen on many ac o s such as dose a e, he ype o
adia ion applied, empe a u e, e c.
Elec onics 2018,7, 163 4 o 11
A de ice le el, an inc ease o he p opaga ion delay o he ci cui s ins an ia ed in he FPGA is
he main aspec o conside . Faul s can appea when he iming cons ain s a e iola ed due o his
inc emen [11].
3. Expe imen al Se up
3.1. De ice Unde Tes
The adia ion expe imen s ha e been ca ied ou on wo Xilinx XC3S500E FPGA, manu ac u ed on
90 nm CMOS echnology. In he emainde o he pape , hese De ices Unde Tes (DUTs) a e e e ed
o as FPGA1 and FPGA2. The clock is se using he on-boa d 50MHz c ys al oscilla o . Two high
p ecision ol age sou ces (p og ammable HP 66103A DC powe modules) ha e been used in o de o
se and moni o he co e ol age (1.2 V) and he I/O ol age (3.3 V).
A con en ional RO-PUF consis ing o 512 iden ically laid-ou ROs has been implemen ed. Each
o he ROs consis s o ou in e e s and a NAND ga e, he la e being able o enable/disable he
oscilla ion. A ha d mac o ha occupies one Con igu able Logic Block (CLB) has been c ea ed in o de
o gua an ee he same placemen and ou ing o all he ROs. This ha d mac o has been eplica ed in
he middle o he FPGA c ea ing a 16
×
32 a ay. Du ing he expe imen , each RO is ac i a ed a a
ime du ing 13,000 clock cycles using i s enable signal. The es o he RO-PUF logic (mul iplexe s,
coun e s, decode s, e c.) ha e been implemen ed in o he FPGA zones in o de o limi he impac o
he su ounding logic on RO equencies. An RS232 communica ion p o ocol has been used in o de o
ans e he measu ed RO equencies o he hos compu e . A CRC has been implemen ed in o de o
ensu e he in eg i y o he communica ion.
The ope a ing condi ions o he oom ( empe a u e, p essu e and humidi y) ha e been con olled
in o de o gua an ee ha hese condi ions do no a ec he RO equencies.
3.2. TID Se up
The TID es s ha e been pe o med a he RADLAB acili y, he Gamma Radia ion Labo a o y
ins alled in he Cen o Nacional de Acele ado es (CNA), Spain. The RADLAB [
12
,
13
] is based on
a Co-60 adioac i e sou ce, placed in o a Gamma beam X200 i adia o . The a e age alue o he
pho ons ene gy is 1.25 MeV, which is usually es ablished o es ing pu poses.
The i adia o has a conical opening which con ains a a iable collima o , p o iding di e en
squa e i adia ion ields. Du ing a i s i adia ion se up, he maximum i adia ion ield was used and
no shielding was applied on he boa d, so all he componen s o he PCB we e exposed o adia ion,
no only he DUT (FPGA). As a consequence, some issues we e obse ed be o e de ec ing any e ec in
he DUT. Fo he subsequen campaigns, he i adia ion ield was educed o ocus he main gamma
beam on he FPGA unde s udy. Mo eo e , he se up was addi ionally imp o ed wi h a cus om pa ial
shielding on he boa d, signi ican ly dec easing he dose a e on he mos sensi i e componen s o he
PCB (Figu es 2and 3).
Since he DUT is loca ed in one speci ic posi ion o he PCB submi ed o adia ion, a dummy
boa d was placed o each se up p epa a ion in he same posi ion as he SAMPLE in o de o ca y ou
he dosime y (Figu e 4), ha is, o measu e he dose a e on he DUT, be o e s a ing he i adia ion es .
The dosime y sys em is composed by a Fa me ioniza ion chambe connec ed o he UNIDOS
Webline elec ome e , bo h o hem by PTW. Fi s ai ke ma a e is ob ained and he dose a e in silicon
(Si) is calcula ed aking in o accoun he con e sion ac o s. The dose a e uni o mi y in he adia ion
ield was be e han 95% and he expanded unce ain y associa ed wi h he measu emen was
±
4.2%.
Elec onics 2018,7, 163 5 o 11
Figu e 2. Shielding o he PCB a ached o he co e o he il e box.
Figu e 3. P o ile iew o he shielding be ween he PCB and he co e o he il e box.
Figu e 4.
PCB cus omized o ca y ou he dosime y measu emen s wi h he e e ence poin o he
ioniza ion chambe placed exac ly in he posi ion o he de ice unde es (DUT).
The dosime y and he i adia ion un we e pe o med using a il e box, wi h he DUT inside,
acco ding o he TID s anda d om Eu opean Space Agency [
12
]. This con aine has 1.5 mm Pb (lead)
wi h an inne lining o 2 mm Al (aluminium). The on co e is made o Al, excep in he egion close
o he DUT, whe e he build-up ma e ial is polyme hilme ac ila e (PMMA). In Figu e 5is depic ed he
inal se up.
The FPGA1 and FPGA2 we e exposed o a o al dose o 500 k ad(Si), wi h he dose a es o
5.2 k ad(Si)/h and 5.3 k ad(Si)/h, espec i ely.

Elec onics 2018,7, 163 6 o 11
Figu e 5.
Fil e Box wi h he PCB (and DUT) inside and he connec ions o he di e en po s and
powe supply.
4. Expe imen al Resul s and Discussion
This sec ion desc ibes he esul s o he i adia ion expe imen s on he wo DUTs.
4.1. FPGA Pa ame e s and Func ionali y
The co e cu en s and ol ages we e con inuously measu ed du ing he en i e expe imen .
The p e-i adia ion ope a ion cu en s we e measu ed o be 23.9 mA o FPGA1 and 29.09 mA o
FPGA2. A he end o he expe imen [500 k ad(Si)], he cu en s eached 95.97 mA and 83.35 mA,
espec i ely. These in e nal co e cu en s a e wi hin he limi s o he endo ecommenda ions o his
FPGA ( ypical: 25 mA; maximum: 106 mA). Ne e heless, he i s ailu e was egis e ed a 410 k ad(Si)
in FPGA1. This ailu e was ela ed o he RS232 communica ion p o ocol and a ep og amming o he
FPGA was necessa y in o de o eco e no mal unc ionali y. This kind o e o was ep oduced un il
he end o he expe imen . In FPGA2, no ailu es we e egis e ed. Bo h DUTs could no be econ igu ed
any mo e a e he deposi ed dose eached 440 k ad(Si). The aul y beha iou ha appea ed only
in FPGA1 can be explained by he ba ch di e ence on he DUT o he lowe dose a e ( he esul s
ypically show ma ginally highe dose deg ada ion h eshold a lowe dose a es [14]).
Figu e 6depic s he co e cu en s o FPGA1 and FPGA2 h ough he i adia ion expe imen . I is
no ewo hy ha o bo h DUTs he co e cu en inc eased linea ly wi h he dose. This inc ease o leakage
cu en is ully accoun ed o in he c ea ion o elec on-hole pai s due o he ioniza ion o SiO2[15].
Elec onics 2018,7, 163 7 o 11
0 100 200 300 400 500
To al Dose (k ad(Si))
0.02
0.04
0.06
0.08
0.1
0.12
0.14
ICC (A)
FPGA1
FPGA2
Rep og amming E o (440 K ad)
Fi s Communica ion E o (410 K ad)
Figu e 6. In e nal Co e Cu en s. adia ion.
4.2. Delay Va ia ion o he RO Loop
RO equencies play a key ole in he RO-PUF au hen ica ion scheme, he e o e hey ha e been
subjec ed o exhaus i e analysis du ing he whole expe imen . Fo each RO, we ha e ca ied ou
100 equency acquisi ions in o de o imp o e he measu emen e o by a e aging he alues.
A p e-i adia ion condi ions, he a e age RO equencies o FPGA1 and FPGA2 a e 196.12 MHz and
199.16 MHz espec i ely. A he end o he expe imen [500 k ad(Si)], he a e age RO equencies o
FPGA1 and FPGA2 ha e dec eased o 195.1 MHz (0.5%) and 197.92 MHz (0.6%) espec i ely. Figu e 7
shows how he 512 RO a e age equencies o FPGA2 changed du ing he expe imen . I can be
app ecia ed ha a e a i s sha p dec ease a 10 k ad(Si), all he ROs ollow he same endency. I is
also wo hy o no e ha he e a e no many in e sec ions be ween he di e en lines, which indica es a
good equency s abili y. These esul s a e e y simila o hose epo ed in [
16
], whe e he e ec s o
ageing in a RO-PUF we e s udied.
Figu e 8shows he dis ibu ion o he a e age equencies a p e-i adia ion condi ions and a he
end o he expe imen . Once again, he equency s abili y can be highligh ed. The esul s o FPGA1
a e analogous o hose depic ed in Figu es 7and 8.
0 50 100 150 200 250 300 350 400 450 500
To al Dose (k ad(Si))
1.94
1.95
1.96
1.97
1.98
1.99
2
2.01
2.02
2.03
RO equencies (Hz)
108
Figu e 7. RO equencies s. adia ion.
Elec onics 2018,7, 163 8 o 11
1.94 1.95 1.96 1.97 1.98 1.99 2 2.01 2.02 2.03
RO equencies 108
0
10
20
30
40
50
60
70 End o he Expe imen
P e-i adia ion
1.96 1.97 1.98 1.99 2 2.01 2.02 2.03
RO equencies a P e-i adia ion condi ions (Hz) 108
1.94
1.95
1.96
1.97
1.98
1.99
2
2.01
RO equencies a he end o he expe imen (Hz)
108
Figu e 8.
FPGA2 equency dis ibu ion and sca e plo a p e-i adia ion condi ions and a 500 k ad(Si).
4.3. RO-PUF Quali y Fac o s
We ha e calcula ed he main me ics ela ed o PUF quali y in o de o e alua e he sui abili y
o he RO-PUF o space applica ions. To ha end, a 511-bi esponse has been gene a ed o each
accumula ed doses. This 511-bi esponse is ex ac ed by compa ing he a e age equencies o adjacen
pai s o ROs in he a ay.
4.3.1. Uni o mi y
Figu e 9depic s he uni o mi y o he PUF esponse du ing he expe imen . Fo bo h DUTs,
he esponse bi s a e ai ly e enly dis ibu ed among ‘0’ and ‘1’, showing almos an ideal dis ibu ion
h oughou he en i e expe imen . The a e age numbe o 1’s in he PUF esponse o FPGA1 and
FPGA2 a e 51.43% and 49.61%, espec i ely.
0 100 200 300 400 500
To al Dose (k ad(Si))
48.5
49
49.5
50
50.5
51
51.5
52
52.5
53
% Uni o mi y
FPGA1
FPGA2
Figu e 9. Uni o mi y s. adia ion.
4.3.2. Reliabili y
Figu e 10 shows he in a-die Hamming dis ance calcula ed using Equa ion (2). The p e-i adia ed
511-bi esponse has been se as he e e ence esponse. In bo h FPGAs, he ini ial in a-die HD is low
(>3%) and i inc eases wi h he accumula ed dose. This means ha he e is an inc easing deg ada ion
o he RO pe o mance ha is p opo ional o he adia ion dose.
Elec onics 2018,7, 163 9 o 11
0 100 200 300 400 500
To al Dose (k ad(Si))
2
3
4
5
6
7
8
9
10
11
12
% In a-die Hamming dis ance
FPGA1
FPGA2
Figu e 10. Reliabili y s. adia ion.
4.3.3. Uniqueness
Figu e 11 p esen s he in e -die Hamming dis ance ob ained using Equa ion (3). Once again, a loss
on he uniqueness can be obse ed and is p opo ional o he accumula ed dose.
0 100 200 300 400 500
To al Dose (k ad(Si))
40
41
42
43
44
45
46
% In e -die Hamming dis ance
Figu e 11. Uniqueness s. adia ion.
4.4. Resul Analysis
The inc ease in he co e cu en s a e consis en wi h o he esul s epo ed in he li e a u e o he
same FPGA [
17
]. In he case o FPGA1, he i s ailu e occu ed a 410 k ad(Si), which is also simila
o he i s ailu e epo ed in [
17
], whe e he DUT wo ked p ope ly un il 345 k ad(Si). Rega ding he
RO- equencies, he expe imen s ha e shown ha he e is a good s abili y on he equencies and he
changes due o he accumula ed dose a e negligible.
On he o he hand, he quali y me ics show ha he accumula ed dose makes he esponses
p oduced by he PUF un eliable. None heless, as he uni o mi y me ic shows, he andomness o
he esponse emains una ec ed by he o al dose. This may be due o he dec ease o he noise
pa ame e s ha ha e a di ec in luence on he andomness. Reliabili y is he key me ic o e alua e
a e he deploymen o PUFs in space. I a p e-i adia ion condi ions all he me ics ha e accep able
alues, only a dec ease in he eliabili y due o ionizing adia ion can a ec he es o he me ics.
In his case, he eliabili y me ic shows a li le deg ada ion ha can be co ec ed using some ypical
coun e measu es such as using only RO pai s wi h maximal equency di e ence [
2
] o using quan ize s
wi h eliabili y gua an ees [
18
]. Rega ding uniqueness, as a colla e al e ec o un eliabili y, he esul s
also show a deg ada ion o he me ic.