CMOS SPADs Selec ion, Modeling and
Cha ac e iza ion Towa ds Image Senso s
Implemen a ion
Manuel Mo eno Ga c´
ıa, ´
Osca Gue a Vinuesa, Roc´
ıo del R´
ıo Fe n´
andez, Bel´
en P´
e ez Ve d´
u
and ´
Angel Rod ´
ıguez V´
azquez
Ins i u e o Mic oelec onics o Se illa, IMSE-CNM (CSIC/Uni e sidad de Se illa)
C/Ame ico Vespucio, s/n, 41092 Se ille (Spain)
Email: [email p o ec ed]
Abs ac —The selec ion, modeling and cha ac e iza ion o
Single Pho on A alanche Diodes (SPADs) a e p esen ed. Wo king
wi h he s anda d 180nm UMC CMOS p ocess, di e en SPAD
s uc u es a e p oposed in combina ion wi h se e al quenching
ci cui s in o de o compa e hei ela i e pe o mances. Va ious
con igu a ions o he ac i e egion and he p e en ion o he
p ema u e edge b eakdown a e es ed, looking o a minia u i-
za ion o he de ices o implemen image senso a ays wi hou
loses in hei pe o mance.
I. INTRODUCTION
Single Pho on A alanche Diodes (SPADs) a e p/n junc ions
biased abo e hei b eakdown ol age [1], in he so-called
Geige mode [2]. In his si ua ion he elec ic ield is so high
ha a single ca ie in he deple ion egion can o igina e a
sel -sus ained a alanche cu en in he milliampe es ange [3].
An addi ional ci cui is equi ed o use he SPAD as a single-
pho on de ec o . I is he quenching ci cui , and i s mission is o
ex inguish he a alanche be o e damage o he s uc u e occu s.
The simples one consis s o a high- alue ballas esis o
connec ed in se ies o he diode (Rqin Fig. 1(a)), which is
aimed o lowe he bias ol age below he b eakdown ol age
[4], [5]. When an a alanche is igge ed, he cu en lowing
h ough he diode inc eases, inducing a ol age d op o e he
ballas esis o . The cu en s a s dec easing un il i eaches a
h eshold alue called la ching cu en , a which he a alanche
is no mo e sel -sus ained [4]. Fig. 1(b) shows he ypical I-V
piecewise linea cha ac e is ic o he SPAD.
SPADs a e a dedica ed ype o pho ode ec o s ha a e
a ac ing inc easing in e es . Thei ab ica ion in s anda d
CMOS echnologies allows o in eg a e all pe iphe al blocks
equi ed o ision sys ems (a ays o SPADs and digi al
p ocessing elec onics) on he same monoli hic chip. Thus,
he combina ion o high gain and quan um e iciency, along
wi h hei small size, low ope a ion ol age and insensi i i y
o magne ic ields make SPADs pa icula ly a ac i e o
di e en imaging and medical applica ions [6].
In his pape we p esen a es chip wi h se e al SPAD
s uc u es o be es ed, oge he wi h di e en quenching
ci cui s ha ha e been chosen using he in o ma ion p o ided
by a p op ie a y model o SPADs based on [7]. The main
(a)
Vb
Is
a alanche
no a alanche
Rb
Ila
VD
ID
GEIGER MODE
OF OPERATION
(b)
Fig. 1. (a) Scheme o illus a ing he ope a ion o he SPAD wi h passi e
quenching. (b) I-V cha ac e is ic o he SPAD.
objec i e o his wo k is o s udy he po en iali y o di e en
s uc u es and quenching ci cui s o gene a ing image senso
a ays, using he s anda d 180nm UMC CMOS p ocess.
II. SELECTION OF CMOS SPADSSTRUCTURES
In his sec ion a a ie y o SPAD s uc u es ha ha e been
used so a in di e en echnological nodes is p esen ed. The
di e en modi ica ions in he s uc u e a e in ended o a oid
he p ema u e edge b eakdown (PEB). I consis s o a spu ious
a alanche ha a o able akes places a he edges o he de ice
ac i e a ea, educing i s sensi i i y [1]. The s uc u es a e he
ollowing:
1) Simple p+/nwell diode: This is he basis s uc u e and
does no include any mechanism o a oid PEB.
2) P+/nwell diode wi h well gua d ing: A deepe and
lowe doped implan is in oduced in he pe iphe y o
he junc ion o aise he b eakdown ol age in his egion
wi h ega d o he cen e o he ac i e a ea [8].
3) Twell/nwell diode: The junc ion is o med be ween he
lowe doped and deepe well, and he nwell o dec ease
he da k coun a e (DCR) and change he maximum o
he pho on de ec ion e iciency (PDE) [9].
978-1-4673-1260-8/12/$31.00 ©2012 IEEE 332
4) Con ol ga e gua d ing: A biased poly laye ha
changes he shape o he deple ion egion oge he wi h
a well implan a a ce ain dis ance o he ac i e a ea
a e in oduced o inc ease he b eakdown ol age a he
edge o he junc ion [8].
5) Vi ual gua d ing: A highe doped implan is in o-
duced in he cen al egion o he ac i e a ea o enhance
he elec ic ield in his zone [9].
6) Di used gua d ing: A lowe doped and deepe gua d
ing in he pe iphe y o he de ice is o med by di u-
sion, which imposes minimum size cons ain s [10].
7) Shallow T ench Isola ion gua d ing: An STI is used
o implemen ing an a ea-e icien gua d ing, inc easing
he ill ac o and educing he pixel a ea [11].
Al hough cases 5 and 7 seem o be p omising s uc u es
in e ms o scalabili y, hey will no longe be aken in o
accoun since he use o s anda d CMOS echnologies, o
a oid excessi e ab ica ion expenses, imposes es ic ions on
he a ailabili y o laye s. Mo eo e , case 6 will be neglec ed
because o i s minimum size cons ain s and high DCR [5],
which a e e y impo an d awbacks o image applica ions
using senso a ays.
Besides o he a ia ions in he s uc u e, changes in he
SPAD sizes and geome ies a e o in e es in o de o de-
e mine he op imal image sensing esponse. This is done
by a ying he diame e o he ac i e a ea and implemen ing
SPADs wi h ci cula and oc agonal shapes.
Wi h ega d o he inal applica ion, i is in e es ing o
compa e he ela i e pe o mances o he di e en SPADs in
e ms o se e al pa ame e s be o e designing he senso a ay.
These main pa ame e s ha cha ac e ize SPADs ope a ion a e:
•S a ic I-V cha ac e is ic: This measu emen allows o
de e mine he b eakdown ol age o he SPAD and i s
in e nal esis ance o check he alidi y o he assumed
piecewise linea cha ac e is ic.
•Noise: The main sou ce o in e nal noise is usually asso-
cia ed o da k coun s, which a e p oduced by pho ons and
he mally gene a ed ca ie s ha igge a new a alanche.
The a e pulses also con ibu e o he noise. They happen
when he gene a ed ca ie s a e apped by c ys al de ec s
and a e a ce ain ime delay hey a e eleased p oducing
an a alanche [8]. In he case o SPAD a ays, he c oss alk
will also in luence he o al in e nal noise o he de ice.
I occu s i ca ie s gene a ed in one pixel igge an
a alanche in a nea one.
•Dead ime: Lapse o ime du ing which he SPAD
canno de ec he a i al o new pho ons. I comp ises
he quenching, du ing which i akes place he ex inc ion
o he a alanche, and he ese phase, whe e he ini ial
bias condi ions a e es o ed. Some imes, i is possible o
con ol he pe iod o ime be ween hese wo s ages, he
hold o ime, and see how i a ec s he a e pulsing [4].
•PDE: I ep esen s he p obabili y ha a single abso bed
pho on gene a es an a alanche cu en . I s alue depends
on he wa eleng h o he inciden pho ons [2].
Fig. 2. Cha ge con ol model used o ep esen ing he SPAD beha io .
•Fill ac o : When dealing wi h SPAD a ays, i is impo -
an o inc ease he ill ac o , which is he a io be ween
he ac i e a ea and he o al a ea o he SPAD [12].
•Time esolu ion: Va ia ion o he posi ion in ime o
he di e en ca ie a alanche pulses when he SPAD is
illumina ed wi h a pulsed lase [12].
III. MODEL PARAMETRIZATION
T adi ionally, he model used o he SPAD is ha shown
in [13], bu he e a e new e sions like ha in [7] wi h a
mo e accu a e desc ip ion o he de ice. In his wo k he
model in oduced in [7] has been upda ed o deal wi h in e-
g a ed de ices. This has been done by including he pa asi ic
capaci ances p esen in each s uc u e and wi h a p ope
pa ame iza ion o ou speci ic echnology.
Using he in o ma ion p o ided by he simula ion o a
p+/nwell diode om he echnology, a wo-s ep linea I-V
cu e o each one o he SPAD s uc u es has been ob ained.1
Ispad =(Is, VD< Vb
Is+Vn
Rb
ln 1 + e
VD−Vb
Vn, VD> Vb
(1)
Eq. (1) models he ol age dependence o he s a ic cu en
h ough he SPAD, whe e Isis he sa u a ion cu en , Rb is
he in e nal esis ance, Vnis a no maliza ion ol age, Vb is he
b eakdown ol age, and VDis he ol age ac oss he SPAD.
Looking a he di e en diode s uc u es (see Fig. 3), i can
be seen ha he e exis s a pa asi ic nwell/psubs a e diode. As
illus a ed in Fig. 2, his diode has also been inco po a ed in
he model h ough he inclusion o he ca hode- o-subs a e
capaci o o allow a comple e desc ip ion o he dynamic
beha io o he de ice.
The in o ma ion ob ained by simula ing he SPAD h ough
i s model, oge he wi h he di e en quenching ci cui s in-
cluded in he es chip has been used o design he la e
p ope ly. As i will be shown in he nex sec ion, h ee di e en
opologies o he quenching ci cui will be s udied in o de
o compa e hei pe o mance in e ms o noise (da k coun s
and a e pulsing) and ime.
1The diode wid h and leng h ha e been chosen ying o minimize he
ela i e e o o a ea and pe ime e compa ed o ci cula and oc agonal shapes.
333
(a) (b)
(c) (d)
Fig. 3. SPAD s uc u es implemen ed in he es chip: (a) p+/nwell diode
wi h well gua d ing, (b) well/nwell diode, (c) diode wi h con ol ga e gua d
ing, (d) simple p+/nwell diode.
The compa ison be ween he di e en SPAD s uc u es
oge he wi h hei co esponding quenching ci cui s will be
done in e ms o some o he pa ame e s shown p e iously.
To deal wi h he desi ed applica ion, special a en ion will
be paid o he s a ic I-V cha ac e is ic o he di e en es
s uc u es, he equency o he noise sou ces, he dead ime
and he change in he PDE depending on he wa eleng h o
he inciden pho ons and he s uc u e o he SPAD.
IV. CHARACTERIZATION CIRCUITRY AND TESTCHIP
As s a ed be o e, o he ab ica ion o he es chip he s an-
da d 180nm UMC CMOS p ocess has been chosen. Due o he
cons ain s imposed by he laye a ailabili y o he echnology
i is no possible o implemen he i ual gua d ing and
he STI gua d ing s uc u e. Mo eo e , he minimum size
cons ain s o he di used gua d ing s uc u e is a p oblem
when implemen ing SPAD a ays, so i was disca ded. Only
he i s ou SPAD s uc u es al eady desc ibed in sec ion II
will be implemen ed. They a e shown in Fig. 3.
Rega ding he quenching ci cui y, h ee di e en al e na-
i es ha e been implemen ed:
•Simple passi e quenching ci cui , implemen ing he ba-
llas esis o wi h ei he an NMOS ansis o o a passi e
esis ance.
•Addi ion o he p e ious s uc u e o an ac i e ese
b anch o speed up his s age.
•Passi e quenching and ac i e ese ci cui , which includes
a mechanism o con ol he hold-o ime.
This i s wo quenching ci cui s a e pu oge he (see Fig.
4), wi h he possibili y o ac i a ing o no he ac i e b anch.
This allows o s a om he simples case and hen see
he changes when wo king wi h a mo e complex quenching
ci cui . The compa ison will be made in e ms o :
•Time: Va ia ion o he dead ime and ime esolu ion.
(a)
(b)
Fig. 4. (a) Fi s quenching ci cui . (b) Second quenching ci cui .
TABLE I
MAIN CHARACTERISTICS OF THE DIFFERENT SPAD STRUCTURES.
Tes Type Gua d Type o Ac i e Quenching
s uc u e o diode ing shape a ea (φ) ci cui
#1 p+/nwell well ci cula 7µm Fig. 4(a)
#2 p+/nwell well ci cula 14µm Fig. 4(a)
#3 p+/nwell well ci cula 21µm Fig. 4(b)
#4 well/nwell – ci cula 14µm Fig. 4(a)
#5 p+/nwell well oc agonal 14µm Fig. 4(a)
#6 p+/nwell – ci cula 14µm –
p+/nwell well ci cula 14µm Fig. 4(b)
#7 p+/nwell con ol ci cula 14µm Fig. 4(b)
ga e
•Noise: F equency o da k coun and a e pulsing e en s
depending on he quenching ci cui y.
•Abili y o de ec ing he incoming pho ons a di e en
wa eleng hs when adding complexi y o he quenching
ci cui s, which will depend on he dead ime and PDE.
The quenching ci cui al e na i es and he combina ion o
di e en SPAD s uc u es, sizes and shapes esul in o se en
di e en es s uc u es ha a e de ailed in Table I. Tables II
and III show he alues o he geome ic pa ame e s2and he
s a ic I-V pa ame e s o he di e en s uc u es. As said be o e,
his in o ma ion was used o he design o he wo quenching
ci cui s.
Fig. 5 shows he layou o he di e en s uc u es oge he
wi h he es ci cui y. The measu emen s expec ed o be done
wi h he es chip a e he ollowing:
•The I-V cha ac e iza ion will be ob ained o each s uc-
2ADand PD e e s o he dimensions o he junc ion diode, while Awell
and Pwell a e associa ed o he nwell/psubs a e pa asi ic diode.
334
TABLE II
GEOMETRIC PARAMETERS OF THE DIFFERENT SPAD STRUCTURES.
Tes s uc u e PD(µm) AD(µm2)Pwell (µm) Awell (µm2)
#1 22.0 38.5 36.4 105.7
#2 44.0 154.0 58.4 271.7
#3 66.0 346.4 80.4 514.7
#4 46.4 162.4 61.6 286.3
#5 44.0 154.0 55.9 248.8
#6 44.0 154.0 61.6 301.7
#7 44.0 154.0 51.9 214.3
TABLE III
FITTING PARAMETERS OF THE I-V CHARACTERISTIC TO EQ. (1).
Tes S uc u e Vn(mV) Vb (V) Rb (Ω)Is(A)
#1 10 9.68 823.4 9.7×10−18
#2 10 9.70 207.2 2.8×10−17
#3 10 9.73 91.9 5.6×10−17
#4 10 9.70 207.2 2.8×10−17
#5 10 9.70 207.2 2.8×10−17
#6 10 9.70 207.2 2.8×10−17
#7 10 9.70 207.2 2.8×10−17
u e o see how good he i wi h he model is.
•A measu emen o he dead ime in he di e en con-
igu a ions o he quenching ci cui s will be also done,
oge he wi h he ime esolu ion using a pulsed lase .
•The noise will be cha ac e ized a e lea ing he SPADs
in he da k o se e al hou s. The a e pulsing can be
ob ained by compa ing he esul s wi h he ac i e and
passi e echa ge i i s p obabili y is high. I no , i has o
be s udied in a ime scale a ound one o de o magni ude
smalle han o he DCR (besides educing he dead ime,
as s a ed be o e).
•The PDE will be measu ed a e emo ing he in luence
o he da k coun and a e pulsing e en s.
Once he ela i e pe o mance o he di e en es s uc u es
is compa ed, he e will be mo e in o ma ion o be used ha
will allow o ad ance in he design o image senso a ays.
V. CONCLUSIONS
A e iew o di e en SPAD s uc u es and hei p incipal
cha ac e is ics is p esen ed. Taking in o accoun he es ic ions
in e ms o laye a ailabili y imposed by he s anda d 180nm
UMC CMOS echnology, and he inal a ge o implemen ing
image senso CMOS SPAD a ays, h ee o he s uc u es a e
ejec ed. A p op ie a y model based on [7] and adap ed o
in eg a ed de ices is de eloped o he design o he quenching
ci cui y ha is connec ed o he SPADs. The combina ion
o se e al SPADs wi h dis inc size, shape o s uc u e, along
wi h di e en quenching ci cui s esul s in se en es s uc u es
whose ela i e pe o mance in e ms o he main pa ame e s
o he SPADs will be s udied. This wo k p o ides use ul da a
owa ds he implemen a ion o image senso s in a s anda d
CMOS echnology.
ACKNOWLEDGMENT
The au ho s would like o hank he Spanish Na ional
Resea ch Council (Consejo Supe io de In es igaciones
Fig. 5. Layou iew o he di e en s uc u es, oge he wi h he quenching
and es ci cui y.
Cien ´
ı icas, CSIC) o he JAE-PREDOC esea ch g an ha
suppo s he wo k he e p esen ed.
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