A PROCESSING ELEMENT ARCHITECTURE FOR HIGH-DENSITY
FOCAL PLANE ANALOG PROGRAMMABLE ARRAY PROCESSORS
G.
LiChn-Cemb ano,
S.
Espejo, R. Dominguez-Cas o and
A.
Rod iguez- Vhzquez
Ins i u o de Mic oelec dnica de Se illa
-
CNM-CSIC
Edi icio CICA-CNM, C/Ta ia s/n,
4
101
2-
Se illa, SPAIN
Phone:
+34 95 4239923,
Fax:
+34 95 423 1832,
E-mail: [email p o ec ed]
ABSTRACT^
The a chi ec u e o he elemen a y P ocessing Elemen
-
PE- used in a ecen ly designed 128x128 Focal Plane
Analog P og ammable A ay P ocesso is p esen ed. The
PE a chi ec u e con ains he equi ed building blocks o
implemen bih ca ed da a low ision algo i hms based
on
he execu ion o
3
x
3
con olu ion masks. The ision chip
has been implemen ed in a s anda d 0.35ym CMOS
echnology. The main PE ela ed igu es a e:
180
cells/
mm2, 18 MOPS/cell, and 180 pW/cell.
1.
INTRODUCTION
Among all he possible de elopmen s o he sigh sense,
e olu ion selec ed hose indi iduals -and hei ision
sys ems-, in which he ea ly image p ocessing -in ol ing
calcula ions on a huge da a space- we e pe o med a he
senso y plane. In hese sys ems, a special pa o he b ain,
he e ina,
was mo ed o he sensing de ice,
he
eye,
educing he amoun o in o ma ion o be ansmi ed -and
p ocessed- o he b ain
[I].
Inspi ed by his e iciency, massi ely pa allel ocal
plane image p ocessing a chi ec u es ha e been p oposed
since he la e 80s [2].
In
hese sys ems, each ligh -sensing
de ice is su ounded by special ci cui y o ea ly image
p ocessing, cons i u ing a so-called
P ocessing Elemen
PE. The mode a e accu acy cons ain s, as well as he low
powe consump ion and high densi y o in eg a ion -PES
pe chip- equi emen s, has pushed he design o hese PES
o he analog side.
The op imum design o he PE is he c ucial issue in any
ype o massi ely pa allel p ocessing a chi ec u e. The
eason is qui e simple; hese sys ems consis o he spa ial
1.
This
wo k
has
been pa ially unded by
ONR-NICOP
Spanish-CICYT TIC1 999-0826
N68171-98-C-9004, EU-JST DJCTAM IST-1999-19007
and
eplica ion o a undamen al building block, he PE.
Hence, since he p ocessing pe o mances o he sys em
depend, di ec ly,
on
he numbe o p ocessing nodes -PES-,
he maximiza ion o he numbe o PES, is he majo
design objec i e2.
Un o una ely, no only he p ocessing capabili ies a e
di ec ly p opo ional
o
he numbe o PES. In p ac ice,
mos o he o al powe consump ion, as well as he inal
die a ea, a e also a di ec consequence o hose a he PE
le el. This ende s he design o he PE as he undamen al
p oblem o be aced. I
is
an i e a i e op imiza ion p ocess
in which e e y single mic ome e , and mic owa , coun s.
The e o e, addi ional design e o s o educe he powe
consump ion and a ea occupa ion, while keeping he
p ocessing pe o mances, commonly wo h i .
In wha ha ollows, we will desc ibe he a chi ec u e,
and main design echniques, used o implemen he PE in
he
so
called ACE16K chip
[3].
This is a 128
x
128 Focal
Plane Analog P og ammable A ay P ocesso -FPAPAP-
designed in a 5M-IP 0.35pm CMOS p ocess. Global
pe o mance igu es3 a e 0.33Te aOPS, 0.18 Te aOP/J,
3.8GOPS/mm2, while ad anced compe i o s [4],
[5]
p o ide 2.8 GOPS-9GOP/J-65MOP/mm2, and OSGOPS-
13GOP/J-O.
1
1
GOPS/mm2, hus posi ioning he ACE1 6K
in a op posi ion in his ield.
2.
ARCHITECTURAL CONSIDERATIONS
The i s s ep, in his op imiza ion p ocess, uns a he
a chi ec u al le el a he han a he ci cui o ansis o
ones.
The
iden i ica ion
o
he equi ed unc ional blocks
o low-le el image p ocessing applica ions, he design o
2. A
se ial compu a ion -pixel-wise- a chi ec u e, mus be
N-
imes as e
han
each
PE
-N=numbe
o
PES-
in o de o p o ide
he same F ame a e.
3.
Figu es e e o
8-b
accu acy ope a ions
0-7803-7448-7/02/$17.00 02002 IEEE 111
-
341
a p ope -simple, as , and accu a e- communica ion
scheme among blocks, and he supply o lexible enough
-high p og ammabili y and e sa ili y- ci cui and
sys em opologies, a e he guidelines o he selec ion o
he PE a chi ec u e.
P obably, he i s conside a ion e e s o he accu acy
equi emen s. Low-Le el image p ocessing asks can be
e icien ly ca ied ou by using 6-8b p ecision
calcula ions
151,
[6]. Hence, any a emp o u he
inc ease he accu acy o he di e en blocks in he PE
-
ei he by augmen ing he de ice’s a ea and hence
educing he misma ching le el,
o
by adding special
callib a ion schemes- does
no
commonly wo h i .
In addi ion o ha ,
PES
a chi ec u es mus be
designed as he modula agg ega ion o unc ional
blocks, ins ead o as a sea o analog ansis o s. Hence,
hose blocks mus be comple ely compa ible om he
I/
0
poin o iew, in o de o allow he low o in o ma ion
be ween hem. This ully-communica ed in e - unc ion
scheme, p o ides high algo i hmic capabili ies, due o
he la ge numbe o possible da a ans e ences and
ope a ions. On he o he hand, making he p ocessing
blocks easily p og ammable, inc eases he e sa ili y o
he sys em o easily -by ep og amming- i in o e y
di e en applica ions and en i onmen s.
Finally, selec ing which unc ional blocks mus be
included a he PE le el, is an open ques ion ha
depends on conce ns o di e en na u e. Mos o hese
conside a ions, e e o he en i onmen in which he
chip is o be used and
on
he in ended applica ion.
Howe e , due o bo h, he size o hese chips, and he
high ab ica ion cos s in modem echnologies -abou
80k
Eu o/cm2 o a digi al 5M-1P 0.25pm p ocess-, he
design
o
a
special pu pose ision chip is con ined o
hose cases in which he ma ke niche -and sales- is
ensu ed. O he wise, he PE a chi ec u e mus be lexible
enough o gua an ee he execu ion o di e en ision
algo i hms -also in di e en illumina ion condi ions.
Thus, i we conside ha mos ea ly ision p ocess
consis o he applica ion o con olu ions masks, and he
combina ion -ei he by boolean ope a ions, in he case
o
B/W
images,
o
by a local analog a i hme ic ope a o - o
hei esul s in a bi u ca ed low algo i hm, he ollowing
ope a o s should be included a he PE le el.
.
Mul iplie s and Adde s: Fo he con olu ion ope a-
ion.
Analog Regis e s:
To
allow o he s o age o a i-
ous image p ocessing esul s a he local le el.
A i hme ic Ope a o ando Bina y Ope a o ;
To
combine p e iously ob ained esul s.
Local Masks;
To
allow o he condi ional execu ion
o
ce ain ope a ions a he PE le el depending on
some locally de ined alue.
Op ical Inpu module; To pe mi he ligh sensing
capabili y, and, hence, o a oid he bo le-neck exis -
ing in da a ansmission om he senso y o he p o-
cessing plane.
F om neighbou s
I
1
Bina y
1
1,
kc;
,I I
A;z;s
1
Ope a o
Figu e
1.
Block Diag am
o
he PE
in
ACEl6K.
3. THE PE
IN
ACE16K
3.1.
Block
Diag am
Fig. 1 shows he block diag am o he PE in ACE16K.
A ows indica e how in o ma ion lows. I con ains
8
undamen al building blocks ha communica e o each
o he by means
o
he so-called
ACE-BUS.
Dah
ans e ences a e always ca ied ou in he same way;
some block - he da a sou ce- d i es he ACE-BUS while
ano he one - he da a des ina ion-, a he same imle
acqui es his in o ma ion om he ACE-BUS. Since hle
p ocessing is done in he analog domain, his bus is,
in
p ac ice, a single wi e, hus educing he amoun o a ea
and complexi y equi ed o he in e connec ion
as
compa ed o a possible digi al design o he PE.
3.2.
Mul iplie s
A bank
o
p og ammable analog mul iplie s
is
used o
implemen he neighbo hood ope a ions equi ed in low-
le el image p ocessing
[7].
I connec s he PE wi h i s
8
nea es neighbo s and wi h he PE i sel . Mul iplie s a e
designed using a one ansis o echnique
[8],
which, in
addi ion o he in ended p oduc ,
also
gene a es a signal
independen cu en -o se - ha mus be cancelled
a e wa ds. Bo h, pixel and scaling coe icien a iables,
a e codi ied in ol age o m, while mul iplie ’ ou pu is
p o ided as a cu en - hus acili a ing he compu a ion
o he equi ed addi ion o he con olu ion. Mul iplie s,
in
Fig.
2,
a e d i en
by
h ee di e en pixel alues,
P,
,
P,
and
Pc
in such a way ha he cu en which lows
o he p ocessing co e is exp essed as,
I,
=
A
PA
+
b.
P,
+
c
.
Pc
+
z
(1)
whe e he
A
and
PA
ma ices a e de ined
as4,
4.
Indexes
,
Z,
c,
,
b,
a e used
o
speci y he posi ion
o
he
neighbo igh , le , cen e, op,
bo om.
Hence, o ins ance,
he con ibu ion
o
he op-le neighbo is
a,/
.
PA.
111
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342
o nkighbo .
<$;Tp
F om
neighb. To
P ocessing
co e
Figu e
2.
Dis ibu ion
o
Mul iplie s
3.3.
Cu en P ocessing Block
The cu en s, gene a ed by he one ansis o
mul iplie s, a e collec ed by he inpu block o he PE -in
Fig.
3
-schema ic is displayed in Figu e
4.
Due o he
low ou pu impedance o he one- ansis o mul iplie s, a
i ual g ound -wi h he app op ia e ol age alue- mus
be p o ided -by a class
I1
cu en con eyo - o ha
pu pose. The non-desi ed o se con ibu ion gene a ed
by he mul iplie opology, is subs ac ed om he o al
inpu cu en , by using a high accu acy cu en memo y
block based on a s31 memo iza ion scheme. A e wa ds,
I,,,
can be ei he di ec ly s ee ed o he ACE-BUS o
sen o he inpu o a cu en compa a o , whose ou pu
can be also connec ed o he ACE-BUS. When he PE
is
ope a ed in g ey-scale mode5, he inpu cu en is
allowed o low in o any -use selec able- o he
capaci o s associa ed o he pixel. Depending on his
selec ion, di e en p ocessing pa adigms a e achie ed.
Thus, o ins ance, o un a Sobel ope a o , we would
de ine he ope a o in he
A
ma ix, he image o be
p ocessed would be loaded o he
PA
pixel, and we
woulduse
c
=
z
=
0,
and
b
=
-1
, o ob ain,
dpB
=
-PB+A*PA
(3)
whose s eady s a e solu ion is
P,
=
A
PA.
I he capaci o which is allowed o be upda ed is
CA
,
hen PES a e dynamically coupled, and we ge CNN-like
5.
When he compa a o is used, he same p ocessing
asks
a e a ailable. Howe e , in his case, only
B/W
a e p oduced.
Figu e
3.
Inpu block
o
he
PE
beha io
[9].
In addi ion, by allowing he cu en o low
in o
CA
and by de ining
acc
=
-1
and
a..
=
0,
he
s eady s a e solu ion is,
(4)
hus p o iding g ey-scale a i hme ic ope a ions.
3.4.
Analog Regis e s
The analog egis e s o es
8
g ey-scale pixel alues
wi h an equi alen esolu ion o
8-b.
Memo iza ion elies
on a bo om-pla e sampling echnique
[IO],
which a oids
he in oduc ion
o
signal dependen eed h ough e o .
Mo eo e , his echnique is no sensi i e o o se ol age
o he equi ed
opamp.
Hence, i is e y sui able o
spa ial uni o mi y issues.
3.5.
Op ical Module.
The op ical inpu module, consis s o a mul imode
senso in which bo h he physical de ice used as senso
and he ansduc ion mechanism a e p og ammable. A P-
di m-well diode, a N-welVP-subs diode, o a P-di m-
well/P-subs pho o ansis o , a e a ailable. Selec ion
is
done by using global p og amming ins uc ions.
Fu he mo e, he pho o ansduc ion scheme is also
p og ammable. Bo h linea in eg a ion o he
pho ogene a ed cu en , o loga i hmic comp ession
'J
PA
=
b.
PB+c.
PC+z
I I
Figu e
4.
Schema ic
o
he Image P ocessing Ke nel
I11
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343
sensing, a e also a ailable by p ope de ini ion o he
digi al ins uc ions con olling he chip ope a ion. This
allows o he chip o be used in e y di e en
illumina ion condi ions.
3.6.
Bina y Ope a o
A ully p og ammable 2-inpu I-ou pu bina y
ope a o has been also included. I allows o he
execu ion o any 2- a iables boolean unc ion. Ope ands
a e acqui ed om he ACE-BUS, while he logic
ope a ion o be pe o med is de ined by ou global
digi al ins uc ion signals -in u h- able o m.
3.7. Local masks
&
Add ess E en Blocks
Two masks, whose use is op ional - hey mus be
enabled by he use -, ha e been also inco po a ed o he
PE. The i s one, called
eeze
mask, is a ansien
enabling-disabling mask. When ac i e, i in e up s he
low o cu en om he inpu block o he ACE-BUS,
hence, hose PE’s in which he con en o he mask
-
which has been p e iously acqui ed om he ACE-BUS-
is
+I
emain unchanged. The second one, he
w i ing
mask, ope a es in a simila way. I disables he
possibili y o upda ing any analog egis e . The e o e, i
allows o selec i e upda ing o con en o he memo y.
The add ess e en ci cui y is an independen module
which allows o as downloading o spa se images. In
his case, he chip p o ides he add esses o hose pixels
in which ac i i y is de ec ed. Ac i e cells a e hose cells
ha ing a low-logic le el a he ACE-BUS when he
add ess e en downloading is s a ed.
3.8.
Resis i e Ne wo k
A esis i e g id, connec ing he
PE
o i s igh and op
neighbo has been included. I allows o he execu ion
o
con en ional low-pass di usion p ocess.
4.
Rele an Da a
Fig.
5
displays he layou and
loo
planing o he
PE
in he ACE16K chip, con aining 198 ansis o s. PE size
is 75.5
x
73.7 pm2
-
180 cells/mm
.
Maximum powe
consump ion o he cell is 180p.W. Time cons an o
linea con olu ions is 160ns, yielding peek
pe o mances o abou
18
MOPS
pe cell
-9
p oduc s
and
8
addi ions pe o med in 960 ns -six ime cons an
uni s.
Finally, Fig. 6 shows, as an example, he execu ion o
he Sobel ope a o on he amous Lena’s pic u e. Image
loading and downloading equi es 130ps each, while
o al p ocessing ime is only
3ps
-including in emal sel -
callib a ion p ocesses-.
2
Figu e
5.
Layou and Floo planing o he PE
5.
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Figu e
6.
Example o Image P ocessing wi h ACE16K
111
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