Imp o ing he Design P ocess o VLSI Ci cui s by Means o a Ha dwa e Debugging
Sys em: UNSHADES-1 F amewo k
M.A. Agui e, J. Tombs, A. To alba and L.G. F anquelo
Escuela Supe io de Ingenie os. Uni e sidad de Se illa
A da. Camino de los Descub imien os s/n,
4109 Se illa (SPAIN)
[email p o ec ed], jo[email p o ec ed],, [email p o ec ed], leo[email p o ec ed]
Abs ac – Due o he inc ease in size and complexi y o VLSI
in eg a ed ci cui s, new design ools a e becoming needed.
Telecommunica ions and Elec onic Indus y demand designs
ha in eg a e in ensi e digi al signal p ocessing blocks and
complex con ol asks. Rapid P o o yping echniques in oduce
a new s age in o he design low ha o e come he d awbacks o
simula ion s age and sho en design imes. Ad anced FPGAs
can hos he design o i s emula ion and can un inse ed in o
he inal sys em. The bene i s o hei use go beyond he simple
apid p o o yping app oach, and a e able o p o ide addi ional
in o ma ion and o he use ul asks ha will be p esen ed in his
pape .
I. INTRODUCTION
Due o he inc easing complexi y o many elec onic
p ojec s, he design low o VLSI in eg a ed ci cui s has o be
comple ed [1] wi h he use o some p o o yping o emula ion
echniques. Figu e 1 show he comple e design low
including he p o o ype phase. The adi ional simula ion
s age isn’ enough, because s imuli gene a ion does no
always ep esen s all he un- ime si ua ions and, in mos o
cases, i ’s almos impossible o gene a e enough da a o
ac i a e all cases in he deepes design blocks inside he
design hie a chy ee. S imuli a e usually gene a ed using
well con olled models o he sys em. Howe e , i he
p o o ype is essayed using he physical elemen s o he inal
sys em, non con olled (in e ms o modelling) si ua ions can
be in oduced aking in o accoun he eal ex e nal
componen s. A he same ime in e nal scope echniques ha e
o be in oduced o ob ain in o ma ion abou wha is ac ually
happening inside he sys em.
The p o o ype is ypically suppo ed by means o an
ad anced SRAM-FPGA [4] hese can no mally wo k a high
clock equencies. The main ad an ages o using FPGAs o
his pu pose a e basically: Fi s , he e’s an unlimi ed numbe
o con igu a ion cycles, ha allows he e i ica ion o
mul iple e sions o he ci cui ne lis , and second he
emula ed e sion can be p oduced wi h ex a ci cui y and
pins o p o iding ex a execu ion- ime in o ma ion.
Ad anced FPGA’s a e SRAM based p og ammable
ci cui s ha can hos la ge digi al ci cui s wi h a easonable
de ice beha iou . These de ices a e ypically buil wi h o he
ea u es e y use ul o building he p o o yping sys em
i sel , such as many elec ical iopin s anda ds, JTAG po s,
clock skew compensa ion, gene al pu pose mul iplie s, on-
chip memo y blocks… e c.
The concep o a Ha dwa e Debugge [6-7] is mo e ample
han a simple p o o yping sys em . Using an ad anced FPGA,
i no only can emula e he inal ci cui bu i can p o ide
in o ma ion abou how he ci cui is wo king du ing
execu ion, and e en ually p o ide mo e con ol on he
unning de ice ha can be exploi ed o a be e analysis.
Basically he added capabili ies a e: cycle by cycle s epping
o he en i e ci cui , ex ac un- ime in o ma ion o in e nal
scope, and, e en ually, p oduce modi ica ions in he in e nal
egis e s.
HIGH LEVEL
DESCRIPTION
HIGH LEVEL
SIMULATION
SYNTHESISTECHNOLOGY
PLACEMENT, ROUTING
AND SHIPMENT
SYNTHESIS
ADD DEBUG CIRCUIT
FPGA TECHNOLOGY
PHYSICAL COMPILER
FOR EMULATOR
SYSTEM WITH EMULATOR MAN-MACHINE INTERFACE
CONFIGURATION MAP INTERNAL REGISTER
Fig 1. Modi ied VLSI Design Flow
Mos FPGA ound ies o e debugging packages ha
suppo eco ding in e nal signals in o a syn hesised
memo y, like an in e nal logic analyse . These p oduc s a e
Chipscope om Xilinx [9-10] and SignalTap om ALTERA.
Basically hey consis o a ci cui o he un- ime condi ion
de ec ion ha igge s he signal cap u e p ocess. Some
memo y esou ces a e ese ed o eco ding he p eselec ed
signals. All o hese esou ces ha ha e o be included in he
same ci cui ne lis . The size and beha iou o he placed and
ou ed ci cui depends s ongly o how many signals and
clock cycles a e going o be o be eco ded and he p esence
o hose elemen s s ongly a ec s o he beha iou o he
emula ed ci cui . The ex a size and he modi ied
pe o mance o he ci cui is called he o e head o he
debugging sys em.
This pape p esen s UNSHADES-1, a di e en app oach
based on VIRTEX FPGAs whe e some special ea u es ha
a e exclusi e o his FPGA a e exploi ed o cons uc ing a
ha dwa e debugge sys em. UNSHADES-1 means
UNi e si y o Se illa HA dwa e Debugging Sys em and is
based on he pla o m HADES-1 [2,5]. The comple e
sys em, so wa e and ha dwa e a e inse ed in o he Xilinx
s anda d design packages, Founda ion and Alliance. This
pape is o ganised as ollows: Sec ion II shows an o e iew
o he VIRTEX p ope ies ha a e use ul o UNSHADES
sys em. Sec ion III desc ibes how o execu e he s ep by s ep
sys em. In sec ion IV a wo wi es sys em o con olling he
debugge is p esen ed and Sec ion V y VI b ie ly p esen
some ideas abou he so wa e and inally sec ion VII will
show he conclusions.
II. HARDWARE DEBUGGING SYSTEM
UNSHADES-1 is a sys em independen ha dwa e
debugge whe e he designed ci cui is subs i u ed in he inal
sys em by one ad anced FPGA, a de ice aken om
VIRTEX se ies om Xilinx. A compu e suppo s he
in e ace man-machine. UNSHADES boa d [5] is basically a
sma link be ween he FPGA and he compu e , whe e i can
download he con igu a ion o he FPGA and can ead and
w i e pa ial in o ma ion o ha con igu a ion. This ea u es
play an impo an ole in ou sys em because i means ha
FPGA can be explo ed and manipula ed in o de o ob ain
inne iew and con ol o he de ice du ing execu ion.
VIRTEX FPGAs [7] o m a amily o de ices om Xilinx
ha suppo la ge amoun o sys em ga es wi h high le el
ci cui pe o mance. The nex pa ag aphs will highligh he
mos in e es ing ea u es o hese FPGAs o ou pu pose.
Using he Selec Map po Vi ex can be easily, con igu ed,
ead and w i en, o ally o pa ially. The in o ma ion can be
mo ed as 8-bi s wide da a a a high speed (un il 60Mb/s)
du ing he pa ial eading and w i ing. This allows as
selec ing o he in o ma ion o ead o modi y.
Secondly, he e’s a single-clock cycle p ocess o sa ing
he in e nal s a e ( he con en s o he all he Flip- lops) o
ex e nal eading: he CAPTURE_VIRTEX mac o. A e he
execu ion o he mac o he sa ed s a e can be uploaded o he
hos and he in o ma ion abou he ac ual egis e con en s
can be linked wi h hei designe ’s names, gi en du ing
design ime hus making he eco ded in o ma ion
comp ehensi e o he use . The s a e in o ma ion is copied o
special dedica ed memo y cells ha a e no included in he
common esou ces o he FPGA and his p ocess doesn’
con ibu es o he o e head o he UNSHADES-1 sys em.
Finally, all he Vi ex lip- lops ha e a clock enable inpu
o enabling synch onous changes. This inpu can be sa ely
manipula ed o con ol he execu ion o he design ins ead o
using signals ha con ol on he clock wi es hemsel es.
III. STEP BY STEP EXECUTION
S opping a sys em clock is no easy in la ge FPGAs,
because clocks a e compensa ed using phase compensa ion
echniques ha need se e al clock cycles o be se led and
canno be esumed. Be o e he sys em s ops, a debug
condi ion has o be eached, his is done wi h a p e-
p og ammed condi ion ha wa ches he unning sys em.
When he condi ion is sa is ied he sys em eezes he ci cui .
Ins ead o s opping he sys em clock he Clock Enable inpu
o all he lip- lops can be used o eeze he ci cui . In his
case, he ci cui can be ozen pa ially. We ha e used his
inpu o ob aining a ull con ol o he execu ion p ocess,
ee o gli ches.
Wi h an ex a ex e nal inpu , a simple s a e machine can
con ol he clock enable inpu o he lip- lops. A e e y
ising edge o his signal a ini e s a e machine enables he
sys em a single clock cycle and ac i a e he CAPTURE
mac o. A e his, he hos can upload he new in o ma ion.
Fo in oducing a s ep-by-s ep execu ion mechanism in o
he design ne lis he ollowing s eps ha e o be pe o med:
1. A ach he line
eeze o all lip- lops ha a e going o
be ozen. This can be done in oducing he lowing
code in o he high le el desc ip ion code ( o example,
in VHDL) [9].
i (clk’e en ) and clk=’1’) hen
i ( eeze=’1’) hen
.....................
end i ;
end i ;
2. This line will be con olled by a s a e machine ha de-
asse s i when he eeze condi ion is aken and
p oduces he CAPTURE_VIRTEX p ocedu e.
3. The PC uploads he in o ma ion con aining he ci cui
s a e.
4. Using an ex e nal line he PC ac i a es he ci cui o a
single clock cycle. The nex clock cycle a new
CAPTURE_VIRTEX p ocedu e is ac i a ed.
5. Again he PC uploads he in o ma ion.
S eps 4 and 5 can be epea ed as many imes as desi ed,
and, a e e y s ep he egis e con en s can be eco ded in a
ile wi h a alid o ma sui able o being displayed in a
wa e o m iewe .
Figu e 2 depic s an block scheme o how he desc ibed
sys em wo ks whe e CAPTURE_VIRTEX mac o is ac i a ed
when he clock enable is deasse ed.
FINITE STATE MACHINE
ACTIVATES A SINGLE
CLOCK PULSE
CLOCK
ENABLE
EXECUTION TIME
STOP CONDITION
EXTERNAL PAD
DQ
CLK
CAPTURE_VIRTEX
CLK
Fig 2. S ep by s ep machine
The numbe o consumed esou ces o his ci cui is
negligible, less han one hund ed sys em ga es and i can be
shown ha he e’s no e ec on he ci cui beha iou , because
he un- ime condi ion o ac i a ing he cap u e sys em is a
simple compa a o .
The pullup esis o p o ides a bi-di ec ional cha ac e o
he ex e nal pad. I indica es ha he ci cui is unning when
low, bu a e he condi ion, i goes o esis i e high eady o
managemen by he s ep by s ep sys em.
IV. TWO WIRES METHOD
This sec ion will explain how he UNSHADES-1 emula o
in o ms o he con ol compu e abou he de ec ion o a
pa icula e en . We ha e in oduced a wo wi es me hod.
Thus, ou debugge will ha e an o e head o wo pin o i s
own con ol. These wo lines a e:
• E en line: This line is sha ed wi h he ex e nal pin
used in he s ep by s ep me hod. I is an open
collec o line (as explained be o e). When he
ci cui is wo king, his line is deasse ed. All he
p og ammed e en s a e o -ed o his line. When
any e en is asse ed hen a e a eadback p ocess
he e en can be iden i ied.
• Resume line: This line will eac i a e he ci cui
a e an e en has been de ec ed, o e ase he un-
ime e en .
Figu e 3 shows a scheme o how he sys em is buil . I can be
seen ha bo h sys ems s ep by s ep and wo-wi es con olle
sha e he E en Line, due o he h ee s a e cha ac e .
A e an e en he emula o has o ge he necessa y
in o ma ion o he use . The me hod is associa ed o he
Xilinx mac o CAPTURE_VIRTEX, whe e he ci cui s a e is
copied in one clock cycle o an special con igu a ion
memo y. A e his igge he sys em can be s opped (and
s ay ozen) o con inue wo king. In he i s case he
debugging p ocess loses he synch oniza ion wi h he
ex e nal sys em bu no clock cycles a e los and in he second
he emula ion gi es he in o ma ion o a single snapsho o
he sys em.
No e ha he debugging condi ion is no es ic ed o a
single condi ion. The use can ix a p io i as many condi ions
as desi ed. Main ad an age o his me hod is ha he ac ual
debug condi ion ha igge s he sys em is iden i ied in he
same way as he in e nal egis e s and signals.
V. INSERTION OF THE DUBUGGING CIRCUIT
Debug ci cui can be au oma ically inse ed in o he
emula o wi hou being esyn hesized. The designe akes
decisions abou which wi es o egis e s ha e o be wa ched
o de ine he igge condi ion o he i s snapsho . No e ha
due o he pu e pa allel na u e o ha dwa e all condi ions a e
wa ched simul aneously. One compa a o has o be inse ed
pe e en . This ex a ci cui can be inse ed o he high le el
code, bu some design ime can be imp o ed i he ci cui is
inse ed o he s uc u al ne lis (VHDL, EDIF,...) a he
p e ious s age o physical implemen a ion. The main
ad an age is ha he designe debugs he inal ne lis , and
doesn’ ha e o e-syn hesise he comple e design, which is
mo e o less 40% o he o al syn hesis ime. This ask can be
done au oma ically using a ool ha is being de eloped in ou
depa men .
VI. UNSHADES SOFTWARE
The Man-machine in e ace is an essen ial pa o a
ha dwa e debugge . In he same way ha in o ma ion is
p esen ed, pe o mance supe io o he comple e sys em is
ob ained as he sys em can be inspec ed and manipula ed. In
his way he sys em has o be as and e ec i e. We ake
ad an age wi h he pa ial econ igu a ion echniques o
VIRTEX de ice. The econ igu a ion ime is hen e y as
because only a small pa o he FPGA has o be inspec ed o
con igu ed. Fo example, a ame ( he minimum amoun o
in o ma ion ans e ed) o VIRTEX 50 can be inspec ed in
less han 10 mic oseconds.
In o de o display s ep-by-s ep in o ma ion, a s anda d
o ma ( cd) da abase is p oduced and a wa e o m iewe
displays he e olu ion o he emula ed ci cui .
Mo eo e , i we ha e he sys em in a ozen s a e some
manipula ions can be p oduced in he s a e, allowing he
modi ica ion o he alues o he lip- lop con en s. This
no el idea is also being de eloped in he new so wa e ool.
EVENT LINE
RESUME LINE
CONDITION 1 CONDITION nCONDITION 2
DET 1 DET 2 DET n
EDGE DETECTOR
Fig 3. Two wi es con ol sys em
VI. CONCLUSIONS
The idea o debugging digi al ci cui s in un- ime is
a ac i e. Due o he imp o emen s o he FPGA’s he
ci cui can be emula ed and inse ed in o he inal sys em
p e iously o being sen o he ound y. FPGA’s p o ide
mo e ea u es han expec ed and can be ins umen ed o he
design p ocess. In ou Depa men we ha e de eloped
UNSHADES-1, a new ool o debug digi al ci cui s. Wi h
he inse ion o an ex a logic he ci cui can be emula ed in a
con olled way wi hou being a ec ed o he con ol ci cui
i sel . UNSHADES sys em p esen an al e na i e non
exclusi e o he comme cial debugging sys ems.
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