CNNA-94
Thi d
IEEE
In e na ional Wo kshop
on
Cdlula
Neu al Ne4wodcs
and hei Applica ions
Rome,
I aly,
Decembe
1821,1994
Fig. 1 shows he concep ual
block diag am o he implcmcn a-
ion desc ibed
in
his
pape . The sys-
em
has
he same undamen al
capabili ies
as
he o iginal e sion
p oposed by
Roska
and Chua [I],
along wi h he possibili y
o
op ical
ini ializa ion.
Du ing he sys em design p o-
cess,
anen ion
was
dedica ed
A
CNN
Uni ed
Chip
in
CMOS
Technology
PROORAM-
c”
APR
+
MABLE
Figu e
1
-
Schema ic cell a chi eclu c
o
(I
CNN
Uni e sal
Chip.
R.
Dominguez-Cas o,
S.
Espejo,
A.
Rod iguez-VaZqucz,
and
R.
Ca m~na
Cen o Nacional
de
Mic oelec 6nica-Uni e sidad
de
Se illa
Edi icio
CICA,
Wda dn, 41012-Se illa,
SPAIN
Phone: 34
-
5
-
423
99
23.
Fax:
34
-
5
-
462
45
06.
E-mail:
[email p o ec ed]
Absl ac
-
This pape desc ibes he
design
o
a CNN uni e sal chip in a s andani CMOS ech-
nology. The co e
o
he chip consis s
o
an
away
o
32
x
32
conple ely pmg ammabk CNN cells.
Inpu image can be
loaded
in
op ical
o
ciec ical
o m.
Accu acy
is
in
he
ange
o
7-8
bi ,
and
cell densi y is
o
33
cel1s/mm2.
1.
In oduc ion
CNN Uni e sal
Chips
a e he
main
componen s
o
CNN Uni e sal
Machines
[
11. Thei
uni e sali y [2], oge he wi h
hei
abili y o implemen any CNN applica ion, makes hei elec-
onic implemen a ion ex emely an ac i c.
he o iginal
CNN
model has
been
uscd-[3].
This-model has p ope ies which
a e
e y simila o
hose
o
he o iginal one, esul s
in
highe
a ea
and powe e iciency. and is
mo e
ole an
o
p o-
cess pa ame e a ia ions.
I
can
be
desc ibed
by
he
ollowing equa ion,
whe e he
sum
ex ends o he neighbo hood
o
cell
c,
and e e y symbol
is
used wi h i s adi-
ional meaning [3] excep o he e m
Ex,,
which he e ep esen s a p og ammable (by ac o
kc)
o se e m.
2.
A
syne gy
o
analog
and
digi al
p og”b1li y
A
hyb id
s a egy
which combiaes
he
ad an ages
o
analog
and
digi al p og ammabili y
[4] has been used o con ol he p og ammed alues o CNN coe icien s.
This
app oach is based
0-7803-2070-OB4/$4.00
6
1994
IEEE
91
on a combined use o analog-p og ammable mul iplie s wi hin he
cells
and o digi al con ol
signals
om
he ou side
o
he cell a ay. Clea ly, some in e ace ci cui y is needed o gene a e
he
in e nal analog weigh -signals om hei digi ally coded alues. Due o he la ge numbe
o
mul iplie s in he ne wo k, e en small educ ions in mul iplie -a ea jus i y he a ea dedica ed o
he in e ace ci cui y.
In
ou case, he cell-a ea
is
subs an ially educed, hus sys em-a ea educ-
ion is ex emely high.
The in e ace ci cui y consis s
o
se e al iden ical blocks, one
o
each p og ammable
pa ame e in he ne wo k. The unc ionali y
o
each
in e ace blocks is ha o a nonlinea
D/A
con e e , and i s implemen a ion ollows he adap i e a chi ec u e shown
in
Fig.
2,
in
which
he analog weigh signal adap s i s alue un il he scaling ac o o he analog- and digi ally-con-
-
-
RAM
memo y.
olled mul iplie s coincide [4].
This
app oach me ges mos
o
he
ad an ages o digi ally- and analog-p o-
g ammed mul iplie s, achie ing low a eas and
a educed numbe o con ol lines, simpli ying
he con ol o he weigh alues, and elimina -
ing hei sensi i i y o global p ocess pa axbe-
e a ia ions.
In
addi ion, i allows he
ealiza ion o he
APR
111 using a digi al equi ed o
he
hyb id-con ol
app oach.
.
Adap i e
s age+Cell
a ay
Figu e
2
-
A chi e um
o
he
D/A
in e ace ci cui m
92
by wo analog bu e s wi h e y low ou pu impedance, whose ou pu
a e
also
he weigh sig-
nals ansmi ed o e e y cell in he sys em. Du ing a p ecalib a ion s ep, con olled by
+op
hese bu e s
a e
disconnec ed om he mul iplie , and he di e en ial weigh signals a e
sho ed a he inpu o he mul iplie .
This
has he e ec o se ing he common mode ol age
V,,
o he ol age
VL
a he inpu
o
he low impedance loading s ages. The e o cu en low-
ing ou o he p-channel cu en
mi o
is
s o ed
in he p-channel ansis o s wi h ga es d i en
by swi ches con olled by
+op
which cons i u e he analog memo ies.
A e
his
calib a ion
s ep, he ou pu o he cmn memo ies
ace
added o
he
di e ence o he ou pu signals o he
analog mul iplie and he DIA con e e , and
he
esul ing cu en is in eg a ed
a
he inpu
nodes o he analog bu e s. The ou pu o
hese
bu e s con ol he weigh signals o he mul i-
plie , hus closing a eedback loop which
se les
a e he analog weigh signals ha e he co -
ec , adap ed alue. The sign o he p opmmed weigh is in oduced by swapping he
connec ions o he inpu and ou pu nodes o he bu e s, wi h espec
o
he adap i e co e o
he ci cui y. The signals d i ing he cells do no ha e any swi ch
in
hei
pa h,
in o de o a oid
ou pu impedance deg ada ion.
The
D/A con e e is implemen ed by a bina y weigh ed
a ay
o n-channel ansis o s in sa u a ion.
A
inal impo an issue is he powe dissipa ion o he bu e s, which is ex emely high.
The amoun o cu en equi ed om he ou pu o one bu e depends on he alue o he p o-
g ammed weigh .
Fo
his
eason, he
bu e s
include a weigh -dependen bias cu en , con-
olled by he mos signi ica i e bi s o
he
digi al wo d encoding
he
weigh alue.
3.
E o
Sou ces
and
E alua ion
C i e ia
The design o a ea-e icien analog in eg a ed ci cui s equi es a ca e ul analysis di ec ed
owa ds he iden i ica ion, cha ac e iza ion, and educ ion
o
all possible e o s a ising in he
p ac ical ealiza ion.
A
i s subdi ision
o
hese e o s can
be
in o dynamic and s a ic non-ide-
ali ies.
In
addi ion, e o s can
be
classi ied
as
de e minis ic and andom. De e minis ic e o s
a e o igina ed by any non ideali y de i ed om he ci cui implemen a ion assuming ha iden-
ically designed de ices a e ac ually iden ical, while andom e o s a e o igina ed by misma ch
e ec s.
Misma ch e o s a e s ongly dependen on
he
a ea o he de ices, which is o ex eme
ele ance in
ou
applica ion. Misma ch
e o s
a e
he dominan e o sou ce whene e low a ea
de ices a e used, and o CNN implemen a ions, hese e o s a e
specially
ele an on he mul-
iplie s.
3.l.Misma ch
e o s
on
he mul iplie s
We assume ha e e y mul iplie
has
a weigh de ia ion and
an
ou pu o se . Tha is, while
he ideal cha ac e is ic o he mul iplie wi h a gene ic weigh
p
is,
xo
=
pxi,
in p ac ice we ha e
x0
=
(p+6p)x,+SxO ,
whe ebo h6p(weigb e o )andGx,~(o se e o )
a es ochas ic a i-
ables, assumed s a is ically independen , wi h
ze o
mean. Using
his
model
o
all he mul ipli-
e s
in
Eq.
1,
and conside ing he cell
o
be
in i s linea egion, we ha e,
T-
d ew
=
{
=>‘(I)
+
b:Ud)
+
kcXSa
+
(2)
whe e he
i s
line o he equa ion con ains he nominal e ms, and
he
second he e o
e ms.
The igh -hand side o equa ion
Eq.
2
cons i u es he in eg and
F( )
o
he
in eg al equa-
ion go e ning e e y cell
(sec
J2q.
l).
Assuming ha he s a e a iables and he inpu alues
a e
d
+
2
{
SO>d( )
+
shy}
+
c
{
6*&
+
S&}
+
6kCxa
+qa
93
limi ed
o
he same in e al
[-x,,
xsa ],
he
maximum nominal alue o
( )
is gi en, a any
ime
ins an by,
I
o
e e y mul iplie , he
ela i e weigh e m
and he
ela i e
o se
e o
a e
bounded by
max{ ( ))
=xsaI'
~{laj+Ib~l+lkll
(3)
hen, he e o
o
in eg and
( )
ela i e o
i s
maximum alue is bounded by
E,
i,q
=
5kc.xa+5x~
+
{S.~d( )+66;ud+6x+6u~}l
s
IC
I
dc
N(c)
A e a de ailed analysis o a
la ge
numbe
o
mul iplie s
[5],
a mul iplie based on ou
MOS
ansis o s ope a ing in
he
iode
egion (Fig.
4b)
was selec ed.
This
mul iplie exhibi s
low misma ch e o s and a wide ange
o
linea i y. In addi ion, i s pa asi ic dynamic beha io is
negligible.
I
Figu e
4
-
a) Schema ic
o
he analog co e
o
he
cell.
b)
Mul iplie
4.
Gene al cha ac e is ics
and
unc iodi y
The ex e nal managemen
o
he chip is comple ely digi al. Analog weigh s a e speci ied
and in e nally s o ed in digi al o m.
Fo
each empla e alue, an adap i e s age ans o ms he
digi al code in o an analog ol age, which is hen ansmi ed o he ne wo k.
This
me hodol-
ogy esul s
in
weigh insensi i i y o p ocess-pa ame e a ia ions.
as
well
as
on accu a e ex e -
nal con ol.
E e y cell inco po a es a pho osensi i e de ice, which allows he sys em o
be
op ically
ini ialized. Elec ical ini ializa ion is
also
possible, while ou pu image is always downloaded
in elec ical
o m.
Inpu and ou pu images
a e
assumed
o
be
bina y
in
e e y
case.
Elec ical image uploading and downloading is ealized h ough
32
YO
bonding pads, on
a ow by ow basis.
The digi al ci cui y a each cell includes a ou -bi s a ic memo y
(LLM),
a comple ely
p og ammable wo-inpu digi al ga e
(LLU),
and ini ializa ion and con ol ci cui y
(LCCU)
o
many di e en ope a ions. Memo y con en s can
be
mo ed om one loca ion o ano he .
The ou -bi memo y a each cell allows he ne wo k o s o e ou comple e images. Two addi-
ional " ead-only-memo ies" wi h ixed
+1
and
-1
alues a e also a ailable. Any memo y can
be
used
as
inpu
U
o
as
ini ial condi ions
X(0)
o
he
ne wo k.
94
Da a- ans e ence p ocesses ( o o om he ex e io o he chip, he CNN, he pho osen-
son,
o he
LLU)
a e cen alized on he
LLM,
as
shown in Fig.
1.
Mic oins uc ions ( empla es, o se
e ms
and local logic ope a ions) a e digi ally s o ed
in an on-chip s a ic
RAM
memo y, which implemen s he analog
and
logic p og am egis e s
(APR
and
LPR)
and
has
a capaci y o
8
ins uc ions. The in o ma ion con ained
in
each o
hese
ins uc ions
is
desc ibed in Tab. 1. A e
an
ins uc ion se
has
been
loaded
in o he digi al mem-
o y, he indi idual
CNN
and logic ope a ions
can
be
used
any numbe o imes in
any
o de .
Minimum
allowed inc emen o
he
analog
pa ame e s
is
smalle
han
he expec ed s anda d
de ia ion in he weigh o
he
mul iplie s
dw
o misma ch e ec s. The e o e, coe icien disc e -
iza ion does
no
ha e a signi ican e ec on he
Linal
p ecision.
The
allowed ange o
he
coe -
icien s can
be
scaled (a
he
expense
o
simila change in
he
ime cons an o he ne wo k) by
an
a bi a y alue
W,-.
This is a consequence o using
he
FSR
model
[3].
Da a
desc ip ion
Feedback coe icien s
Numbe
o
Bi s
pe
AllOW d
Minimum
coe icien s coe icien
ValUCS
inc emen
4
9
8
[-W,,,,.
Wm,l
W,,,,/128
Con ol coe icien s
O se e m
Bounda ycells
s a e a iable
Bouada ycells inpu alue
LLU
u h
able
95
-
9
8
I-W,,,,,
Wm,l Wm,/128
d
1
8
[-Wm,.
W,,I Wm,/128
xs
1
2
{-LO,
11
us
1
2
{-LO,
11
'IT
1
4
bY
G
________
---_-_--

Bias and uning s ages, which gene a e he analog e e ence ol ages equi ed o he
analog co e
o
he cells, a e loca ed a e e y come o he chip a ea, and connec ed among
hem. A digi al decode , placed a he le side o he cell a ay, is used
o
gene a e he 32 con-
ol
signals
equi ed o he
ow
by
ow
U0
p o ocol. The
32
YO
cells loca ed a he op o he
chip include inpu and ou pu digi al bu e s, as well
as
he ci cui y equi ed o mul iplex he
inpu
and
ou pu
signals h ough he
same
32 lines. The ci cui y loca ed a he bo om o he
ceIl a ay can
be
di ided
in o
wo la ge sec ions. The
i s ,
loca ed below, is he SRAM block
implemen ing he APR and LPR, which con ains 8 wo ds ( o
8
mic oins uc ions) o 160 bi s.
The second, loca ed abo e, con ains 10 adap i e s ages (nine weigh s plus he o se e m).
Finally, he blocks
on
he igh side a e used o gene a e some con ol signals and o miscella-
neous pu poses.
Fig. 5b shows he layou o one cell. The size o he cell is 180 x 170
pn2,
and he size o
he comple e chip
is
7,7
x
6,8
mm2.
The design has been sen o ab ica ion in
a
s anda d lpm
CMOS echnology, and is due om he ound y in he ollowing weeks. Tes esul s a e
expec ed
o
be a ailable
o
p esen a ion
a
he ime o he con e ence.
I
Figu e
5
-
a)
Schema ic
o
he comple e chip
b)
Layou
o
one cell
o
he
FSR
CNN
uni e sal
chip
Re e ences
[
11
T. Roska
and
L.O.
Chua: “The CNN Uni e sal Machine: An Analogic A ay Compu e ”,
IEEE T ansac ions
on
Ci cui s and Sys ems-11: Analog
and
Digi al Signal P ocessing,
[2]
L.O.
Chua, T. Roska and P.L. Vene iane : “The CNN
is
Uni e sal
as
he Tu ing Machine“.
IEEE T ans. Ci cui s and Sys ems
I:
Fundamen al
Theo y
and Applica ions,
Vol.
40,
pp
[3]
S.
Espejo.
R.
Dom’nguez-Cas o, A. Rod iguez-Vizquez and
R.
Ca mona: “Con e gence
and S abili y
o
he FSR
CNN
Model”.
In
his p oceeding.
[4]
S.
Espejo,
R.
Dom’nguez-Casuo, A. Rod iguez-Vbquez and R. Ca mona: “Weigh -Con-
ol
S a egy o P og ammable Ch I Chips”.
Ln
his p oceeding.
[5]
S.
Espejo:
“VU1
Design and Modeling
o
CNNs”
Ph. Disse a ion, Uni e si y
o
Se illa,
Ma ch 1994.
Vol.,
40,
NO.-3,
Ma ch 1993.
289-29
1,
Ap il 1993.
96