A Class of Differentiator-Based Multifunction Biquad Filters Using OTRAs

THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 18 |NUMBER: 1 |2020 |MARCH A Class of Differentiator-Based Multifunction Biquad Filters Using OTRAs Neeta PANDEY1, Rajeshwari PANDEY1, Rashika ANURAG2, Ritu VIJAY3 1Department of Electronics and Communication Engineering, Delhi Technological University, Main Bawana Road, 110042 Delhi, India 2Department of Electronics and Communication Engineering, JSS Academy of Technical Education Noida, C Block, Phase 2, Industrial Area, Sector 62, 201301 Noida, India 3Department of Electronics, Banasthali University, Vanasthali Road, 304022 Banasthali, India [email protected], rajeshw[email protected], raashik[email protected], [email protected] DOI: 10.15598/aeee.v18i1.3363 Abstract. This paper presents Signal Flow Graph (SFG) approach-based realization of Single Input Multiple Output (SIMO) filter topologies. A differentiator is placed as basic building block. A total of sixteen variants are derived from the proposed differentiatorbased SFG. The Operational Trans-Resistance Amplifier (OTRA), an active block having low parasitics at input terminals, is used to validate the proposed methodology. All the derived filter structures use three OTRAs, six resistors and two capacitors. The filter performance parameters can be adjusted independently. The functional verification of the proposed method is done via SPICE simulations using 0.18 µm CMOS technology parameters from MOSIS. Keywords Filter, OTRA, SIMO. 1. Introduction The Continuous-Time (CT) filters are widely used in consumer electronics, instrumentation, military ordnance, telecommunications and radar systems, etc. Therefore, considerable research efforts have been devoted to developing CT filters based on wide variety of active blocks. The bandwidth of traditional active blocks is limited by closed-loop voltage gain and presence of the parasitic elements influences the performance of filter. The active block, OTRA [1], uses current feedback technique, which makes its bandwidth almost independent of the gain. Additionally, the parasitic impedances at input terminals are low and have negligible effect on circuits. Therefore, OTRA-based CT filters have been investigated in recent past [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18] and [19] and they can be categorized as (i) single and (ii) multiple OTRA-based structures. Though single OTRA-based filters [2], [3], [4] and [5] are useful when power consumption is important, they show larger sensitivity to component variation and are less versatile than their multiple OTRA-based counterparts [1], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18] and [19]. The salient features of the available multiple OTRA-based CT filters are listed below: •A single response is available in [1], [6], [7], [8], [10], [16] and [17], whereas [8], [9], [11], [12], [13], [14] and [15] offer multiple responses. •Single/Multiple output filters [6], [7], [8] and [16] may, however, give other responses by choosing appropriate input excitation terminal. •Filters [1], [8], [10], [16] and [18] impose condition on component/switch selection for obtaining the responses. The underlying principle of these filters [1], [6], [10], [11], [12], [13], [14] and [16] is connection of lossy and lossless integrator. In the recent past, the researchers have developed few differentiator-based signal processing and generating circuits [7], [8], [9], [15], [20], [21], [22], [23], [24], [25], [26], [27] and [28] finding applications in the area of control system and biomedical instrumentation. However, the area is not much explored, as evident from the limited literature available. Considering this, differentiator-based SIMO filter topologies designed using SFG-based approach are proposed in this paper and OTRA is used to validate it. c 2020 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 31 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 18 |NUMBER: 1 |2020 |MARCH It is pertinent to mention here that SFG-based approach, with integrators, has been employed in [29], [30], [31], [32] and [33]. The paper is arranged in five sections. Section 2. includes the discussion on the proposed SFG, followed by a brief review of OTRA and basic signal processing blocks designed using OTRA. The OTRA-based SIMO filter topologies are also included in the same section subsequently. The non-ideality analysis is given in Sec. 3. , followed by simulation results in Sec. 4. The paper is finally concluded in Sec. 5. 2. Circuit Description 2.1. The Proposed SFG The proposed differentiator-based SFG, which uses two differentiators in forward path, is depicted in Fig. 1. The coefficients ki(i∈ {1,2,3,4}) may assume value 1and −1. Four different SFGs can be generated from Fig. 1 by selecting the values of k1and k2respectively as (1,1),(1,−1),(−1,1) or (−1,−1) as depicted in Fig. 2. These SFGs represent four different topologies and are referred respectively as topology 1, topology 2, topology 3 and topology 4. The values of k3and k4 are chosen so that appropriate transfer functions can be obtained. Vin k1 k4 k3 V3 V2 V1 k2-sτ1sτ2 Vo Fig. 1: The proposed differentiator-based SFG. It may be noted that the SFG in Fig. 1 uses an inverting differentiator, followed by a non-inverting differentiator. Alternate SFGs can be derived by placing •a non-inverting differentiator followed by an inverting differentiator, •two non-inverting differentiators, or •two inverting differentiators. The resulting SFGs are depicted in Fig. 3. In each SFG in Fig. 3, k1and k2may further be selected as (1,1),(1,−1),(−1,1) or (−1,−1), thus providing a total to sixteen SFGs, and are shown in Fig. 4. Vin k +1 +1 V3 V2 V1 +1 -sτ1sτ2 Vo (a) Vin k -1 -1 V3 V2 V1 -1 -sτ1sτ2 Vo (b) Vin -k +1 +1 V3 V2 V1 +1 -sτ1sτ2 Vo (c) Vin -k -1 -1 V3 V2 V1 -1 -sτ1sτ2 Vo (d) Fig. 2: SFGs generated from Fig. 1 for k1and k2as (a) topology 1, (b) topology 2, (c) topology 3, (d) topology 4. 2.2. The OTRA The OTRA is an active block with two low-impedance input terminals and a low-impedance output terminal. The circuit symbol of OTRA is given in Fig. 5 and its terminals are characterized by matrix of Eq. (1):   Vp Vn Vo  =  0 0 0 0 0 0 Rm−Rm0  ·  Ip In I0  ,(1) where Rmis trans-resistance gain of OTRA. The value of Rmis ideally infinity; therefore, OTRA is generally used in negative feedback configuration. c 2020 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 32 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 18 |NUMBER: 1 |2020 |MARCH Vin k1k k4 k3 V3 V2 V1 k2sτ1-sτ2 Vo (a) Vin k1k k4 k3 V3 V2 V1 k2sτ1sτ2 Vo (b) Vin k1k k4 k3 V3 V2 V1 k2-sτ1-sτ2 Vo (c) Fig. 3: Alternate SFGs. Vin k -1 +1 V3 V2 V1 +1 sτ1-sτ2 Vo (a) Topology 5: k1= 1,k2= 1. Vin k +1 -1 V3 V2 V1 -1 sτ1-sτ2 Vo (b) Topology 6: k1= 1,k2=−1. Vin -k -1 +1 V3 V2 V1 +1 sτ1-sτ2 Vo (c) Topology 7: k1= 1,k2= 1. Vin -k +1 -1 V3 V2 V1 -1 sτ1-sτ2 Vo (d) Topology 8: k1= 1,k2=−1. Vin k -1 -1 V3 V2 V1 +1 sτ1-sτ2 Vo (e) Topology 9: k1= 1,k2= 1. Vin k +1 +1 V3 V2 V1 -1 sτ1-sτ2 Vo (f) Topology 10: k1= 1,k2=−1. Vin -k -1 -1 V3 V2 V1 +1 sτ1sτ2 Vo (g) Topology 11: k1=−1,k2= 1. Vin -k +1 +1 V3 V2 V1 -1 sτ1sτ2 Vo (h) Topology 12: k1= 1,k2=−1. Vin k +1 -1 V3 V2 V1 +1 -sτ1-sτ2 Vo (i) Topology 13: k1= 1,k2= 1. Vin k +1 +1 V3 V2 V1 -1 -sτ1-sτ2 Vo (j) Topology 14: k1= 1,k2=−1. Vin -k +1 -1 V3 V2 V1 +1 -sτ1-sτ2 Vo (k) Topology 15: k1=−1,k2= 1. Vin -k +1 +1 V3 V2 V1 -1 -sτ1-sτ2 Vo (l) Topology 16: k1=−1,k2=−1. Fig. 4: The SFG structures. Vp Vn Ip In - + RmVo Fig. 5: The OTRA block. A close inspection of SFGs in Fig. 2 and Fig. 4 reveals that the circuit realization would require voltage addition-subtraction followed by amplifier (inverting / non-inverting), and differentiators (inverting / non-inverting). The OTRA-based realization of voltage addition/subtraction is shown in Fig. 6. It uses five resistors and one OTRA. By equating the currents of inverting and non-inverting terminals, the output of the circuit from Fig. 6 is obtained as: Vo=R5V1 R1 +V2 R2 −V3 R3 −V4 R4.(2) Exchanging (Vi, Ri), where i∈ {1,2}with (Vj, Rj), where j∈ {3,4}in Fig. 6 yields the following relation: Vo=−R5V1 R1 +V2 R2 −V3 R3 −V4 R4.(3) It may be noted that Eq. (3) is inverting form of Eq. (2). c 2020 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 33 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 18 |NUMBER: 1 |2020 |MARCH Rm Vo R5 V1 V2 V3 V4 R1 R2 R3 R4 Fig. 6: OTRA-based realization of voltage addition/subtraction. By choosing the values of resistances appropriately, the desired addition-subtraction can be performed. Equation (2) provides non-inverting output, whereas Eq. (3) gives an inverting output. The OTRA-based circuits of inverting and noninverting differentiators are given in Fig. 7 and their respective outputs are given by: Vo=−sCRVin,(4) Vo=−sCRVin.(5) - + C Rm R Vo Vin (a) - + Rm R C Vo Vin (b) Fig. 7: OTRA-based realization of (a) inverting and (b) noninverting differentiators. 2.3. OTRA-Based Realization of SFGs The OTRA-based realization of SFGs can be obtained by using the basic blocks from Fig. 6 and Fig. 7. The corresponding circuit realizations of SFGs from Fig. 2(a), Fig. 2(b), Fig. 2(c) and Fig. 2(d) are depicted respectively in Fig. 8(a), Fig. 8(b), Fig. 8(c) and Fig. 8(d). It may be noted that the realizations from Fig. 8(a) and Fig. 8(b) are same as those given in Fig. 8(c) and Fig. 8(d) respectively, since their corresponding k1k2product terms are the same. - + - + - + Rm V3 R1 R4 R5 R2 R3 C2 C1 V2 V1 Vin R3/k Rm Rm (a) - + - + - + Rm V3 R1 R4 R5 R2 R3 C2 C1 V2 V1 Vin R3/k Rm Rm (b) - + - + - + Rm V3 R1 R4 R5 R2 R3 C2 C1 V2 V1 Vin R3/k Rm Rm (c) - + - + - + Rm V3 R1 R4 R5 R2 R3 C2 C1 V2 V1 Vin R3/k Rm Rm (d) Fig. 8: OTRA-based realization of SFGs from Fig. 2. The transfer functions of the topology in Fig. 8(a) are obtained as: V1 Vin =k D(s), V2 Vin =−k(sR2C2) D(s), V3 Vin =−ks2R1R2C1C2 D(s), (6) where D(s) = 1 + sR2R3C2 R5 +s2R1R2R3C1C2 R4 .(7) c 2020 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 34 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 18 |NUMBER: 1 |2020 |MARCH The transfer functions of the topology in Fig. 8(b) are computed as: V1 Vin =−k D(s), V2 Vin =k(sR2C2) D(s), V3 Vin =ks2R1R2C1C2 D(s). (8) It may be noted that V1,V2and V3respectively represent low pass, band pass and high pass responses. All the transfer functions at different nodes represented by Eq. (6) and Eq. (8) are characterized by following pole frequency (ω0), bandwidth (ω0 Q) and quality factor (Q): ω0=R4 R1R2R3C1C2 1 2,(9) ω0 Q=R4 R1R5C5 ,(10) Q=R5R1C1 R2R3R4C2 1 2.(11) It is clear from Eq. (9), Eq. (10) and Eq. (11) that both bandwidth and quality factor can be adjusted independently by varying R5without modifying the pole frequency. The pole frequency may be varied by changing Riand Ci(i= 1,2) and quality factor may be kept constant by assuming R3=R4=R5and R1 R2=C2 C1. Further, the gain of the filter responses can be changed by varying the value of k. The OTRA-based realizations of the SFGs listed in Fig. 4 are also obtained and omitted for the sake of brevity. The transfer functions are similar to the one given in Eq. (6), Eq. (7) and Eq. (8). 3. The Non-Ideality Analysis The response of the filter may deviate due to nonideality of OTRA. Ideally, the trans-resistance gain Rm is assumed to approach infinity. However, in practice, Rmis a frequency-dependent finite value. Considering a single-pole model for trans-resistance gain, Rm(s)can be expressed as: Rm(s) = R0 1 + s ω ,(12) where R0is low-frequency trans-resistance gain. For high-frequency applications, the trans-resistance gain Rm(s)is approximated as: Rm(s)≈1 sCp ,(13) where Cp=1 R0ω0 .(14) Taking this effect into account, the transfer functions in Fig. 8(a) in presence of finite transimpedance are computed as: V1 Vin n =kn Dn(s), V2 Vin n =−kn(sR2C2) Dn(s) (1 + sR2Cp2), V3 Vin n =−kns2R1R2C1C2 Dn(s) (1 + sR2Cp2) (1 + sR1Cp3), (15) where Dn(s) = (1 + sR3Cp1) + sR2R3C2 R5(1 + sR2Cp2)+ +s2R1R2R3C1C2 R4(1 + sR1Cp3) (1 + sR2Cp2). (16) It is clear from Eq. (15) and Eq. (16) that transfer functions modify in presence of non-ideality. These equations reduce to Eq. (6) and Eq. (7) by choosing the operating frequency below min 1 R3Cp1,1 R2Cp2,1 R1Cp1. 4. Simulation Results To verify the proposed scheme, the functionality of the filter from Fig. 8(a) is tested through SPICE simulations using CMOS OTRA architecture of [34] and 0.18 µm CMOS process parameters provided by MOSIS (AGILENT). Supply voltages ±1.5V are taken. The simulation is performed for pole frequency of 159 kHz and unity quality factor. All the resistances are taken as 10 kΩand capacitor is taken as 100 pF. The simulated frequency response for low pass, band pass and high pass for the circuit from Fig. 8(a) are depicted in Fig. 9. The total power consumption is found to be 6mW. The other set of simulations is carried out to show tuning of band pass filter center frequency and gain. The center frequency is varied by changing R1and R2 simultaneously from 5kΩto 20 kΩin step of 5kΩwhile keeping all other resistances and capacitances at 10 kΩ and 100 pF respectively. This setting leads to constant Qvalue. Figure 11 shows the simulated band pass response for variation in center frequency and Qwith change in resistance. It may be noted that Qvaries slightly from unity value, which may be attributed to non-idealities of OTRA. For variation of band pass response gain while keeping center frequency constant, all resistances except the one connected to input terminal and capacitances are c 2020 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 35 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 18 |NUMBER: 1 |2020 |MARCH 1k 10k 100k 1M 10M 1 2 Gain (-) Frequency (Hz) Fig. 9: Simulated low pass, band pass and high pass responses of the circuit from Fig. 8(a). 0.0 0.2 0.4 0.6 0.8 1.0 -100 -50 0 50 100 input output Time (ms) Voltage (mV) Fig. 10: Time domain waveform of low pass response. chosen as 10 kΩand 100 pF, respectively. The values of k= 1,2and 4are taken to obtain gain of 1,2and 4, respectively. The simulated response is depicted in Fig. 12, which agrees with theoretical predictions. The SPICE simulations are also performed to observe the time domain behavior. All resistances and capacitances are kept at 10 kΩand 100 pF, respectively. A 5kHz sinusoidal input of 50 mV amplitude is applied to the filter and the low pass transient response is depicted in Fig. 10. Total harmonic distortion is also measured by changing input sinusoid amplitude and its value was found to be within 3 % till 150 mV amplitude. Another simulation is done by applying three sinusoids having frequencies of 10 kHz, 100 kHz and 1MHz, respectively. Figure 13 shows the input and output waveforms and corresponding frequency spectrums. It is clear that the sinusoid having 1MHz frequency is significantly attenuated. Monte Carlo simulations are also done to check robustness of the proposed circuits by considering Gaussian distribution for fifty runs with 5% variations in all passive components. For brevity, the histogram of circuit from Fig. 8(a) at LPF node output is depicted 1k 10k 100k 1M 10M 1 2 Frequency (Hz) Gain (-) (a) 5 10 15 20 0.0 200.0k 400.0k Center frequency (kHz) Resistance (kΩ) (b) 5 10 15 20 0.5 1.0 1.5 Resistance (kΩ) Quality factor (-) (c) Fig. 11: Simulated (a) band pass frequency response, (b) center frequency and (c) Qvariation. in Fig. 14, it implies the circuit is well operated within the theoretical frequency. The performance parameters related to power consumption, THD and output noise are presented in [11], [12], [13] and [14]. The same is placed in Tab. 1. The higher power consumption of the proposed topology in c 2020 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 36 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 18 |NUMBER: 1 |2020 |MARCH 1k 10k 100k 1M 10M 0 2 4 Frequency (Hz) Gain (-) (a) 2.5 5.0 7.5 10.0 0 1 2 Quality factor (-) Resistance (kΩ) (b) 2.5 5.0 7.5 10.0 0 2 4 Resistance (kΩ) Gain (-) (c) 2.5 5.0 7.5 10.0 150.00k 175.00k 200.00k Center frequency (kHz) Resistance (kΩ) (d) Fig. 12: Simulated (a) frequency band pass response, (b) Qvariation, (c) gain variation and (d) center frequency variation. 0 100 200 300 -200 0 200 Output Voltage (mV) 0 100 200 300 -200 0 200 Input Voltage (mV) Time (μs) (a) 0 1 2 3 4 5 0 25 50 Frequency (MHz) Input Voltage (mV) 0 1 2 3 4 5 0 25 50 Output Voltage (mV) (b) Fig. 13: Simulated transient low pass response (a) input and output waveforms and its (b) frequency spectrum. c 2020 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 37 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 18 |NUMBER: 1 |2020 |MARCH Tab. 1: Summary of performance parameters. Ref. OTRA implementation Power consumption (%) THD (%) Output noise (µV·Hz− 1 2) [11] CMOS based 4.04 1.7– [12] CFOA based 421 –4 [13] CMOS based 2.58 5.7 0.722 [14] CMOS based 1.09 6.74 0.316 Proposed CMOS based 6 3 0.140 120k 140k 160k 180k 0 5 10 15 20 Frequency (Hz) Percentage samples (%) Fig. 14: Monte Carlo simulation results. compatison with other CMOS-based OTRA implementations may be observed. However, the output noise for the proposed topology is lowest. 5. Conclusion An alternate realization for Single Input Multiple Output (SIMO) filter topologies has been presented in this contribution wherein differentiator is used as basic building block. An SFG is proposed for this purpose, which can further be used to derive sixteen SFGs through proper selection of inverting and non-inverting differentiators placed in loop; and their addition. The active block OTRA is used to verify the concept. All the realizations use three OTRAs, six resistors and two capacitors. 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