Design and control of parallel three phase voltage source Inverters in low voltage AC microgrid

POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 15 |NUMBER: 2 |2017 |JUNE Design and Control of Parallel Three Phase Voltage Source Inverters in Low Voltage AC Microgrid El Hassane MARGOUM 1, Nissrine KRAMI 1, Luis SECA2, Carlos MOREIRA2, Hassan MHARZI 1 1Department of Electrical Engineering, National School of Applied Science, Ibn Tofail University, Kenitra, Morocco 2Institute for Systems and Computer Engineering, Technology and Science (INESC TEC), Faculty of Engineering, University of Porto, R. Dr. Roberto Frias, 4200 Porto, Portugal [email protected], [email protected], [email protected], [email protected], [email protected] DOI: 10.15598/aeee.v15i2.1912 Abstract. Design and hierarchical control of three phase parallel Voltage Source Inverters are developed in this paper. The control scheme is based on synchronous reference frame and consists of primary and secondary control levels. The primary control consists of the droop control and the virtual output impedance loops. This control level is designed to share the active and reactive power correctly between the connected VSIs in order to avoid the undesired circulating current and overload of the connected VSIs. The secondary control is designed to clear the magnitude and the frequency deviations caused by the primary control. The control structure is validated through dynamics simulations.The obtained results demonstrate the effectiveness of the control structure. Keywords Droop control, energy storage systems, hierarchical control, MicroGrid, Smart grid. 1. Introduction The MicroGrid (MG) concept has been proposed in order to increase controllability and observability of the distribution grid [1]. Hence, MG can integrate different types of Distributed Generation (DG) such as Renewable Energy Sources (RES) (PhotoVoltaic (PV) panels, micro windturbines), low carbon technologies, Energy Storage Systems (ESS) and loads. All these components are connected together and smartly managed in order to improve reliability and security of supply at the distribution level [1] and [2]. MG is a flexible system [3]. It can operate in two modes: connected to the main network (grid connected mode) at the Low Voltage (LV) level or autonomously (islanded mode) [3]. In the grid connected mode, the MG can exchange the power with the main grid and can also provide ancillary services to the upstream distribution network, such as reactive power, grid frequency support and so forth [4] and [5]. The amount of power exchanged with the external grid is calculated by the tertiary control functions implemented generally in a MicroGrid Central Controller (MGCC) [3], [5], [6] and [7]. In the case of contingencies or faults occurrence in the main grid, the MG changes the mode of operation from grid connected to islanded mode [4], where the power demanded by the local loads is supplied by local distributed generations, since the MG is operating disconnected from the main grid. The Energy Management System (EMS) takes into account the State of Charge (SoC) of ESSs, controllable sources and controllable loads in order to balance generation and consumption, thus improving reliability, efficiency and security of supply [1], [5], [8] and [9]. The MG requirements and the nature of power generated by DGs make the power converters indispensable components. In the case of AC MG, the final stage is an inverter (DC-AC converter). The inverters are very flexible devices that allow implementation of advanced control solutions in order to increase controllability of the MG, thus enabling further integration c 2017 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 120 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 15 |NUMBER: 2 |2017 |JUNE of intermittent RES [3], [4], [7] and [10]. The power inverters in AC MG can be classified into grid forming and grid feeding units [4]. The grid forming units operate as Voltage Source Inverters (VSI). They are responsible for regulation of frequency and magnitude of the AC bus voltage. Moreover, they are mandatory when the MG operates in islanded mode, since they are the only ones responsible for the voltage regulation. In contrast, the grid feeding units are designed to inject power into the grid and they are often connected to the DGs based on RES such as PV systems and microwind turbines. However, unlike grid forming units, the grid feeding units cannot constitute a MG [4] and [5]. When the MG is operating in the islanded mode, it is necessary to use fast energy storage technologies in order to balance generation and consumption and keep the amplitude and frequency of the common load bus voltage in acceptable limits [10]. The ESS are interfaced by VSIs that are connected in parallel through the MG [1] and [10]. Adequate power sharing is required in order to avoid the undesired circulating current as well as theoverload power converters [3]. Droop control technique has been widely used as an autonomous power sharing solution. This technique is based on local information [3], [4], [5], [7] and [11]. However, it suffers from several drawbacks, especially when it is applied to low voltage grids that have a high R/X ratio due to resistive distribution feeders [3] and [12]. Hence, the active and reactive power are affected by the coupling impedance [13]. An additional control loop called Virtual Output Impedance (VOI) has been proposed [14] and [15], this control loop makes the distribution grid behaving like an inductive grid, thus ensuring the active and reactive power decoupling and improving the system stability. By adding this control loop, the active Power-Frequency (P-ω) and the reactive Power-Voltage (Q-V) can be applied to share the active and reactive power, respectively [4] and [12]. Althoughthe frequency and the voltage are directly involved (frequency and amplitude deviations). For this reason, a centralized controller based on low bandwidth communication links has been proposed in order to restore the frequency and the magnitude to their nominal values [3], [5] and [7]. Hierarchical control structure of MG has been proposed in several works [3], [5], [7] and [16]. This control structure is a compromise between fully centralized and fully decentralized approaches [5]. It includes three main control levels: primary, secondary and tertiary control [3] and [7]. The primary control is responsible for power sharing between the connected inverters in order to avoid the undesired circulating current and converters overload. The secondary control restores the amplitude and the frequency deviations of the load bus voltage caused by the power sharing controller. The tertiary control manages the power between the MG and the main grid [3]. Primary and secondary control for parallel connected VSIs forming an autonomous AC MG are developed and discussed in this paper. The control scheme consists of a local controller and a centralized controller. The local controller includes voltage and current Proportional Integral (PI) controllers based on synchronous reference frame and power sharing controller that consists of droop control and VOI. The secondary control implemented in a centralized controller restores the deviations produced by the power sharing controller. The remainder of this paper is structured as follows: Section 2. presents a design of the MG local controller that consists of inner loops, droop control and virtual output impedance. Section 3. presents a design of the centralized secondary control. Simulation results for two parallel connected VSIs forming an islanded AC MG are presented and discussed in Sec. 4. 2. Local Controller Design: Inner Loops and Primary Control The VSIs local controller is based on local measurements [3], it generally includes droop control, output virtual impedance and inner control loops (Voltage and current loops) [3], [7], [13], [17] and [18]. The block diagram of the VSI local controller is depicted in Fig. 1. The power stage of each VSI consists of a three-leg three phase inverter connected to a Battery Energy Storage System (BESS) through the DC link Capacitor (C), loaded by an LC filter and connected to the MG AC bus through a line impedance. The VSI control system consists of the power sharing controller (droop control and VOI), voltage loop, current loop and the Pulse Width Modulator (PWM). The park transformation is used to transform variables from the natural frame to the synchronous reference frame. More details are presented in the following subsections. 2.1. Inner Loops The VSIs inner control loops are based on synchronous reference frame including an outer voltage loop and an inner current loop as shown in Fig. 2. ProportionalIntegral (PI) controllers are used in two control loops [19]. Voltage and current feed-forward have been added in order to improve performances of the regulators [5]. c 2017 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 121 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 15 |NUMBER: 2 |2017 |JUNE SECTION POLICIES © 2015 ADVANCES IN ELECTRICAL AND EL Fig. 1: VSI local controller Fig. 2: VSI inner control loops 2.2. Primary control If two or more power converters are parallel connected to a common load bus (LB) , the undesired circu current can appear and the power will not be shared properly between the parallel connected converters[3] . In order to solve this power sharing issue, the primary control has been proposed level adapts the frequency and the amplitude of the voltage reference in order to share the active and reactive power properly between the connected VSIs. Thus avoiding the undesired circulating current and the converters overload[3], [4], [7]. This control level consists of droop control and the VOI [3]   !" PWM Inner loops BESS DC/AC Converter #"$ VOLUME: XX IN ELECTRICAL AND EL ECTRONIC ENGINEERING If two or more power converters are parallel connected to , the undesired circu lating current can appear and the power will not be shared parallel connected power . In order to solve this power sharing issue, has been proposed [3]. This control level adapts the frequency and the amplitude of the share the active and reactive power properly between the connected VSIs. Thus the undesired circulating current and the This control level [3] . 2.2.1. Power calculation and droop control The equations of active and reactive power generated by a VSI are given in dqcoordinates variables by (5) and (6), respectively [4]. = % & (∗(+∗ ( = % & (∗(− where  and ( are the capacitor voltage and the current after the LC filter. A block diagram of the power calculation and droop control is shown in Fig.3.  ) *+  ∗  ,   - ) - ( - LC Filter voltage measurment Inner loops Line impedance Droop control Virtual output impedance ,  ,  DC/AC Converter LC Filter Line Impedance  ( - #"$ Power sharing Controller | NUMBER: X | 2015| MONTH 3 Power calculation and droop control The equations of active and reactive power generated by coordinates variables by (5) and ( ) (5) ∗ () (6) are the capacitor voltage and the block diagram of the power calculation and droop (  Power calculation ,  AC Bus Line Impedance - -     Power sharing Controller Fig. 1: VSI local controller. Fig. 2. VSI inner control loops Fig. 3. Block diagram of power calculation and droop control ACAC V ∟δ E ∟0° ZLine=R+jX VSI 1AC Bus Fig. 4.Equivalent circuit of two parallel connected VSIs. Fig. 5. Synchronous reference frame virtual output impedance _ + 𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃 +𝐾𝐾𝑖𝑖𝑃𝑃𝑃𝑃 𝑠𝑠 + + + + _ + 𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃 +𝐾𝐾𝑖𝑖𝑃𝑃𝑃𝑃 𝑠𝑠 + + + + - 𝐿𝐿𝐿𝐿𝐿𝐿 Current loop Voltage loop _ + 𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃 +𝐾𝐾𝑖𝑖𝑃𝑃𝑃𝑃 𝑠𝑠 + + _ + 𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃 +𝐾𝐾𝑖𝑖𝑃𝑃𝑃𝑃 𝑠𝑠 + + Reference 0 + _ + _ 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 𝑉𝑉∗𝑉𝑉 𝑉𝑉∗𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉 𝐼𝐼𝐼𝐼𝑉𝑉𝑉𝑉 𝐼𝐼∗𝑉𝑉 𝐼𝐼∗𝑉𝑉 𝐼𝐼𝐿𝐿𝑉𝑉 𝐼𝐼𝐿𝐿𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉𝐿𝐿𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉𝐿𝐿𝑉𝑉 𝐿𝐿𝐿𝐿𝐿𝐿 𝐿𝐿 𝑃𝑃=𝐿𝐿∗− 𝐺𝐺𝑃𝑃(𝑠𝑠)∗ 𝑃𝑃 𝐸𝐸𝑃𝑃=𝐸𝐸∗− 𝐺𝐺𝑃𝑃(𝑠𝑠) ∗ 𝑄𝑄 𝐿𝐿𝑉𝑉𝑉𝑉𝑠𝑠𝑓𝑓 𝐸𝐸𝑉𝑉𝑉𝑉𝑠𝑠𝑓𝑓 𝑉𝑉𝑉𝑉𝑉𝑉 ∗𝐼𝐼𝐼𝐼𝑉𝑉 +𝑉𝑉𝑉𝑉𝑉𝑉 ∗𝐼𝐼𝐼𝐼𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉 ∗𝐼𝐼𝐼𝐼𝑉𝑉 −𝑉𝑉𝑉𝑉𝑉𝑉 ∗𝐼𝐼𝐼𝐼𝑉𝑉 𝐿𝐿𝑐𝑐 𝑠𝑠+𝐿𝐿𝑐𝑐 𝐿𝐿𝑐𝑐 𝑠𝑠+𝐿𝐿𝑐𝑐 1 𝑠𝑠 𝜙𝜙𝑃𝑃 𝑉𝑉𝑉𝑉 + + + + Power calculation Droop control 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 𝐼𝐼𝐼𝐼𝑉𝑉𝑉𝑉 𝑅𝑅𝑣𝑣∗ 𝐼𝐼𝑜𝑜𝑃𝑃 − 𝐿𝐿𝑣𝑣ω ∗ 𝐼𝐼𝑜𝑜𝑃𝑃 𝐼𝐼𝑜𝑜𝑃𝑃𝑃𝑃 𝑉𝑉𝑧𝑧𝑣𝑣𝑃𝑃 𝑉𝑉 𝑧𝑧𝑣𝑣𝑃𝑃 𝐼𝐼𝐼𝐼𝑉𝑉 𝑉𝑉𝑧𝑧𝑣𝑣𝑃𝑃𝑃𝑃 𝑅𝑅𝑣𝑣∗ 𝐼𝐼𝑜𝑜𝑃𝑃 +𝐿𝐿𝑣𝑣ω ∗ 𝐼𝐼𝑜𝑜𝑃𝑃 𝐼𝐼𝑜𝑜𝑃𝑃 Virtual output impedance −𝑄𝑄𝑚𝑚𝑚𝑚𝑚𝑚 𝐸𝐸ref 0 L load 𝑄𝑄𝑟𝑟𝑟𝑟𝑟𝑟 ∆𝑉𝑉 𝑄𝑄𝑚𝑚𝑚𝑚𝑚𝑚 𝑄𝑄 𝐸𝐸 C load (𝑎𝑎) (𝑏𝑏) −𝑃𝑃 𝑚𝑚𝑚𝑚𝑚𝑚 𝐿𝐿 ref 0 Generation 𝑃𝑃𝑟𝑟𝑟𝑟𝑟𝑟 ∆𝐿𝐿 𝑃𝑃 𝑚𝑚𝑚𝑚𝑚𝑚 𝑃𝑃 𝐿𝐿 Storage Fig. 2: VSI inner control loops. Transfer functions of the voltages (Vdand Vq) and currents (Idand Iq) controllers are given as follows [19]: RV d(s) = KP V d +KiV d s,(1) RV q(s) = KP V q +KiV q s,(2) RId(s) = KP Id +KiId s,(3) RIq(s) = KP Iq +KiIq s,(4) where KP V d (KP V q) are proportional term coefficients of the direct (quadrature) voltage controller, and KiV d (KiV q) are integral term coefficients of the direct (quadrature) voltage controller. KP Id (KP Iq) are proportional term coefficients of the direct (quadrature) current controller, and KiId (KiIq) are integral term coefficients of the direct (quadrature) current controller. A block diagram of the local controller is depicted in Fig. 2. 2.2. Primary Control If two or more power converters are parallel connected to a common Load Bus (LB), the undesired circulating current can appear and the power will not be shared properly between the parallel connected power converters [3]. In order to solve this power sharing issue, the primary control has been proposed [3]. This control level adapts the frequency and the amplitude of the c 2017 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 122 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 15 |NUMBER: 2 |2017 |JUNE Fig. 2. VSI inner control loops Fig. 3. Block diagram of power calculation and droop control ACAC V ∟δ E ∟0° ZLine=R+jX VSI 1AC Bus Fig. 4.Equivalent circuit of two parallel connected VSIs. Fig. 5. Synchronous reference frame virtual output impedance _ + 𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃 +𝐾𝐾𝑖𝑖𝑃𝑃𝑃𝑃 𝑠𝑠 + + + + _ + 𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃 +𝐾𝐾𝑖𝑖𝑃𝑃𝑃𝑃 𝑠𝑠 + + + + - 𝐿𝐿𝐿𝐿𝐿𝐿 Current loop Voltage loop _ + 𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃 +𝐾𝐾𝑖𝑖𝑃𝑃𝑃𝑃 𝑠𝑠 + + _ + 𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃 +𝐾𝐾𝑖𝑖𝑃𝑃𝑃𝑃 𝑠𝑠 + + Reference 0 + _ + _ 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 𝑉𝑉∗𝑉𝑉 𝑉𝑉∗𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉 𝐼𝐼𝐼𝐼𝑉𝑉𝑉𝑉 𝐼𝐼∗𝑉𝑉 𝐼𝐼∗𝑉𝑉 𝐼𝐼𝐿𝐿𝑉𝑉 𝐼𝐼𝐿𝐿𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉𝐿𝐿𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉𝐿𝐿𝑉𝑉 𝐿𝐿𝐿𝐿𝐿𝐿 𝐿𝐿 𝑃𝑃=𝐿𝐿∗− 𝐺𝐺𝑃𝑃(𝑠𝑠)∗ 𝑃𝑃 𝐸𝐸𝑃𝑃=𝐸𝐸∗− 𝐺𝐺𝑃𝑃(𝑠𝑠) ∗ 𝑄𝑄 𝐿𝐿𝑉𝑉𝑉𝑉𝑠𝑠𝑓𝑓 𝐸𝐸𝑉𝑉𝑉𝑉𝑠𝑠𝑓𝑓 𝑉𝑉𝑉𝑉𝑉𝑉 ∗𝐼𝐼𝐼𝐼𝑉𝑉 +𝑉𝑉𝑉𝑉𝑉𝑉 ∗𝐼𝐼𝐼𝐼𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉 ∗𝐼𝐼𝐼𝐼𝑉𝑉 −𝑉𝑉𝑉𝑉𝑉𝑉 ∗𝐼𝐼𝐼𝐼𝑉𝑉 𝐿𝐿𝑐𝑐 𝑠𝑠+𝐿𝐿𝑐𝑐 𝐿𝐿𝑐𝑐 𝑠𝑠+𝐿𝐿𝑐𝑐 1 𝑠𝑠 𝜙𝜙𝑃𝑃 𝑉𝑉𝑉𝑉 + + + + Power calculation Droop control 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 𝐼𝐼𝐼𝐼𝑉𝑉𝑉𝑉 𝑅𝑅𝑣𝑣∗ 𝐼𝐼𝑜𝑜𝑃𝑃 − 𝐿𝐿𝑣𝑣ω ∗ 𝐼𝐼𝑜𝑜𝑃𝑃 𝐼𝐼𝑜𝑜𝑃𝑃𝑃𝑃 𝑉𝑉𝑧𝑧𝑣𝑣𝑃𝑃 𝑉𝑉 𝑧𝑧𝑣𝑣𝑃𝑃 𝐼𝐼𝐼𝐼𝑉𝑉 𝑉𝑉𝑧𝑧𝑣𝑣𝑃𝑃𝑃𝑃 𝑅𝑅𝑣𝑣∗ 𝐼𝐼𝑜𝑜𝑃𝑃 +𝐿𝐿𝑣𝑣ω ∗ 𝐼𝐼𝑜𝑜𝑃𝑃 𝐼𝐼𝑜𝑜𝑃𝑃 Virtual output impedance −𝑄𝑄𝑚𝑚𝑚𝑚𝑚𝑚 𝐸𝐸ref 0 L load 𝑄𝑄𝑟𝑟𝑟𝑟𝑟𝑟 ∆𝑉𝑉 𝑄𝑄𝑚𝑚𝑚𝑚𝑚𝑚 𝑄𝑄 𝐸𝐸 C load (𝑎𝑎) (𝑏𝑏) −𝑃𝑃 𝑚𝑚𝑚𝑚𝑚𝑚 𝐿𝐿 ref 0 Generation 𝑃𝑃𝑟𝑟𝑟𝑟𝑟𝑟 ∆𝐿𝐿 𝑃𝑃 𝑚𝑚𝑚𝑚𝑚𝑚 𝑃𝑃 𝐿𝐿 Storage Fig. 3: Block diagram of power calculation and droop control. voltage reference in order to share the active and reactive power properly between the connected VSIs. Thus avoiding the undesired circulating current and the converters overload [3], [4] and [7]. This control level consists of droop control and the VOI [3]. 1) Power Calculation and Droop Control The equations of active and reactive power generated by a VSI are given in dq-coordinates variables by Eq. (5) and Eq. (6), respectively [4]. P=3 2(Vcd ·Iod +Vcq ·Ioq),(5) Q=3 2(Vcq ·Iod −Vcd ·Ioq),(6) where V cdq and Iodq are the capacitor voltage and the current after the LC filter. A block diagram of the power calculation and droop control is shown in Fig. 3. The Park transformation is used to obtain the dqcoordinates variables.   Xd Xq X0  = =2 3  cos(θ) cos(θ−2π 3) cos(θ+2π 3) sin(θ) sin(θ−2π 3) sin(θ+2π 3) 1 2 1 2 1 2    Xa Xb Xc  , (7) where (Xd, Xq, X0) is the variable vector in synchronous reference frame and (Xa, Xb, Xc) is the variable vector in the natural reference frame. In order to filter the active and reactive power ripples a first order Low Pass Filter (LPF) is used. The transfer function of the LPF is given by Eq. (8): LP F (s) = ωc s+ωc ,(8) where ωcis the LPF cut-off frequency. A MG consists of a number of parallel connected converters [11]. Figure 4 shows the equivalent circuit of ACAC V ∟δ E ∟0° ZLine=R+jX VSI 1AC Bus Fig. 4: Equivalent circuit of two parallel connected VSIs. a VSI connected in parallel with an AC bus. The active and reactive power delivered by the VSI are expressed as follows [20]: P=EV Zcos δ−V2 Zcos θ+EV Zsin δ·sin θ, (9) Q=EV Zcos δ−V2 Zsin θ−EV Zsin δ·cos θ, (10) where Vand Eare the VSI voltage amplitude and AC bus voltage amplitude, respectively, Zand θare the amplitude and the angle of the line impedance, respectively, δis the load angle. When the coupling impedance is mainly inductive, the active and reactive power equations become as follows: P≈EV Xsin δ, (11) Q≈EV Xcos δ−V2 X.(12) Low voltage grids have a high R X. In this work we have used the VOI to ensure the inductive behavior of the line impedance. We assumed that the equivalent line impedance is mainly inductive. The frequency and voltage droop expressions are given by Eq. (13) and Eq. (14), respectively: fd=fref −GP(S)·P, (13) Ed=Eref −GQ(S)·Q. (14) c 2017 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 123 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 15 |NUMBER: 2 |2017 |JUNE Fig. 2. VSI inner control loops Fig. 3. Block diagram of power calculation and droop control ACAC V ∟δ E ∟0° ZLine=R+jX VSI 1AC Bus Fig. 4.Equivalent circuit of two parallel connected VSIs. Fig. 5. Synchronous reference frame virtual output impedance _ + 𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃 +𝐾𝐾𝑖𝑖𝑃𝑃𝑃𝑃 𝑠𝑠 + + + + _ + 𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃 +𝐾𝐾𝑖𝑖𝑃𝑃𝑃𝑃 𝑠𝑠 +++ + - 𝐿𝐿𝐿𝐿𝐿𝐿 Current loop Voltage loop _ + 𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃 +𝐾𝐾𝑖𝑖𝑃𝑃𝑃𝑃 𝑠𝑠 + + _+ 𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃 +𝐾𝐾𝑖𝑖𝑃𝑃𝑃𝑃 𝑠𝑠 + + Reference 0 + _ + _ 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 𝑉𝑉∗𝑉𝑉 𝑉𝑉∗𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉 𝐼𝐼𝐼𝐼𝑉𝑉𝑉𝑉 𝐼𝐼∗𝑉𝑉 𝐼𝐼∗𝑉𝑉 𝐼𝐼𝐿𝐿𝑉𝑉 𝐼𝐼𝐿𝐿𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉𝐿𝐿𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉𝐿𝐿𝑉𝑉 𝐿𝐿𝐿𝐿𝐿𝐿 𝐿𝐿 𝑃𝑃=𝐿𝐿∗− 𝐺𝐺𝑃𝑃(𝑠𝑠)∗ 𝑃𝑃 𝐸𝐸𝑃𝑃=𝐸𝐸∗− 𝐺𝐺𝑃𝑃(𝑠𝑠) ∗ 𝑄𝑄 𝐿𝐿𝑉𝑉𝑉𝑉𝑠𝑠𝑓𝑓 𝐸𝐸𝑉𝑉𝑉𝑉𝑠𝑠𝑓𝑓 𝑉𝑉𝑉𝑉𝑉𝑉 ∗𝐼𝐼𝐼𝐼𝑉𝑉 +𝑉𝑉𝑉𝑉𝑉𝑉 ∗𝐼𝐼𝐼𝐼𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉 ∗𝐼𝐼𝐼𝐼𝑉𝑉 −𝑉𝑉𝑉𝑉𝑉𝑉 ∗𝐼𝐼𝐼𝐼𝑉𝑉 𝐿𝐿𝑐𝑐 𝑠𝑠+𝐿𝐿𝑐𝑐 𝐿𝐿𝑐𝑐 𝑠𝑠+𝐿𝐿𝑐𝑐 1 𝑠𝑠 𝜙𝜙𝑃𝑃 𝑉𝑉𝑉𝑉 + + + + Power calculationDroop control 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 𝐼𝐼𝐼𝐼𝑉𝑉𝑉𝑉 𝑅𝑅𝑣𝑣∗ 𝐼𝐼𝑜𝑜𝑃𝑃 − 𝐿𝐿𝑣𝑣ω ∗ 𝐼𝐼𝑜𝑜𝑃𝑃 𝐼𝐼𝑜𝑜𝑃𝑃𝑃𝑃 𝑉𝑉𝑧𝑧𝑣𝑣𝑃𝑃 𝑉𝑉 𝑧𝑧𝑣𝑣𝑃𝑃 𝐼𝐼𝐼𝐼𝑉𝑉 𝑉𝑉𝑧𝑧𝑣𝑣𝑃𝑃𝑃𝑃 𝑅𝑅𝑣𝑣∗ 𝐼𝐼𝑜𝑜𝑃𝑃 +𝐿𝐿𝑣𝑣ω ∗ 𝐼𝐼𝑜𝑜𝑃𝑃 𝐼𝐼𝑜𝑜𝑃𝑃 Virtual output impedance −𝑄𝑄𝑚𝑚𝑚𝑚𝑚𝑚 𝐸𝐸ref 0 L load 𝑄𝑄𝑟𝑟𝑟𝑟𝑟𝑟 ∆𝑉𝑉 𝑄𝑄𝑚𝑚𝑚𝑚𝑚𝑚 𝑄𝑄 𝐸𝐸 C load (𝑎𝑎) (𝑏𝑏) −𝑃𝑃 𝑚𝑚𝑚𝑚𝑚𝑚 𝐿𝐿 ref 0 Generation 𝑃𝑃𝑟𝑟𝑟𝑟𝑟𝑟 ∆𝐿𝐿 𝑃𝑃 𝑚𝑚𝑚𝑚𝑚𝑚 𝑃𝑃 𝐿𝐿 Storage (a) Fig. 2. VSI inner control loops Fig. 3. Block diagram of power calculation and droop control ACAC V ∟δ E ∟0° ZLine=R+jX VSI 1AC Bus Fig. 4.Equivalent circuit of two parallel connected VSIs. Fig. 5. Synchronous reference frame virtual output impedance _ + 𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃 +𝐾𝐾𝑖𝑖𝑃𝑃𝑃𝑃 𝑠𝑠 + + + + _ + 𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃 +𝐾𝐾𝑖𝑖𝑃𝑃𝑃𝑃 𝑠𝑠 +++ + - 𝐿𝐿𝐿𝐿𝐿𝐿 Current loop Voltage loop _ + 𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃 +𝐾𝐾𝑖𝑖𝑃𝑃𝑃𝑃 𝑠𝑠 + + _+ 𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃 +𝐾𝐾𝑖𝑖𝑃𝑃𝑃𝑃 𝑠𝑠 + + Reference 0 + _ + _ 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 𝑉𝑉∗𝑉𝑉 𝑉𝑉∗𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉 𝐼𝐼𝐼𝐼𝑉𝑉𝑉𝑉 𝐼𝐼∗𝑉𝑉 𝐼𝐼∗𝑉𝑉 𝐼𝐼𝐿𝐿𝑉𝑉 𝐼𝐼𝐿𝐿𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉𝐿𝐿𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉𝐿𝐿𝑉𝑉 𝐿𝐿𝐿𝐿𝐿𝐿 𝐿𝐿 𝑃𝑃=𝐿𝐿∗− 𝐺𝐺𝑃𝑃(𝑠𝑠)∗ 𝑃𝑃 𝐸𝐸𝑃𝑃=𝐸𝐸∗− 𝐺𝐺𝑃𝑃(𝑠𝑠) ∗ 𝑄𝑄 𝐿𝐿𝑉𝑉𝑉𝑉𝑠𝑠𝑓𝑓 𝐸𝐸𝑉𝑉𝑉𝑉𝑠𝑠𝑓𝑓 𝑉𝑉𝑉𝑉𝑉𝑉 ∗𝐼𝐼𝐼𝐼𝑉𝑉 +𝑉𝑉𝑉𝑉𝑉𝑉 ∗𝐼𝐼𝐼𝐼𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉 ∗𝐼𝐼𝐼𝐼𝑉𝑉 −𝑉𝑉𝑉𝑉𝑉𝑉 ∗𝐼𝐼𝐼𝐼𝑉𝑉 𝐿𝐿𝑐𝑐 𝑠𝑠+𝐿𝐿𝑐𝑐 𝐿𝐿𝑐𝑐 𝑠𝑠+𝐿𝐿𝑐𝑐 1 𝑠𝑠 𝜙𝜙𝑃𝑃 𝑉𝑉𝑉𝑉 + + + + Power calculationDroop control 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 𝐼𝐼𝐼𝐼𝑉𝑉𝑉𝑉 𝑅𝑅𝑣𝑣∗ 𝐼𝐼𝑜𝑜𝑃𝑃 − 𝐿𝐿𝑣𝑣ω ∗ 𝐼𝐼𝑜𝑜𝑃𝑃 𝐼𝐼𝑜𝑜𝑃𝑃𝑃𝑃 𝑉𝑉𝑧𝑧𝑣𝑣𝑃𝑃 𝑉𝑉 𝑧𝑧𝑣𝑣𝑃𝑃 𝐼𝐼𝐼𝐼𝑉𝑉 𝑉𝑉𝑧𝑧𝑣𝑣𝑃𝑃𝑃𝑃 𝑅𝑅𝑣𝑣∗ 𝐼𝐼𝑜𝑜𝑃𝑃 +𝐿𝐿𝑣𝑣ω ∗ 𝐼𝐼𝑜𝑜𝑃𝑃 𝐼𝐼𝑜𝑜𝑃𝑃 Virtual output impedance −𝑄𝑄𝑚𝑚𝑚𝑚𝑚𝑚 𝐸𝐸ref 0 L load 𝑄𝑄𝑟𝑟𝑟𝑟𝑟𝑟 ∆𝑉𝑉 𝑄𝑄𝑚𝑚𝑚𝑚𝑚𝑚 𝑄𝑄 𝐸𝐸 C load (𝑎𝑎) (𝑏𝑏) −𝑃𝑃 𝑚𝑚𝑚𝑚𝑚𝑚 𝐿𝐿 ref 0 Generation 𝑃𝑃𝑟𝑟𝑟𝑟𝑟𝑟 ∆𝐿𝐿 𝑃𝑃 𝑚𝑚𝑚𝑚𝑚𝑚 𝑃𝑃 𝐿𝐿 Storage (b) Fig. 5: Frequency (a) and voltage (b) droop characteristics for inductive line impedance. These equations are graphically presented as depicted in Fig. 5. Where Eref and fref are the voltage magnitude and frequency reference, respectively, Ed,fdand φdare the drooped voltage magnitude, frequency and the phase reference, respectively, Pand Qare the measured active and reactive power. GP(s)and GP(s)can be designed as follows: GP(s) = Kp =∆f Pmax ,(15) Gq(s) = Kq =∆E 2Qmax ,(16) where Kp and Kq are the proportional coefficients of the frequency and the voltage droop, respectively, ∆f and ∆Eare the maximum acceptable deviation of the frequency and the voltage, respectively, Pmax and Qmax are the maximum active and reactive power delivered by the VSI, respectively. 2) Virtual Output Impedance (VOI) When the coupling impedance is not purely inductive, the traditional droop control scheme cannot be applied directly. However, the droop control is not enough to ensure the system stability and reactive power sharing between the connected VSIs. For this reason, a virtual impedance loop was proposed in the technical literature [3], [11], [12], [13], [15], [21], [22] and [23]. The objective of this control loop is to decouple active and reactive power control [4] and [24], thus ensuring the system stability and improving the performances of the droop control without causing any power losses. The VOI loop consists of dropping the voltage reference calculated by the droop control loop proportionally to the output current. The dropped voltage reference is expressed as follows: Vref =Vd−Zv(s)·Io,(17) where Zv(s)is the VOI transfer function, Vdvoltage reference calculated by the droop control loop and Iois the output current after the LC filter. Fig. 2. VSI inner control loops Fig. 3. Block diagram of power calculation and droop control ACAC V ∟δ E ∟0° ZLine=R+jX VSI 1AC Bus Fig. 4.Equivalent circuit of two parallel connected VSIs. Fig. 5. Synchronous reference frame virtual output impedance _ + 𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃 +𝐾𝐾𝑖𝑖𝑃𝑃𝑃𝑃 𝑠𝑠 + + + + _ + 𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃 +𝐾𝐾𝑖𝑖𝑃𝑃𝑃𝑃 𝑠𝑠 + + + + - 𝐿𝐿𝐿𝐿𝐿𝐿 Current loop Voltage loop _ + 𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃 +𝐾𝐾𝑖𝑖𝑃𝑃𝑃𝑃 𝑠𝑠 + + _ + 𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃 +𝐾𝐾𝑖𝑖𝑃𝑃𝑃𝑃 𝑠𝑠 + + Reference 0 + _ + _ 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 𝑉𝑉∗𝑉𝑉 𝑉𝑉∗𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉 𝐼𝐼𝐼𝐼𝑉𝑉𝑉𝑉 𝐼𝐼∗𝑉𝑉 𝐼𝐼∗𝑉𝑉 𝐼𝐼𝐿𝐿𝑉𝑉 𝐼𝐼𝐿𝐿𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉𝐿𝐿𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉𝐿𝐿𝑉𝑉 𝐿𝐿𝐿𝐿𝐿𝐿 𝐿𝐿 𝑃𝑃=𝐿𝐿∗− 𝐺𝐺𝑃𝑃(𝑠𝑠)∗ 𝑃𝑃 𝐸𝐸𝑃𝑃=𝐸𝐸∗− 𝐺𝐺𝑃𝑃(𝑠𝑠) ∗ 𝑄𝑄 𝐿𝐿𝑉𝑉𝑉𝑉𝑠𝑠𝑓𝑓 𝐸𝐸𝑉𝑉𝑉𝑉𝑠𝑠𝑓𝑓 𝑉𝑉𝑉𝑉𝑉𝑉 ∗𝐼𝐼𝐼𝐼𝑉𝑉 +𝑉𝑉𝑉𝑉𝑉𝑉 ∗𝐼𝐼𝐼𝐼𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉 ∗𝐼𝐼𝐼𝐼𝑉𝑉 −𝑉𝑉𝑉𝑉𝑉𝑉 ∗𝐼𝐼𝐼𝐼𝑉𝑉 𝐿𝐿𝑐𝑐 𝑠𝑠+𝐿𝐿𝑐𝑐 𝐿𝐿𝑐𝑐 𝑠𝑠+𝐿𝐿𝑐𝑐 1 𝑠𝑠 𝜙𝜙𝑃𝑃 𝑉𝑉𝑉𝑉 + + + + Power calculation Droop control 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 𝐼𝐼𝐼𝐼𝑉𝑉𝑉𝑉 𝑅𝑅𝑣𝑣∗ 𝐼𝐼𝑜𝑜𝑃𝑃 − 𝐿𝐿𝑣𝑣ω ∗ 𝐼𝐼𝑜𝑜𝑃𝑃 𝐼𝐼𝑜𝑜𝑃𝑃𝑃𝑃 𝑉𝑉𝑧𝑧𝑣𝑣𝑃𝑃 𝑉𝑉 𝑧𝑧𝑣𝑣𝑃𝑃 𝐼𝐼𝐼𝐼𝑉𝑉 𝑉𝑉𝑧𝑧𝑣𝑣𝑃𝑃𝑃𝑃 𝑅𝑅𝑣𝑣∗ 𝐼𝐼𝑜𝑜𝑃𝑃 +𝐿𝐿𝑣𝑣ω ∗ 𝐼𝐼𝑜𝑜𝑃𝑃 𝐼𝐼𝑜𝑜𝑃𝑃 Virtual output impedance −𝑄𝑄𝑚𝑚𝑚𝑚𝑚𝑚 𝐸𝐸ref 0 L load 𝑄𝑄𝑟𝑟𝑟𝑟𝑟𝑟 ∆𝑉𝑉 𝑄𝑄𝑚𝑚𝑚𝑚𝑚𝑚 𝑄𝑄 𝐸𝐸 C load (𝑎𝑎) (𝑏𝑏) −𝑃𝑃 𝑚𝑚𝑚𝑚𝑚𝑚 𝐿𝐿 ref 0 Generation 𝑃𝑃𝑟𝑟𝑟𝑟𝑟𝑟 ∆𝐿𝐿 𝑃𝑃 𝑚𝑚𝑚𝑚𝑚𝑚 𝑃𝑃 𝐿𝐿 Storage Fig. 6: Synchronous reference frame virtual output impedance. The synchronous reference frame VOI depicted in Fig. 6 is adopted in this work. The VOI equations are given in dq-coordinates as follows [12] and [24]: Vzvd =Rv·Iod −Lvω·Ioq,(18) Vzvq =Rv·Ioq +Lvω·Iod,(19) where Rvand Lvbeing the virtual resistance and the virtual inductance and Iodq is the dq-coordinates output current of the VSI after the LC filter (as shown in Fig. 1). The virtual resistance has been added in order to damp the oscillations [22]. As the virtual inductance is high as good power sharing performances are achieved. However, its size is limited by the maximum voltage deviations in the LB. Since, the VOI drops the voltage reference generated by the droop control loop proportionally to the output current. 3. Centralized Controller Design: Secondary Control Droop control and virtual output impedance control loop produce voltage and frequency deviations. The secondary control is designed to restore these deviations and keep the frequency and the amplitude at the LB in the allowable limits [3] and [6]. The secondary controller is based on two PI controllers, one restores the voltage deviations and the other one restores the frequency deviations. The secondary control block diagram is depicted in Fig. 7. $ qr n$ $ [\t  ] +  ]  $ [\] U u^ nU  ] +  ]  U + + _ _ Fig. 7: Block diagram of Secondary control level. c 2017 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 124 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 15 |NUMBER: 2 |2017 |JUNE Voltage source invetrer 1 BESS Load 1 Load 2 Load N BESS Main Grid Switch L O A D _ B U S Line impedance ZGrid Line impedance ZVSI1 Line impedance ZVSI2 Energy storage system Energy storage system Voltage source invetrer 2 ^ Fig. 8: Block diagram of two parallel connected VSIs with distributed loads forming an AC MicroGrid. The voltage and frequency restoration signals can be calculated as follows [3]: δf =kpf (f∗ MG −fMG) + kif R(f∗ MG −fMG)dt, (20) δE = =kpE(E∗ MG −EMG) + kiE R(E∗ MG −EMG)dt, (21) where δf (δE) are the frequency (amplitude) restoration signals, f∗ MG (E∗ MG) and fMG (EMG) are the reference of the frequency (amplitude) and the measured frequency (amplitude) at the LB, respectively, KP f (KP E) are the proportional term coefficients of the frequency (voltage) PI controller, and Kif (KiE) are the integral term coefficients of the frequency (amplitude) PI controller, respectively. 4. Simulation Results In order to evaluate the control system performances, an islanded MG formed by two parallel connected VSIs, as shown in Fig. 8, are simulated using Matlab/Simulink environment. Each inverter is connected to the LB through a line impedance, the output impedance of two VSIs are not equal, ZVSI2= 2·VSI1 as seen in Fig. 8. The system parameters are listed in Tab. 1 The switching frequency of the VSIs is set to 20 kHz. In order to show clearly the active and reactive power sharing between the connected converters at different load conditions, three loads are connected to the load bus at different times (unbalanced loads are not considered in this study). Figure 9 shows the power sharing between the VSIs. After the connection of load 1 to the LB from t= 0 s to t= 5 s, the active power is shared properly between the VSIs and the reactive power is shared with a small error. Then, load 2 is connected at t= 5 s, and disconnected at t= 10 s. Meanwhile, the active power at the LB increases from 5 kW to 10 kW. As a consequence, the reactive power error between the two VSIs increases. This error is due to the strong coupling between the active and reactive power. At t= 15 s, the second VSI is disconnected from the LB and thenthe connected loads are supplied by one VSI. At t= 17, another active load of 1 kW is connected to the LB. Figure 10 shows the output voltage at the LB. Figure 11 and Fig. 12 show the output current of VSI1 and VSI2, respectively. The main disadvantage of the droop control is the steady state voltage and frequency deviations, the power sharing is achieved through dropping the amplitude and the frequency of the voltage. Figure 13 shows the nominal and measured values of the frequency of the load bus voltagethat drops proportionally to the active power. Figure 14 shows the nominal voltage (220 V) and the load bus voltage, the load bus voltage drops proportionally to the reactive power. Fig. 9: Active and reactive power sharing. c 2017 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 125 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 15 |NUMBER: 2 |2017 |JUNE Tab. 1: System parameters. Power stage Parameter Value Nominal RMS voltage: Vrms (V) 220 Nominal frequency: f (Hz) 50 DC voltage: Vdc (V) 650 Inverter filter inductance: Lf(H) 2.0E-3 Inverter filter capacitance: Cf(F) 11.0E-6 VSI 1 line impedance: ZVSI1=R1+jX1 0.2+j0.0126 VSI 2 line impedance: ZVSI2=R2+jX2 0.4+j0.0252 load 1: P (kW), Q (KVAR) P=5, Q=250 load 2: P (kW), Q (KVAR) P=5 load 3: P (kW), Q (KVAR) P=1 Inner loops Voltage controller PI Current controller PI KpVd = 0.5, KiVd = 1000, KpVq = 0.15, KiVq = 300. KpId = 40, KiId = 85, KpIq = 40, KiIq = 85. Primary control Droop control Virtual output impedance Kp=3.33E-5 Kq=22E-3 Rv=1ΩLzv=7 mH Secondary control Frequency restoration Voltage restoration Kpf=15E-4 Kif=500 KpE=15E-4 KiE=1000 Power calculation filters: T= 0.2 Fig. 10: Output voltage of a VSI. Fig. 11: Output current of a VSI1. Fig. 12: Output current of a VSI2. Fig. 13: Frequency reference and LB frequency without secondary control. Fig. 14: RMS voltage reference and LB RMS voltage without secondary control. In order to keep the frequency and the amplitude of the load bus voltage in acceptable limits, the secondary control is used. Figure 15 and Fig. 16 show the reference and the measured frequency and voltage in the LB respectively. The secondary control restores correctly the deviations produced by the primary control. The frequency and RMS voltage of the LB are kept in the allowable limits. The load bus frequency and voltage overshoots in Fig. 15 and Fig. 16 are causedby the disconnection of load 2 at t= 10 s, the secondary control regulated the voltage and the frequencyto their nominal values. c 2017 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 126 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 15 |NUMBER: 2 |2017 |JUNE Fig. 15: Frequency reference and LB frequency with secondary control. Fig. 16: RMS voltage reference and LB RMS voltage with secondary control. 5. Conclusion Design and analysis of inner control loops, Primary and secondary control for parallel connected VSIs forming a low voltage MG are presented in this paper. The inner control loops are based on synchronous reference frame. PI controllers are used in voltage and current loops. The primary control includes droop control and a VOI loop. The centralized secondary control includes voltage and frequency restoration controllers. The simulation results are also presented and show that the active and reactive power are shared properly. The amplitude and the frequency of the LB voltage are restored by the centralized secondary control and kept in the allowable limits. Acknowledgment This work was supported by IRESEN (Institut de Recherche en Energie Solaire et Energies Nouvelles) of Morocco in the framework of the Inno-PV research project "SECRETS - Sustainable Energy Clusters REalized Through Smart Grids". References [1] GOUVEIA, C., J. MOREIRA, C. L. MOREIRA and J. A. PECAS LOPES. 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