Competitive cost-effective memory access predictor through short-term online SVM and dynamic vocabularies

Competitive cost-effective memory access predictor through short-term online SVM and dynamic vocabularies Pablo Sanchez-Cuevas a,b,∗,Fernando Diaz-del-Rio a,b,c,Daniel Casanueva-Morato a,b, Antonio Rios-Navarro a,b,c aRobotics and Technology of Computers Lab, Universidad de Sevilla. Avenida Reina Mercedes s/n, 41012 Sevilla, Spain bSmart Computer Systems Research and Engineering Lab (SCORE), Universidad de Sevilla. Avenida Reina Mercedes s/n, 41012 Sevilla, Spain cResearch Institute of Computer Engineering (I3US), Universidad de Sevilla. Avenida Reina Mercedes s/n, 41012 Sevilla, Spain A R T I C L E I N F O Keywords: Address prediction Support vector machines Memory access Superscalar processors Machine learning A B S T R A C T In recent years, there has been a significant increase in the processing of massive amounts of data, driven by the growing demands of mobile systems, parallel and distributed architectures, and real-time systems. This applies to various types of platforms, both specific and general-purpose. Despite numerous advancements in Computer Systems, a critical challenge remains: the efficiency and speed of memory access. This bottleneck is being addressed through cache prefetching, that is, by predicting the next memory address to be accessed and then by having always prefetched in the cache system those data to be used shortly by the processor. This paper explores established intelligent techniques for address prediction, examining their limitations and analyzing the memory access patterns of popular software applications. Building on the successes of previous intelligent predictors based on Machine and Deep Learning models, we introduce a new predictor, SVM4AP (Support Vector Machine For Address Prediction), designed to overcome the identified drawbacks of its predecessors. The architecture of SVM4AP improves the trade-off between performance and cost, compared to those previous proposals in the literature, achieving high accuracy through short-term learning. Comparisons are made with two prominent predictors from the literature: the classical DFCM (Differential Finite Context Method) and the contemporary Deep Learning-based DCLSTM (Doubly Compressed Long-Short Term Memory). The results demonstrate that SVM4AP achieves superior cost-effectiveness across various configurations. Simulations reveal that SVM4AP configurations dominate both DFCM and DCLSTM counterparts, forming the majority of the first Paretto front. Particularly noteworthy is the significant advantage of our proposal for small-size predictors. Furthermore, we release an open-source tool enabling the scientific community to reproduce the results presented in this paper using a set of benchmark traces. 1. Introduction Today’s society is increasingly dependent on computing to perform various activities and solve problems, but at the same time, computing has become more difficult to support and manage due to its diversity and sophistication. The aim is to expand the enormous set of services provided by large infrastructures such as the Internet, in addition to integrate Artificial Intelligence functionalities: optimization of processes and resources, computer vision, pattern recognition, intelligent generation of multimedia content, etc. Moreover, the aim is to apply these requirements in all kinds of scenarios, provided not only by general-purpose computers but also by specific-purpose systems with significant constraints. ∗Corresponding author. Computer architects undoubtedly face great challenges and great opportunities in this context. In response to computational demand, many new architectures have been proposed that exploit all levels of parallelism and improve efficiency. Examples in recent years include SoCs (System on Chip), TPUs (Tensor Processing Units), and IoT (Internet of Things) networks, among others. Another front of evolution has been microarchitecture. Among other issues, memory access remains one of the biggest bottlenecks [1]. Historically, memory hierarchies, in general, and cache systems, in particular, have alleviated this problem both for the CPU and for other systems and devices, e.g., in the case of non-volatile storage [2]. Even so, techniques such as prefetching, which consists of preloading E-mail addresses: [email protected] (P. Sanchez-Cuevas), [email protected] (F. Diaz-del-Rio), [email protected] (D. Casanueva-Morato), [email protected] (A. Rios-Navarro). https://doi.org/10.1016/j.future.2024.107592 Received 30 January 2024; Received in revised form 3 July 2024; Accepted 30 September 2024 P. Sanchez-Cuevas et al. the most likely data to be used by the processor a posteriori, have been integrated to optimize these systems [3]. However, given the demand for massive data computation, this bottleneck requires additional optimizations. Following the success of branch predictors, e.g., TAGE [4], value predictors suppose an optimization of memory usage, which allows predicting the final value of a memory read instruction [5]. Thanks to these predictors, instructions can be executed speculatively, avoiding the waiting time of a prior memory access instruction. A variant of such value predictors is access prediction, which aims at predicting the memory address used by a memory read or write instruction. The latter technique is now widely used for a much more effective and accurate prefetching, since memory access patterns hold a high statistical auto-correlation in most programs and algorithms [6]. In particular, the aim is to always have prefetched in the cache system all the data to be used by the processor. In addition, this would allow us to insert (speculatively) the prefetched data directly into the processor’s execution engine, thus being able to apply value speculation [7]. Due to the importance of access prediction, in this paper, we propose a novel prediction model called Support Vector Machine For Address Prediction (SVM4AP), which results in a substantial improvement in cost-effectiveness compared to the classical Differential Finite Context Method (DFCM) predictor and the recent Doubly Compressed Long-Short Term Memory (DCLSTM). The main factors that support this difference are the use of a high learning rate SVM model, the mapping of address deltas in a dynamic dictionary, and the lower capacity required for SVM4AP’s modules, resulting in a predictor that achieves high precision based on the short-term learning of access patterns. Indeed, both simple and complex access patterns are captured by the learning model (the SVM) easily by predicting, not over the previous deltas, but rather over the dictionary classes these are mapped. In summary, the main contributions of our proposal are as follows. •We propose the SVM4AP predictor based on three main components: (1) an input buffer that records the context of each memory access instruction; (2) a linear SVM that, given the access history, predicts the next address delta as a dictionary class; and (3) a tiny dictionary that indexes each class to a delta. •We successfully tackle full-dynamism by designing our proposal where, in contrast to other Machine and Deep Learning stateof-the-art counterparts, the SVM performs online learning, plus the non-static dictionary is maintained via an LFU replacement policy. •We perform quantitative comparisons with the state-of-the-art DFCM and DCLSTM predictors, showing in both cases a clear improvement in terms of cost-effectiveness. •We release an open-source implementation of the presented experiments, from which the scientific community can reproduce the results and/or develop their own address predictors. In Section 2, the characteristics of both classical and novel predictors are explored. In Section 3the characteristics of the usual memory access patterns and their relations with the predictors are described. In Section 4design improvements concerning predictors from the literature are discussed, leading to the design proposed in Section 5. Section 6specifies the test suite to evaluate the performance of SVM4AP concerning DFCM and DCLSTM. Finally, the conclusions and ideas for future work are summarized in Section 7. 2. Related works Most of the classical methods perform address prediction by implementing a table-based value predictor: the intermediary or final prediction values are stored in different tables and are indexed by a feature associated with the corresponding memory access instruction. The Last Value Predictor (LVP, Gabbay and Mendelson [8]) is one of these cases, for which a single table is implemented and returns a predicted address given the Program Counter (PC) of a memory access instruction. Another predictor of interest is the DFCM [9], which is to be used as a baseline for comparisons in this work. The DFCM presents two separate tables: a first one (called Value History Table or VHT) accessed by the PC of the memory read/write instruction that returns a hash value and the address of the previous access of the same instruction; and a second one (called Value Prediction Table or VPT) accessed by the hash value obtained from the first table and returns the stride or delta (difference between two consecutive accessed addresses) that is summed with the address of the previous access, resulting in the predicted address. A final example of a table-based predictor of relevance is the Value TAgged GEometric [10], which was developed from the TAGE branch predictor [4]. It features a global branch history that is hashed with the PC of the memory access instruction in order to index a sequence of tables, each storing value predictions. Among the predictions given by the tables, the one indexed by the highest number of global branch history bits is selected. These classical predictors have the advantage of being simple and having low hardware cost, incurring a latency equal to the time required to obtain the final results from the tables. However, this memory-based mapping comes with a performance that is highly dependent on those most possible access contexts that are stored in a table of limited capacity. Therefore, the performance of classical predictors is highly dependent on memory cost and complexity and disparity of the access contexts of a given program [11]. Novel methods try to overcome such restrictions by implementing the mapping function using a Machine Learning model. This follows a remarkable evolution in Computer Architecture for mechanisms such as branch prediction [12], cache reuse prediction [13], cache replacement policy [14], and even microarchitectural malware detection [15]. As these works state, the application of a Machine Learning model allows a considerable improvement due to its high precision in recognizing linear and nonlinear patterns, which usually surpass the performance of classical methods. Cache prefetching, closely related to memory address prediction, has also leveraged the potential of Machine Learning. In the last years, some Reinforcement Learning-based prefetchers of relevance have emerged, like Bera et al. [16], Gerogiannis and Torrellas [17], Yang et al. [18] and Huang and Wang [19]. These prefetchers can filter and regulate prefetching through their reward system, which is dependent on measuring real-time, performance-wise information such as memory bandwidth or prefetching timeliness. This approach improves previous state-of-the-art confidence mechanisms. With respect to address prediction, there is a major trend in works that propose Recurrent Neural Networks (RNNs) for temporal localitybased prefetching by leveraging predicting cache accesses or cache misses. Specifically, many Long Short Term Memory (LSTM)-based proposals have been introduced in the last years, such as Zeng and Guo [20], Shi et al. [21], Braun and Litz [22], Ganfure et al. [23]. Some particular examples of interest for this paper are Hashemi et al. [24], Srivastava et al. [25] and Zhang et al. [26], which propose an LSTMbased RNN as the classification model, and where each address delta is predicted as a value associated to a word (class returned by the classifier) and stored in a statically, offline fitted vocabulary/dictionary. This allows this model to considerably reduce its output space. The DCLSTM is one of the main contributions in this regard, which is formed by one Embedding layer, one LSTM layer, and one or two fully connected layers. In order to save up a significant amount of network size, both input and output are dictionary words that are not one-hot encoded but rather encoded in binary numbers. A complex model, like the LSTM-based RNN, enables the predictor to learn all sorts of access patterns, minimizing the possible impact of facing complex contexts, in contrast to the table-based predictor counterpart. However, this comes at the price of having considerable Future Generation Computer Systems 164 (2025) 107592 2 P. Sanchez-Cuevas et al. hardware costs both on the weights matrix that these models usually include and on the set of linear and non-linear operations (required to process context features and intermediate results). Other works, such as Peled et al. [27], approach prediction as a regression problem from contextual program information [28] together with traditional architectural memory information (PC, miss history, and branch history). They use this data to train a neural network to learn the patterns of memory accesses. However, this is an inefficient predictor in terms of both resource and energy consumption [29] due to the area and power requirements implicit in the proposed neural networks. Moreover, whereas applying successful offline learning to this kind of model allows the implementation of a pre-fitted predictor, additional online learning is necessary to adapt the predictor to the local context of a given application and its input data. Here, a disadvantage appears when applying online learning: the more complex a Machine Learning model is (like the case of Deep Learning models), the more difficult and unsuccessful its fitting [30]. There are additional proposals that do not propose a predictor, but rather neural networks that support the current alternatives. Works such as Bhatia et al. [31], which proposes a neural network in charge of filtering the results of the predictor to improve its accuracy, or Rahman et al. [32], which proposes a Machine Learning technique that, based on the features of the code to be executed, searches for the optimal configuration for the predictor. In summary, although RNN-based proposals may achieve high accuracy, they are not currently feasible hardware solutions for predictors due to their large memory consumption, their elevated latency times, and their need for both intense offline and online training to maintain their dynamic learning models [29] with high prediction rates. To counteract these issues, some very recent studies from the field of Neuromorphic Engineering have presented bio-inspired counterparts to the previously mentioned RNN-based works, like in [33,34], where Spiking Neural Networks (SNN) with Hebbian learning rules were used for memory prefetching. Due to the interesting features of this kind of bio-inspired models, which ensure lower latency, memory cost and power consumption [35], it is expected that more studies on this novel methodology appear in the state-of-the-art [36]. From the reviewed related works, we conclude that DFCM and DCLSTM models pursuit the same aim that our proposal, so they have been selected for comparison with ours in Section 6. Note the relevance of DCLSTM since it is the latest contribution in terms of generalpurpose access prediction, whereas the rest of the most recent works do not propose memory access predictors as such, but rather memory prefetchers. For instance, while DCLSTM is a general-purpose predictor with the capability of predicting a wide range of deltas, Pathfinder [34] only uses deltas between −63 and +63 for block prediction inside a memory page. Due to the use of dynamic buffers (the input buffer and the dictionary), our model, the SVM4AP, is able to perform generalpurpose address prediction and can be directly compared to the DFCM and DCLSTM predictors. 3. Memory access patterns As commented in previous sections, predicting memory access addresses is highly related to value prediction. However, it gains a strong differentiation when the patterns on which each technique focuses are analyzed. In fact, it can be said that not only is access prediction one particular case of value prediction (in fact, the same predictors can be applied for both tasks), but it also exploits a range of patterns that make the implementation of access prediction easier [7]. For instance, consider a simple program whose main computation is a simple loop which iterates through two vectors, performing two memory reads and one memory write, like in the case of the wellknown SAXPY loop or in general those benchmarks that solve scientific numerical equations over a surface or space, like SPEC applications roms and cactuBSSN (see Table 2). Although the data loaded from memory in each access is arbitrary and can take any value with neither a clear nor a predictable pattern, a rather different situation occurs for their memory addresses because they have no memory space gaps. On the whole, for scan patterns or similar, the prediction of the accessed addresses is trivial. Moreover, the program sections that follow this trend are often the bottleneck of many of the algorithms executed nowadays, and especially in those of scientific and multimedia applications where vector and matrix operations are prevalent. In such cases, a predictor would achieve optimal performance when the differences between consecutive accessed addresses (called deltas or strides) belong to a small set of possible values. In contrast, memory access patterns take the opposite behavior for algorithms whose data is not placed in memory in a continuous manner but rather randomly distributed. Such is the case of structures like linked lists or graphs among others (see for example SPEC benchmarks mcf or omnetpp in Table 2), whose elements are dynamically allocated by the operative system and, hence, are located across memory space with random gaps. Furthermore, in such algorithms, the accesses to the different elements of these structures are not usually fixed by the code but rather dependent either on a condition which controls one or more branches, or on an input or intermediary value. These kinds of algorithms present the most difficult scenario to predict access addresses. For any of the two main cases here described, one major factor needs to be considered: access space, which is the set of all possible addresses that a program can access, may range from 0to (264 − 1) in 64-bit architectures. Therefore, both the input and output space that the predictor must handle is huge, even for delta/stride predictors. These and other issues are tackled by our predictor proposal as described in Section 5, and its final performance is validated in Section 6. 4. Outlining a new model Our predictor proposal comes from a set of design decisions that are meant to overcome the detected drawbacks of other predictors. The first of these choices was to prevent the use of table-based indexing functions (e.g., similar to those encountered in the DFCM predictor, Goeman et al. [9]) by substituting them with a Machine Learning block. With respect to the memory pattern predictor and learning blocks, it can be observed that only the weight matrix of RNNs incurs a high memory cost (e.g., those from [11,25,26]), in addition to a considerable latency on both inference and retraining. Therefore, a solution based on a linear Support Vector Machine (SVM) was chosen since it features a much lower cost both in memory and latency, and its results are excellent, as shown in the following sections. One major point in the previously referenced Deep Learning-based methods was predicting deltas (differences between consecutive access addresses) by classifying them with a statically fitted dictionary, where each class/word is associated with a delta. Although it enables a much more efficient RNN model due to reducing the output space from any possible delta value to only a few hundred of classes/words, it makes the predictor less dynamic and more constrained by the programs (whose memory accesses are recorded as a dataset) selected for the static model training. Based on this, a dictionary has also been incorporated in our proposal; but with the particular feature of being 100% dynamic: all classes/words are dynamically stored during execution, following a Least Frequently Used (LFU) eviction policy. One remarkable advantage is also achieved: this approach enables a dictionary of much smaller size, focusing on only a few possible deltas that appear during each code zone of the execution. This dictionary plays a similar role to that of the DCFM second table; however, its size can be very much smaller, as shown in Section 6. Another crucial choice of our proposal is that predictions are performed on local history access traces (that is, the sequence of accesses associated with the instruction Program Counter) instead of a global Future Generation Computer Systems 164 (2025) 107592 3 P. Sanchez-Cuevas et al. one. Its main advantage is that this approach does not mix accesses of different instructions so that the predictor would learn every sequence as a pattern attached separately to each instruction. This would result in a more precise prediction. However, a little complication is the need for a cache to store the history (i.e., the access sequences) and the last accessed address for each memory read/write instruction: the herecalled input buffer. This component is similar to the first table of the DFCM predictor since it is also indexed by instruction PC and it outputs a certain feature for the later address prediction. In order to alleviate the memory cost of the input buffer and, more importantly, to improve the predictor’s precision, one final decision has been taken: instead of storing access sequences as deltas between consecutive addresses, sequences of classes (extracted from the dictionary) that correspond to each of the deltas are being stored. In consequence, SVM predictions would be (delta) classes from the history sequence of classes for every instruction. Thanks to this design choice, the input space of the SVM model has been significantly reduced in comparison to those of the referenced RNN proposals. In summary, the prior decisions result in a model that predicts the next delta from a small but currently relevant set (stored in the dictionary), given the sequence of accesses (encoded as classes) of the executed load or store instruction. Using a linear SVM allows a more straightforward fitting to the dynamic inputs and outputs while giving up some longer-term patterns. Thus, our proposal leverages short-term learning, achieving greater cost-effectiveness than the DCLSTM predictor, as depicted in Section 6. The next section details the architecture of the new address predictor, called SVM4AP. 5. Proposed model: SVM4AP In this work, we propose a predictor model that can be considered as a hybrid between the DFCM and an RNN: the SVM4AP predictor. Specifically, it steps forward from the DFCM [9] since the delta/stride indexation via hash codes gets replaced by a SVM. Its components are described as follows (see notation in Table 1): 1. Input buffer. A memory table that stores an entry for each memory read/write instruction containing: (1) the last accessed memory address 𝑎𝑝; and (2) the sequence 𝑞𝑝of delta classes (a.k.a. words) of the last 𝑛𝑞accesses of the instruction. The table is indexed by the Program Counter (PC) 𝑝of the given memory access instruction. It can be implemented as a𝑛𝑤way set associative cache memory with 𝑛𝑠sets in total, where the objective is to allocate the entries of the most commonly executed memory access instructions, also making use of a Least Recently Used (LRU) eviction policy. 2. SVM. A linear Support Vector Machine [37] which takes as input a sequence 𝑞of 𝑛𝑞classes and returns as output a predicted class 𝑐𝑝among the considered, possible 𝑛𝑐classes. The proposed implementation features as many hyperplanes as 𝑛𝑐output classes following aone-to-all classification, and the prediction function for each hyperplane is expressed as: 𝑓(𝑞 , 𝑐) =𝑤𝑐⋅𝑞−𝑏𝑐(1) 𝑝𝑟𝑒𝑑(𝑞 , 𝑐) ={+1 if 𝑓(𝑞 , 𝑐)≥0, −1 otherwise (2) where 𝑤𝑐and 𝑏𝑐are the normal weight vector and the intercept of the 𝑐th hyperplane, respectively. For fitting each hyperplane, given a sample of 𝑞′as input and 𝑦′ 𝑐(which is equal to −1 if 𝑞′ is of class 𝑐or +1 otherwise) as output, a gradient descent can be implemented by the following expressions: 𝑑(𝑞′, 𝑦′ 𝑐, 𝑐) = 1 −𝑦′ 𝑐 ⋅𝑓(𝑞′, 𝑐)(3) ∇𝑤𝑐={0if 𝑑(𝑞′, 𝑦′ 𝑐, 𝑐)≤0, −𝑦′ 𝑐 ⋅𝑞′otherwise (4) Fig. 1. Prediction (a) and fitting (b) phases run by the SVM4AP predictor. Operations performed by each component and their inputs and outputs are also shown, following the short definitions of Table 1. Table 1 Glossary of the main terms of the SVM4AP model. Symbol Definition 𝑝Memory access instruction PC 𝑎𝑝Last accessed address for instr. 𝑝 𝑞𝑝History of last deltas from instr. 𝑝encoded as dictionary classes 𝑐𝑝Predicted class of delta of instr. 𝑝  𝑑𝑝Predicted delta of instr. 𝑝 𝑎𝑝Predicted memory address of instr. 𝑝 𝑎𝑝 ′New memory address of instr. 𝑝 𝑞𝑝 ′New history of last deltas from instr. 𝑝encoded as dictionary classes 𝑐𝑝 ′Class of new delta of instr. 𝑝 𝑑𝑝 ′New delta of instr. 𝑝 ∇𝑏𝑐={0if 𝑑(𝑞′, 𝑦′ 𝑐, 𝑐)≤0, 𝑦′ 𝑐otherwise (5) 𝑤′ 𝑐=𝑤𝑐+𝜂⋅∇𝑤𝑐(6) 𝑏′ 𝑐=𝑏𝑐+𝜂⋅∇𝑏𝑐(7) where ∇𝑤𝑐and ∇𝑏𝑐are the gradients of the normal vector and the intercept of the 𝑐-th hyperplane, respectively, which are multiplied by the learning rate 𝜂in order to obtain the new normal vector 𝑤′ 𝑐and intercept 𝑏′ 𝑐. 3. Dictionary. Another memory table that in this case stores 𝑛𝑐 entries, where 𝑛𝑐is the number of classes that are used in the predictor. Each entry holds (1) a delta 𝑑, which is a stride or difference between two consecutive memory access addresses, and (2) a confidence value 𝑘. Such a table can be implemented with a particular fully associative cache memory of 𝑛𝑐ways, where an entry is accessed either by indexing directly with a given class or by querying the entry (and its corresponding class) which stores the given delta. A Least Frequently Used (LFU) eviction policy is applied by making use of the confidence 𝑘 of each entry, which is incremented on fetching the entry and decremented on fetching another entry. The precise functioning of the predictor and how the components communicate with each other is explained in two phases: the prediction pipeline and the fitting pipeline, as portrayed in Fig. 1. These two parts are described below: (a) The prediction phase receives a new PC 𝑝of a memory access instruction as input of the predictor. This PC is employed as Future Generation Computer Systems 164 (2025) 107592 4 P. Sanchez-Cuevas et al. an index to the input buffer, from which both a base address 𝑎𝑝(indeed, the last accessed memory address) and the class sequence 𝑞𝑝= [𝑞𝑝(0),…, 𝑞𝑝(𝑛𝑞− 1)] are read. The sequence is inputted in the linear SVM, which outputs a predicted class 𝑐𝑝. This class is then used to index the dictionary from which the resulting delta  𝑑𝑝is read. The final predicted memory address equals the sum of the base address and the delta: 𝑎𝑝=𝑎𝑝+ 𝑑𝑝. If there was a miss during the fetch of the input buffer entry, no prediction is performed. (b) The fitting phase responds to an opposite situation: the currently accessed memory address 𝑎𝑝′is given by the processor in addition to its corresponding PC 𝑝. Therefore, the input buffer is accessed using 𝑝as an index. Two cases appear: (1) If the entry is stored in the input buffer (hit), a new delta is computed as the difference between the current memory address and the last one stored in this entry: 𝑑𝑝′=𝑎𝑝′−𝑎𝑝; (2) If the entry cannot be fetched from the input buffer (miss), the new delta will be 𝑑𝑝′= 0. Thus, for any of the two cases, the new delta is used for fetching (by query) the dictionary, from which the other two cases appear: (1) If the fetch hits the dictionary, having 𝑐𝑝′as the class of the fetched entry, its confidence is summed by a confidence jump value (which can be seen as a reward): 𝑘(𝑐𝑝′)←𝑘(𝑐𝑝′) +𝐽; (2) If the fetch misses, a new entry 𝑑𝑝′is written in the dictionary, which is assigned a class value 𝑐𝑝′and an initial confidence value equal to half of the maximum 1 2𝑘𝑚𝑎𝑥. The confidence of the rest of the entries is decremented by one. Once the class 𝑐𝑝′has been mapped to the current new delta 𝑑𝑝′, a new class sequence can be formed and stored in the input buffer. Specifically, in the case where there was a hit previously in the input buffer, the new class gets pushed into the previous class sequence, which is then stored in the corresponding entry of the input buffer, the new sequence being equal to 𝑞𝑝′= [𝑞𝑝(1),…, 𝑞𝑝(𝑛𝑞− 1), 𝑐𝑝′]. On the contrary, on a previous input buffer miss, a new entry needs to be allocated in the input buffer, where the sequence is set to 𝑞𝑝′= [𝑛𝑐,…, 𝑛𝑐, 𝑐𝑝′]. Additionally, either on an input buffer hit or a miss, the current address 𝑎𝑝′is written as the last accessed address. Finally, if the prediction for PC 𝑝prior to this fitting phase missed, i.e. computed an address 𝑎𝑝different from the true target one 𝑎𝑝′, a fit is performed in the SVM. The model is adjusted with one sample where the input is equal to the old class sequence 𝑞𝑝 and the output is actually the new dictionary class 𝑐𝑝′. In summary, our proposal can be viewed as a mix between referenced DFCM and Machine Learning-based predictors, including a whole set of optimizations with the objective of minimizing costs and maximizing precision. In fact, these modifications aim to focus the SVM4AP on local-context, high learning rate fittings in which the predictor greedily learns patterns that will rapidly be evicted by other patterns, in line with the dynamic nature of the memory access patterns of a program. Indeed, this approach has finally been successful, as the results discussed in Section 6show. 6. Experimentation In this section, experimental results are presented and their discussion is included. The effectiveness of the SVM4AP model is validated for the prediction of memory addresses accessed in real applications of the SPEC benchmark [38], showing detailed comparisons between baseline predictors and the proposed implementation. 6.1. Experimental setup The experimentation process consists of a two-step pipeline: first, memory access addresses are recorded by instrumenting a group of applications, and then the recorded accesses are used as a dataset for the predictor models. The first step is accomplished using Intel Pin [39] to instrument the execution of the SPEC 2017 benchmarks. The program counter (PC) and the memory address of each memory access instruction executed in a real CPU are recorded. The output of this process will depend on the virtual memory mapping assigned by the operating system. In our case, this step is carried out on an Intel Core i7-10750H laptop (2.60 GHz, 6 cores, 6×32 kB data caches, Level 2 cache size 6×256 kB, Level 3 cache size 12 MB) using Ubuntu 18.04. The second step is programmed as a C++ project and uploaded to GitHub1in order to publish an early, standalone experimentation tool which can be expanded for future models and benchmarks. The software encapsulates all predictor models (with the exception of DCLSTM, whose source code comes from its original repository2) and simulation tasks that emulate the behavior of real predictors. The output of these tasks is not host-dependent, and thus no environmental information is relevant for it. 6.2. Dataset building method A closer look at the first step of the experimentation process reveals that this task is not computationally trivial because of the huge amount of memory access instructions that are executed during the run of a SPEC application. Table 2shows the applications selected for experimentation in this work, their SPEC type classified between integer (INT) or floating point (FP), and their corresponding number of memory accesses. This number ranges from 5.40 × 109to 1.974 × 1012 instructions, covering a total amount of 7.72 × 1012 accesses. Building such a dataset of 7.7 × 1012 accesses is not practical in both storage and subsequent processing time. To tackle this major restriction, we have implemented an easy but fair workload selection model in order to both reduce significantly the number of accesses and to cover uniformly the original enormous workload. Note that we refer to workload as the amount of memory accesses that are sampled from an instrumentation tool of the corresponding programs. For each SPEC application, instrumentation is performed and a trace of 𝑀= 109accesses in total is extracted, and for each access (1) the instruction PC, (2) a bit indicating whether the access has been a read or a write, and (3) the virtual memory address are stored. Such an amount of samples results in a trace file of nearly 30 GB. To evenly represent the overall access patterns of each target application, a uniform distribution has been chosen, that is, a total of 𝑔= 1000 groups have been recorded, each containing 𝑚= 106accesses. These groups are separated between them by a distance of 𝐷accesses. Additionally, both at the start and at the end of the complete trace, a sequence of 𝑃 accesses is left unrecorded, considered as padding. For a program that has a total sequence of 𝑁accesses, these last two distances 𝐷and 𝑃 can be calculated using the following equations: 𝐷=⌊𝑁−𝑀 𝑔+ 1⌋,(8) 𝑃=⌊(𝑁−𝑀) −𝐷× (𝑔− 1) 2⌋(9) A simple example of a distribution following this model for a program execution with 𝑁= 1000 memory accesses in total, 𝑀= 300 accesses per group, and 𝑔= 5groups can be seen in Fig. 2. Note that this method is not a random sampling but a partition of the memory access trace following the execution order. One interesting aspect of having accesses in separated trace groups is that it can roughly reproduce the behavior of CPU process context 1https://github.com/Hematies/PredicMem23. 2https://github.com/MemMAP/MemMAP. Future Generation Computer Systems 164 (2025) 107592 5 P. Sanchez-Cuevas et al. Table 2 Memory access statistics. SPEC application Type Application area Memory access instructions’ count (109instr.) perlbench INT Perl interpreter 300.2 gcc INT GNU C compiler 229.6 mcf INT Route planning and scheduling 623.9 lbm FP Fluid dynamics 1974.0 omnetpp INT Discrete Event simulation 451.5 xalancbmk INT XML to HTML conversion 490.7 x264 INT Video compression 482.5 deepsjeng INT Alpha–beta tree search (Chess) 732.6 exchange2 INT Recursive solution generator (Sudoku) 1393.3 leela INT Monte Carlo tree search (Go) 623.4 roms FP Regional ocean modeling 5.4 cactuBSSN FP Physics: relativity 387.5 Fig. 2. Example of access distribution for a program with 𝑁= 1000 accesses in total. The access groups, the separation between them and the boundary paddings are portrayed in blue, black and gray blocks resp. switching. That is, each sequence of 𝑚accesses may be perceived as the memory accesses that take place between the process allocation on the CPU and its subsequent eviction, which are performed by the operating system scheduler. This consideration will be significant in the next subsection since this behavior is assumed to happen, and thus the predictor and its online parameters will be reset in each trace group change. Whereas this dataset recording method allows a much less expensive approximation to the trace extraction both in time and storage costs, it must be clarified that the whole process still requires many hours of execution and returns hundreds of gigabytes of data. While our method is fair and simulates process switches, there are other alternative dataset-building methods in the current literature [40–42] that alleviate the cost. For example, each SPEC application trace can be sampled following previously tuned checkpoints [43]. Then, for each checkpoint, a weight can be provided as a significance metric: the higher the value, the more importance is given to the sequence of accesses present in the checkpoint. Another interesting and heterodox procedure is described in [6], where the trace is generated based on statistical metrics in order to accurately characterize the burstiness of memory access behaviors. Due to experimentation costs, a full comparison between our fair method and the previously mentioned ones is left for future work. 6.3. Search of feasible SVM4AP predictors Although the proposed SVM4AP can almost reach the best-known performance where memory is considered to be infinite (see Section 6.4), predictors should rely rather on optimizing cost-effectiveness in realistic scenarios. Since the two tables of the SVM4AP predictor play a significant role in the final hit rate, here we explore and test different, realizable configurations for these tables. The input buffer is implemented (see Section 5) as an 𝑛𝑤-way set associative memory cache accessed via instruction PC that returns an entry with the corresponding last memory address and a𝑛𝑞-length class/word sequence. In addition, the dictionary consists of a memory of 𝑛𝑐classes, each corresponding to an Table 3 Input buffer memory cost for different configurations (in bytes). 4-length seq. 8-length seq. 2 ways 4 ways 2 ways 4 ways 4 classes 128 sets 4288 8576 4672 9344 256 sets 8512 17 024 9280 18 560 1024 sets 33 536 67 072 36 608 73 216 8 classes 128 sets 4416 8832 4928 9856 256 sets 8768 17 536 9792 19 584 1024 sets 34 560 69 120 38 656 77 312 Table 4 Input buffer miss rate for different configurations and benchmarks. cactuBSSN mcf perlbench 2 ways 4 ways 2 ways 4 ways 2 ways 4 ways 128 sets 0.9101 0.8705 0.0150 0.0017 0.7124 0.3812 256 sets 0.8640 0.7489 0.0036 0.0004 0.4481 0.1360 1024 sets 0.5299 0.1832 0.0004 0.0003 0.0807 0.0159 entry that stores the corresponding delta or stride. This dictionary can be indexed by a class value or queried by a delta value (see Section 5). A complete search on the configuration space would require a very long experimentation run time because a total of 109accesses must be simulated for each predictor configuration per each selected SPEC application. Thus, only a small but representative subset of values was chosen for the exploration of the different SVM4AP results according to a double criterion: covering values that produce realizable hardware implementations and spanning a broad dissimilarity between them. The selected configuration values are the following: 𝑛𝑠∈ {128,256,1024}, 𝑛𝑤∈ {2,4}, 𝑛𝑞∈ {4,8}, 𝑛𝑐∈ {4,8} where 𝑛𝑠and 𝑛𝑤are the number of sets and ways of the input buffer respectively, and 𝑛𝑞and 𝑛𝑐are the number of classes/words in each input sequence and the dictionary respectively. A similar heuristic of trying to minimize experimentation cost while maximizing dissimilarity was followed when selecting the tested applications. Thus, three applications representing the best, worst and middle case scenarios were chosen: cactuBSSN,mcf and perlbench. Results are organized into three sets of tables: •Input buffer. Table 3shows the memory costs for each of the explored input buffer configurations, while Table 4lists the input buffer miss rates for them and for the three selected applications. •Dictionary. Table 5includes the dictionary miss rates for the two proposed numbers of classes and the selected applications with the corresponding memory cost for each configuration. Future Generation Computer Systems 164 (2025) 107592 6 P. Sanchez-Cuevas et al. Table 5 Dictionary miss rate for different configurations (first 3 columns), and their corresponding memory cost in bytes (last column). cactuBSSN mcf perlbench 4 classes 0.0027 ± 0.0004 0.269 ± 0.004 0.074 ± 0.008 37 bytes 8 classes 0.0022 ± 0.0004 0.199 ± 0.003 0.067 ± 0.006 75 bytes Table 6 SVM memory capacity for different configurations (in bytes). 4 classes 8 classes 4-length seq. 80 160 8-length seq. 144 288 •SVM model. Table 6shows the memory costs of the model weight matrix for each of the configurations explored, whereas Table 7 summarizes the model precision for the different configurations and for the three selected applications. Notice that the dictionary’s hit rate is computed as the hit rate of that component just when the input buffer hits. In the same direction, the model’s hit rate is computed as the hit rate when both the input buffer and the dictionary hit. Therefore, the predictor’s final hit rate is equal to the product of the three hit rates. It is worth noting that the input buffer represents the critical component in terms of memory because the memory size of the model implementation and the dictionary are negligible (see Tables 3,5and 6). Thus, the memory capacity of the predictor should be fitted straightly through the input buffer. Furthermore, in turn, the input buffer is configured to meet one objective: minimizing its own miss rate by tuning its cache configuration. Nevertheless, it has to be remarked that the fitting of both the dictionary and the SVM model affects the input buffer’s memory cost indirectly via two parameters: the sequence length and the number of classes. Hence, this interdependence among the components of the system entails a trade-off between the memory cost and hit rate of the predictor. The input buffer miss rate is highly dependent on the total number of input buffer entries for two of the analyzed benchmarks (cactuBSSN and perlbench). Specifically, doubling the number of ways produces a considerable improvement in the input buffer hit rate. This effect indicates that memory accesses to instruction PCs tend to collide in the same cache sets, which can be due to access sparsity or non-alignment. The dictionary miss rate supposes an important factor only for the mcf application, mainly because its graph computation involves dispersed accesses across its memory space. Doubling the size of the dictionary (by doubling the number of classes) partially alleviates this effect. Finally, the precision of the SVM model when both the input buffer and the dictionary hit tends to be maximum when 4 classes are implemented. However, this precision is adjusted to those cases where both the input buffer and the dictionary hit. As portrayed in Table 5, implementing 4 classes leads to a smaller dictionary that results in a lower hit rate. This trade-off is reviewed later in Section 6.4. On the other hand, except for the case of mcf, no clear difference in the SVM hit rate is drawn when comparing sequence lengths of 4 or 8. Having evaluated the results of the exploration of the configurations space, two configurations of the SVM4AP 𝑛𝑞-𝑛𝑐are highlighted among the rest: SVM4AP 4-4 and SVM4AP 8-8. Specifically and according to the previous discussion, the SVM4AP candidates are composed of: (1) a 4-way associative input buffer which stores 1024 sets with entries containing class sequences of length 4 and 8 respectively, and (2) a dictionary of 4 and 8 classes in total respectively, each having total confidence of 256 and confidence jumps of 8. The decision to focus on zipping the sequence length and the number of dictionary classes as 𝑛𝑞=𝑛𝑐allows the building of a configuration space where the scale of complexity of the SVM model can be easily tuned and analyzed. The prior exploration of the configuration space delivered insights into the SVM4AP’s behavior, its relation with features such as input buffer size, and two a priori proposed appropriate solutions. In Section 6.4 a final configuration space is covered to test different locally optimal SVM4AP configurations, forming an extension of the previously covered configurations while selecting the parameters patterns that yield better results. 6.4. Results and discussion Following a quantitative measure of the overall performance and cost-effectiveness of the presented SVM4AP, the use of state-of-the-art predictors for comparison is proposed. Specifically, the DFCM and the DCLSTM were selected. In the case of the DFCM, implementations have been carried out for two different variants described in detail in [44,45], which are labeled here as follows: •HashOnHash: The new hash value is computed as the hash as a combination of the previous hash value and the resulting delta (the difference between the current address and the previous one). •K-Order: The resulting delta is pushed into a sequence of 𝐾deltas stored in the accessed entry of the first table. Then, the hash value is computed as the hash of the 𝐾deltas stored in this entry. DFCM, like other table-based predictors, achieves better precision the greater the capacity of its two tables. Indeed, in a simulation environment, an ideal DFCM predictor whose tables contain an infinite number of entries (via an implementation using dynamic memory with hash-maps, for example) can be evaluated. Furthermore, in this case, having limitless tables gains relevance since its predictions are based on storing all possible prediction solutions for all possible contexts. Here, an analog approach is brought to the fore when implementing the SVM4AP: its configuration space allows multiple implementations with different outcomes in the range of cost-effectiveness. For example, as seen in Section 6.3, the prediction hit rate is highly dependent on the hit rate achieved by both the input buffer and the dictionary, which in turn is directly affected by the size of those tables. An ideal SVM4AP predictor can be implemented by having an infinite input buffer while, in contrast to the DFCM, the rest of the elements (the SVM model and the dictionary) remain with a fixed size. This is due to the static nature of an SVM model, whose input and output sizes, of course, cannot vary dynamically. Therefore, the performance of SVM4AP with Matching Learning inference is more limited to realistic configurations than a table-based brute force mapping DFCM predictor that can be extended to an ideal scenario with better results, as shown in Section 6.4.4. In the case of DCLSTM, we have directly reproduced the ideal experimental procedure of the model from [25]: training and testing a different DCLSTM predictor for each trace. That is, for each SPEC application, a predictor is set to learn only the memory access patterns intrinsic to it. Note that this testing mode greatly benefits this predictor. It is noteworthy that the DCLSTM’s results are obtained after a data split between training and test sets (as common in Deep Learning pipelines), which also leaves more skew towards the DCLSTM model. Conversely, SVM4AP’s results come from the on-line learning across the whole trace without any testing phase nor split selection. The goal of this experimentation heuristic is to give a straight comparison between a best-case, Deep Learning implementation and our Machine Learning proposal. Besides, there are other more realistic and practical NN implementations (using a meta-model built upon different specialized DCLSTMs and fitted via online retraining, see [46]), which would deliver even worse results than the specialized, trained models used here. Future Generation Computer Systems 164 (2025) 107592 7 P. Sanchez-Cuevas et al. Table 7 SVM’s hit rate for different input and output sizes. cactuBSSN mcf perlbench 4 classes 8 classes 4 classes 8 classes 4 classes 8 classes 4-length seq. 0.962 ± 0.025 0.953 ± 0.033 0.802 ± 0.004 0.773 ± 0.002 0.861 ± 0.105 0.860 ± 0.109 8-length seq. 0.962 ± 0.026 0.953 ± 0.034 0.818 ± 0.005 0.777 ± 0.004 0.858 ± 0.106 0.856 ± 0.111 Overall, the different feasible configurations shown in Tables 8, 9,10 and described in Section 6.4.2 (the latter specifically for the DCLSTM) are simulated, given the SPEC traces collected by our extraction model from Section 6.2. Note that the configurations taken for SVM4AP is an expanded set from the configuration heuristic reviewed in Section 6.3. The prediction results and memory costs are also summarized in those tables. To illustrate accurately the characteristics of the results given by such amount of implementations, we divide the discussion into four subsections featuring (1) those results given by HashOnHash and KOrder predictors, (2) the results returned by the DCLSTM predictor, (3) the ones given by the SVM4AP predictor, and (4) the final comparison among the all of them. 6.4.1. DFCM results The configurations for both HashOnHash and K-Order variants have been selected first according to the DFCM’s first table (i.e. VHT). Since its functionality is almost the same as the input buffer of SVM4AP, its configuration space follows a similar pattern. Conversely, DFCM’s second table (i.e. VPT), which stores deltas by indexing hash values, is set inside a small configuration subset since final prediction hit rate does not vary much when increasing its size. In the particular case of K-order DFCM, the sequence length 𝐾has been adjusted to just two different sequences, one short and one long. As such, DFCM tables have been simulated as cache memories and the values belonging to their configuration set are: 𝑛𝑠,1∈ {128,256,512,1024}, 𝑛𝑤,1∈ {6}, 𝑛𝑠,2∈ {128,256}, 𝑛𝑤,2∈ {2,4}, 𝐾∈ {4,8}, where 𝑛𝑠,1,𝑛𝑠,2are the number of sets contained in the first and second tables respectively, 𝑛𝑤,1and 𝑛𝑤,2are the number of ways contained in the first and second tables respectively, and 𝐾is the sequence length of deltas in the case of aK-Order DFCM. The DFCM predictors are labeled as the following manner: •‘‘DFCM HoH 𝑏1-𝑛𝑤,1-𝑏2-𝑛𝑤,2’’, which stands for aHashOnHash DFCM whose first table contains 𝑛𝑠,1= 2𝑏1sets and 𝑛𝑤,1ways, and whose second table contains 𝑛𝑠,2= 2𝑏2sets and 𝑛𝑤,2ways, respectively. 𝑏1and 𝑏2are the index bits of each table. •‘‘DFCM K-order 𝐾-𝑏1-𝑛𝑤,1-𝑏2-𝑛𝑤,2’’, which stands for a K-order DFCM that stores sequences of 𝐾deltas, and the same table sets and ways configuration as explained for the ‘‘DFCM HoH’’. The mean hit rates and standard deviations among all SPEC applications for the HashOnHash and K-Order predictors are shown in Tables 8, 9, in addition to the memory capacity needed for such implementations. The aforementioned direct relation between performance and memory cost can be observed, as larger predictors deliver better prediction results for both DFCM variants. Of course, an ideal DFCM with tables of infinite size delivers the best possible hit rate. Moreover, HashOnHash is clearly better in cost-effectiveness than its counterpart, which delivers poorer results while requiring a larger memory budget. For example, the best hit rate achieved by K-Order reaches 74.5 ± 14.6%, and requires a total of 432.06 kB, while the best hit rate of aHashOnHash predictor is 82.1 ± 9.7% occupying 151.5 kB. Regarding the behavior of the best HashOnHash (the ‘‘DCFM HoH 10-6-8-4’’) and the best K-Order (‘‘DCFM K-Order 8-10-6-7-4’’) in terms of hit rate with respect to the different SPEC applications, Figs. 3and Fig. 3. Hit rate of the best explored configuration of the HashOnHash DFCM with respect to the SPEC applications. Fig. 4. Hit rate of the best explored configuration of the K-Order DFCM with respect to the SPEC applications. 4decompose the hit rates of the two tables plus the final prediction hit rate. It can be observed how the first table with such configurations is able to avoid almost all misses, and hence the predictor’s precision is highly dependent only on the second table’s hit rate and the overall match between the correct memory addresses and the ones which are computed from the stored deltas. This is the point of difference between the two variants: both present good second table’s hit rates, but while final hit rates of the HashOnHash approach that of the second table’s hit rate, the final prediction stored by the K-Order matches in fewer occasions with the correct memory address. Such a result is due to the mapping function from the K-Order variant, less able to compute contexts related to correct deltas in the second table. Focusing on the results of the best HashOnHash, it can be noted how discrete computation applications such as mcf, or omnetpp suppose datadependent memory address patterns, where address deltas appear so dispersed that their contexts (encoded as hash values) do not usually hit when accessing the second table. Future Generation Computer Systems 164 (2025) 107592 8 P. Sanchez-Cuevas et al. Table 8 Configurations of the DFCM HashOnHash predictor with their hit rate and total memory cost. Label First table Second table Summary 𝑛𝑠,1𝑛𝑤,1𝑛𝑠,2𝑛𝑤,2Hit rate Memory cost DFCM HoH 7-6-7-4 128 6 128 4 0.632 ± 0.208 24.91 kB DFCM HoH 8-6-7-2 256 ... 128 2 0.688 ± 0.183 38.28 kB DFCM HoH 8-6-7-4 256 128 4 0.704 ± 0.180 42.06 kB DFCM HoH 8-6-8-4 256 256 4 0.712 ± 0.180 49.5kB DFCM HoH 9-6-7-2 512 128 2 0.754 ± 0.125 72.41 kB DFCM HoH 9-6-7-4 512 128 4 0.771 ± 0.118 76.19 kB DFCM HoH 9-6-8-4 512 256 4 0.779 ± 0.115 83.63 kB DFCM HoH 10-6-7-2 1024 128 2 0.799 ± 0.106 140.28 kB DFCM HoH 10-6-7-4 1024 ... 128 4 0.814 ± 0.099 144.06 kB DFCM HoH 10-6-8-4 1024 6 256 4 0.821 ± 0.097 151.5kB Infinite DFCM HoH ∞1∞10.851 ± 0.092 ∞ Table 9 Configurations of the K-Order predictor with their hit rate and total memory cost. Label First table Second table Summary 𝑛𝑠,1𝑛𝑤,1𝐾 𝑛𝑠,2𝑛𝑤,2Hit rate Memory cost DFCM K-Order 4-7-6-7-2 128 6 4 128 2 0.599 ± 0.210 33.13 kB DFCM K-Order 4-7-6-7-4 128 ... 4 ... 4 0.605 ± 0.209 36.91 kB DFCM K-Order 8-7-6-7-2 128 8 2 0.589 ± 0.226 57.13 kB DFCM K-Order 8-7-6-7-4 128 8 4 0.598 ± 0.224 60.91 kB DFCM K-Order 4-8-6-7-2 256 4 2 0.659 ± 0.191 62.28 kB DFCM K-Order 4-8-6-7-4 256 4 4 0.664 ± 0.191 66.06 kB DFCM K-Order 8-8-6-7-2 256 8 2 0.653 ± 0.206 110.28 kB DFCM K-Order 8-8-6-7-4 256 8 4 0.661 ± 0.204 114.06 kB DFCM K-Order 4-9-6-7-2 512 4 2 0.707 ± 0.153 120.41 kB DFCM K-Order 4-9-6-7-4 512 4 4 0.713 ± 0.152 124.19 kB DFCM K-Order 8-9-6-7-2 512 8 2 0.705 ± 0.163 216.41 kB DFCM K-Order 8-9-6-7-4 512 8 4 0.713 ± 0.161 220.19 kB DFCM K-Order 4-10-6-7-2 1024 4 2 0.735 ± 0.142 236.28 kB DFCM K-Order 4-10-6-7-4 1024 4 4 0.741 ± 0.141 240.06 kB DFCM K-Order 8-10-6-7-2 1024 ... 8 ... 2 0.737 ± 0.148 428.28 kB DFCM K-Order 8-10-6-7-4 1024 6 8 128 4 0.745 ± 0.146 432.06 kB Fig. 5. DCLSTM and selected SVM4AP hit rates for the training and test splits (50/50%) of the first 5⋅106trace accesses. 6.4.2. DCLSTM results With the objective of testing the DCLSTM predictor model, a subset of our obtained SPEC traces (from Section 6.2) is here employed as dataset. The experiment comprehends the first 5⋅106memory accesses of each collected trace, an amount that has been shown to be enough for training and testing (see [25]). Here, for each trace, an instance of the DCLSTM model is trained using the first 50% accesses and later tested with the last 50% chunk of the trace. Similarly to Srivastava et al. [25], the training comprises 20 epochs and a batch size of 256, where the input is a sequence of the last three deltas. These deltas, nonetheless, are encoded in binary as classes/words inside a216-size dictionary, which is fitted offline by selecting the top frequent deltas in the trace. Concerning the network structure of the DCLSTM, it includes: (1) an embedding layer with an output size of 10, (2) a LSTM layer with 50 units, (3) a 10% dropout, and (4) a 16-width dense layer using the sigmoid activation function. The loss function applied is binary cross-entropy. Training and testing hit rates are illustrated in Fig. 5. For a clearer comparison, this figure also displays the corresponding outcomes for the SVM4AP with online learning separately for the same two trace splits. To establish this SVM4AP as a reference for comparison as baseline, it is configured as one of the locally optimal implementations outlined in Section 6.3, featuring an input buffer of 1024 sets and 4 ways, 8-length input sequences, and a dictionary with 8 classes. As depicted in Fig. 5, DCLSTM hit rates are significantly lower than those of its SVM4AP counterpart on all traces, encompassing both training and testing splits, with the sole exception of the deepsjeng trace. The latter case is attributed to its trivial accesses, which are requested from the same memory instruction with a constant delta of 1 in almost most cases. In addition to this, there is a clear contrast, highlighted by the mean hit rates of the two models: 0.485 ± 0.216% and 0.476 ± 0.210% for DCLSTM in the training and test splits, respectively; against a much superior 0.784 ± 0.195% and 0.786 ± 0.194% for SVM4AP (also for the training and test splits, respectively). Although a complex model such as an RNN should have the means to learn a wide range of memory address patterns, the design approach and hypothesis defined in Section 4for our simpler proposal are validated, including the focus on short-term learning as opposed to the long-term learning that LSTM-based models are able to accomplish. The SVM4AP exploits characteristics that suppose a proper improvement from state-of-the-art, Deep Learning-based prediction models in terms of precision. Furthermore, the DCLSTM predictor and related models introduce a significant constraint: memory cost. DCLSTM has a relatively modest Future Generation Computer Systems 164 (2025) 107592 9