A 14-bit 4-MS/s Multi-bit Cascade Sigma-Delta Modulator in CMOS 0.35-um Digital Technology

A 14-bit 4-MS/s Multi-bit Cascade Σ∆ Modulator in CMOS 0.35-µm Digital Technology R. del Río, F. Medeiro, J. M. de la Rosa, B. Pérez-Verdú, and A. Rodríguez-Vázquez Instituto de Microelectrónica de Sevilla − CNM-CSIC Edificio CICA-CNM, C/Tarfia s/n, 41012Sevilla, SPAIN Phone: +34 95 5056666, Fax: +34 95 5056686, E-mail: [email protected] Abstract This paper presents a 4th-order 3-stage cascade Σ∆ modulator that achieves 14-bit dynamic range at 4MS/s using low oversampling ratio. It includes a programmable multi-bit quantizer in the last stage, providing 2-, 3-, or 4-bit internal resolution. The modulator is implemented with fully-differential switched capacitor circuits in a CMOS 0.35-µm digital technology. The estimated power consumption is 78mW, from a 3.3-V supply. 1. Introduction Cascade Σ∆ modulators (Σ∆Ms) are being successfully employed for high-speed, high-resolution A/D conversion in xDSL applications [1]-[4]. These architectures perform a high-order filtering by cascading low-order (1stand 2nd-) Σ∆Ms to guarantee unconditional stability. Moreover, the use of multi-bit quantization at the last stage of the cascade reduces the oversampling ratio required for a given modulator resolution. These modulators also exhibit low sensitivity to the DAC non-linearities [5], so that neither correction nor calibration are required. This makes cascade multi-bit Σ∆Ms good candidates to achieve high performance with a reduced power consumption. This paper presents the design of a Σ∆M using a 4th-order 3-stage cascade multi-bit architecture −the 2-12mb modulator [1] shown in Fig.1. A detailed discussion on the benefits of the selected topology, as well as on the selection of integrator weights (summarized in Table 1) can be found in [6] [7]. The modulator presented here can operate with different oversampling ratio Mand last-stage quantizer resolution B: • , and , , providing 13bit@4MS/s, • , , providing 14bit@2MS/s, and • , , achieving 14bit@4MS/s. These M,Balternatives have been implemented together including programmability in the last-stage quantizer, whose resolution can be set to 2, 3, or 4bit. Such performance places this modulator in the state-of-the-art on high-resolution, high-speed Σ∆Ms [1]-[5], especially considering its implementation in a CMOS digital process, unlike the former ones. The paper is organized as follows. Section 2 covers the synthesis of the 2-12mb modulator. Sections 3 to 7 describe the design of the modulator building blocks. Finally, Section 8 is dedicated to layout and prototyping considerations. 2. Modulator Sizing The evaluation of the circuit requirements for the 2-12mb Σ∆M has been done using SDOPT [8], a sizing tool for SC Σ∆Ms. This tool combines accurate analytical expressions for each error contribution degrading the modulator performance and statistical optimization, which allows us to find optimized, non-oversized specifications for the building blocks. Table 2 summarizes the circuit requirements providing 14bit@4MS/s. Most significant error contributions are also shown. Note that quantization noise is the main in-band error source (-85dB). This includes the effect of integrator leakage and weights mismatch. Both non-idealities cause incomplete cancellation of the quantization error in the first and second stages [8], which may degrade the modulator performance. According to SDOPT results, this limits the minimum amplifier DC-gain to 68dB and the maximum standard deviation in capacitors to 0.12%. The unitary capacitor value (0.5pF) is set according to thermal noise and dynamic considerations. Both error powers are well below the limit imposed by the modulator resolution. The requirements in Table 2 for the integrator and the M12= B4= M16= B2= M16= B3= M16= B4= Fig. 1:Block diagram of the 2-12mb Σ∆M. Y1 XE1 g2 -g2' g1 -g1' DAC g3 g3' g3'' - -Y2 E2 DAC H1(z) + + d1 d0 - g4 g4' g4'' - -Y3 E3 d3+Y + d2 ADC B-bit DAC B-bit B B ED H2(z) H3(z) H4(z) - Cancellation Logic This work has been partially supported by the ESPRIT Project 29261 and the CICYT Project TIC 97-0580. amplifier apply only to the first integrator in the cascade. However, some specifications, as amplifier DC-gain, transconductance and output current, can be relaxed for the second, third, and fourth integrator, because their in-band error power contributions are attenuated by increasing powers of M. The same applies for thermal noise, which allows reduction of the unitary capacitor to 0.25pF for these integrators. Fig.2 shows the fully-differential SC implementation of the 2-12mb Σ∆M. The first stage is formed by two SC integrators, with one and two input branches, respectively. A single-bit quantizer (comparator) at the end of the first stage, together with two AND gates, provides the feedback signals A1,B1to switch the integrator sampling capacitors to either Vr+ = +1V or Vr- = -1V. Since the circuit is fully differential, the resulting reference voltages are . The second stage has a two-branch integrator. Although three different weights are needed in this integrator −,, and −weight in Table 1 allows splitting of between the two branches. The same applies for weight in the fourth integrator. This integrator drives the programmable ADC and the third-stage loop is closed through the DAC. The 1-of-16 output code of the ADC (alternatively 1-of-8 if or 1-of-4 if ) is converted to binary code using a ROM memory, providing outputs Y3,0-3 (Y3,0-2 if or Y3,0-1 if ). The modulator is controlled by two non-overlapped clock-phases. The integrator input signals are sampled during phase φ1and the algebraic operations are performed during φ2. The comparators and the ADC are activated at the end of φ2−using φ2as strobe −to avoid any possible interference from the integrator outputs in the beginning of φ1. This timing guarantees a single delay per clock-cycle. In order to attenuate the signal-dependent clock-feedthrough, delayed versions of the phases, φ1d and φ2d, are also provided. The modulator has been extensively evaluated in ASIDES [8], a behavioural simulation tool for Σ∆Ms. Simulations have been carried out including the non-idealities derived from the final implementation of the building blocks. Fig.3(a) shows the signal-to-(noise+distortion)-ratio SNDR of the modula- - + + - - + + - 0.5p 0.5p 2p 0.5p + - Xφ1d φ1 φ1 φ2 φ1dφ2φ2 φ1d - + + - 0.25p 0.5p φ2d φ1d φ1 φ1 φ2 φ1dφ1 φ2d φ2 φ1dφ1φ2 φ1d φ1 φ2 φ1 φ2d φ1d φ1 φ2 φ2 φ2d 0.25p 0.25p φ1d φ1 φ2 φ2d ADC φ2 2p 0.25p 0.5p 0.25p 0.25p 0.5p 0.25p 0.25p 0.25p 0.25p Fig. 2:SC implementation of the 2-12mb Σ∆M. Y1 Y1 φ1 φ2 0.25p Vr+ VrVr+ VrVrVr+VrVr+ Y2 Y2 VrVr+ Vr+VrVr-Vr+Vr+ Vrφ1d φ1 0.25p φ1 φ2 0.25p VrVr+ VrVr+ B2 A2 B2 A2 B1 A1 B1 A1 B2 A2 B2 A2 B1 A1 B1 A1 B1 A1 B1 A1 B1 A1 B2 A2 vD/A+ 0.25p φ1d φ1 φ2 φ2dvD/AvD/A+ vD/AVrVr+ d0-15 d0-7 d0-3 OA1 OA2 OA3 Y3,0-3 Y3,0-2 Y3,0-1 ROM Table 2: Modulator sizing results. SPECS: 14bit@4MS/[email protected]p2-12mb Modulator Oversampling ratio 16 Sampling frequency 64MHz Reference voltages Integrators Sampling capacitor 0.5pF Unitary capacitor 0.5pF Sigma 0.12% Capacitor non-linearity ≤25ppm/V Bottom parasitic capacitor 20% Switch ON-resistance ≤250Ω Opamps DC-gain 68dB DC-gain non-linearity ≤20%V-2 Transconductance ≥2.5mA/V Maximum output current ≥ Output swing ≥ Comparators Hysteresis ≤30mV A/D/A Converter Resolution 4bit Non-linearity (INL)≤0.4%FS Dynamic range 87.2dB 14.2bit Quantization noise -85.0dB Thermal noise -94.8dB Incomplete settling noise -96.9dB Harmonic distortion -99.4dB 2V± 0.95mA± 2V± DAC - + + - OA4 Table 1: Integrator weights for the 2-12mb Σ∆M. g10.25 g31g42 g1’0.25 g3’0.5 g4’1 g21g3’’ 0.5 g4’’ 1 g2’0.5 2V± g3g3′ g3″g3 g4 B3= B2= B3= B2= tor as a function of the input level, when operating with and . The additional operation modes are also depicted. The modulator achieves a dynamic range DR of 85.5dB with , and , . DR is 80.5dB with , and , . Fig.3(b) shows its output spectrum for a -6dBV@250kHz input tone, operating with and . 3. Amplifiers According to the results in Table 2, the amplifier design should concentrate in the following aspects: •Required output swing, which must be feasible in a 3.3-V implementation. The output swing requirement strongly depends on the value of integrator weights selected for the Σ∆M [8]. With the weights in Table 1, the integrator output swing demands are reduced to only the reference voltages −i.e., −, so that they do not become tight for a fully-differential amplifier with 3.3-V supply. •Open-loop DC-gain: Although the SDOPT result for the DC-gain is 68dB, simulations with ASIDES show that this can be relaxed for amplifiers in the second (OA2), third (OA3), and fourth (OA4) integrator down to 62dB, 54dB, and 54dB, respectively. •Dynamics, which critically depend on the equivalent capacitive load of the amplifier Ceq and is rather different for each integrator. Ceq also changes from the sampling phase to the integration phase. They can be calculated as [9]: (1) where Ciand Coare the sampling and feedback capacitors of the integrator, respectively, Cpand Clrefer to the parasitics at the amplifier input and output nodes, M16= B4= M16= B4= M16= B3= M16= B2= M12= B4= M16= B4= 0.0 0.5 1.0 1.5 2.0 Frequency (MHz) -140 -120 -100 -80 -60 -40 -20 0 Amplitude (dBV) Fig. 3:2-12mb Σ∆M: (a) SNDR curves for different M,Bpairs, (b) Output spectrum operating with M= 16 and B=4. (b) (a) -6dBV@250kHz -80 -70 -60 -50 -40 -30 -20 -10 0 Input Amplitude (dBV) 0 10 20 30 40 50 60 70 80 90 SNDR (dB) M = 16, B = 4 (14b@4MS/s) M = 16, B = 3 (14b@2MS/s) M = 16, B = 2 (13b@4MS/s) M = 12, B = 4 (13b@4MS/s) vv+ A vo- (a) vo+ B Ib (b) Fig. 4:Schematics of the amplifiers: (a) Two-stage amplifier, (b) Folded-cascode OTA. Cm Cm Ib v-v+vo+voAB Table 4: Simulation results for the amplifiers. OA1 OA2 OA3 OA4 DC-gain 80.0dB 62.8dB 55.7dB 62dB GB 250MHz 311MHz 261MHz 167MHz PM 67o65o71o79o (1.6pF) (1.4pF) (1.4pF) (4.5pF) Output swing ±2.5V ±3.1V ±2.9V ±3.1V Transconductance 9.6A/V 4.2mA/V 2.6mA/V 5.4mA/V Max. output current ±40mA ±0.57mA ±0.45mA ±0.84mA Power consumption 38.5mW 4.5mW 4.0mW 6.6mW Table 3: Basic amplifier requirements. DC-gain DC-gain Driving Capabilities OA1 68dB 1.49pF 1.51pF high medium OA2 62dB 1.24pF 1.32pF medium medium OA3 54dB 1.24pF 1.32pF low medium OA4 54dB 0.56pF 4.89pF low high Ceq φ1 ,Ceq φ2 , 2V± Ceq φ2 ,CiCpClCnφ2 , +()1CiCp + Co -------------------+   ++= Ceq φ1 ,CpClCnφ1 , +()1Cp Co -------+   += stands for the sampling capacitors of the next integrator in the cascade, and refers to capacitors in the ADC for the fourth amplifier. Table 3 shows the equivalent loads for the four amplifiers, as well as their DC-gain requirements. Note that Ceq is similar for the first three ones during both clock-phases, but becomes considerably larger for OA4 during φ2, since it must drive the ADC. The diversity of specifications for the amplifiers recommends a dedicated design for each of them to avoid over-sizing and optimize the power consumption. A two-stage architecture, shown in Fig.4(a), was selected for OA1 in order to fulfil its DC-gain requirement. It uses a telescopic first stage and Miller compensation. A single-stage folded-cascode OTA, shown in Fig.4(b), has been used in OA2, OA3, and OA4 − enough to accomplish their medium-, low-DC-gain requirements. Although these amplifiers use the same structure, different sizings have been obtained for each of them, in order to fulfil their specifications with a reduced power consumption. The common-mode feedback net (not shown) is of dynamic type for all amplifiers, because it yields smaller power consumption than static ones for high-frequency operation. The main features of the four amplifiers are summarized in Table 4. Note OA1 and OA4 DC-gains are larger than required. Nevertheless, further re-fining of the sizing of these amplifiers did not imply significant reduction of their power consumption. 4. Comparators Comparators at the end of the first and second stages of the Σ∆M demand a low resolution time, while hysteresis as large as 30mV can be tolerated. The same applies for comparators in the last-stage flash ADC. This recommends the use a dynamic comparator based on a regenerative latch, with no need of a pre-amplifying stage. Fig.5 shows the schematic of comparators, widely used in Σ∆M design. The main features of the comparator are shown in Table 5. 5. Switches Due to the high-speed operation of the Σ∆M, finite switch ON-resistance Ron is mainly constricted by dynamic considerations. The influence of Ron in the incomplete charge transferring in combination with the finite opamp dynamics must be carefully evaluated, because it leads to a further degradation of the integrator response. Fig.6 shows the effect of Ron on the first integrator output voltage during a clock-cycle. Note that, as Ron increases, charge-transfer at the beginning of the phases is no more instantaneous and the integrator dynamic is slowed down. Nevertheless, Ron in the range of 250Ω300Ωcan be tolerated, with a minor degradation of the modulator performance. This value is not too demanding for a CMOS transfer gate in the intended technology −operating with a 3.3-V supply −, so that clock-boosting stages or similar techniques can be avoided [10]. CMOS switches, with aspect of 8/0.35 for the NMOS transistor and 29.5/0.35 for the PMOS, have been used. 6. Capacitors Capacitor ratios giving the integrator weights in the Σ∆M have been implemented using unitary capacitors. The value of the unitary is selected according to matching and thermal noise requirements. As formerly stated, this results in a 0.5-pF unitary capacitor for the first integrator and 0.25-pF unitary capacitors for the second, third, and fourth integrator. Besides this, the set of integrator weights in Table 1 has the advantage of requiring only two-branch integrators. This makes the total number of unitaries to be only 16 −smaller than in other cascade Σ∆Ms: 29 capacitors in [2] and [3], and 44 in [4]. Unitary capacitors have been implemented with a multi-metal sandwich structure, using the five metal layers available in the intended technology. The Cnφ1 ,Cnφ2 , φ2 φ2φ2 SRSo (a) (b) Fig. 5:Comparator: (a) Regenerative latch, (b) RS flip-flop. v+vRo Table 5: Simulation results for the comparators. Hysteresis <10mV TPLH 2.5ns TPHL 2.3ns Power consumption 0.65mW 0246810121416 time (ns) -0.25 -0.15 -0.05 0.05 0.15 0.25 Vout ( V) Ron = 0Ω Ron = 250Ω Ron = 1kΩ Integration (φ2) Sampling (φ1) Fig. 6:Evolution of the first integrator output. 0.5-pF unitary capacitor is 52x52µm2size and the 0.25-pF unitary is 36x36µm2. The bottom-plate parasitic capacitor, especially important for evaluating the amplifier dynamic requirements, is around 20% - 25% of the nominal capacitance. 7. Programmable A/D/A Converter The different M,Balternatives have been implemented by means of a selectable-resolution A/D/A converter, capable of 2bit-, 3bit-, or 4bit-quantization. Its SC implementation, depicted in Fig.7, corresponds to that of a 4bit fully-differential flash converter with an adaptable output code driving the DAC input. The latter consists of a simple resistor string of 30 unitaries (R=50Ω) connected between the reference voltages Vr+ = +1V and Vr- = -1V. The value selected for Rensures that settling errors in the voltage references transferred to the ADC during phase φ1and in the input capacitors of the fourth integrator during phase φ2are low enough. Resistors have been implemented using unsalicided p+ poly. The ADC uses 0.25-pF multi-metal sandwich capacitors and CMOS switches identical to that used in the SC integrators. The timing schemeof the switches has been adapted to reduce the capacitive load of the fourth integrator, driving the ADC. Nevertheless, it suffers from input-dependent feedthrough from switches controlled by φ2. This problem has been overcame by making these switches considerably smaller (1/0.35 for both NMOS and PMOS transistors), without degrading the ADC performance. The 4bit ADC output is digitally combined, as illustrated in Fig.7, to provide 2bit-, 3bit-, or 4bit-resolution. The resolution selection is done by input signals S2b and S3b, as shown in Fig.7(b). The functionality of this circuitry, shown in Fig.8, basically consists in the OR operation of the appropriate digital outputs d0-15*of the 4bit ADC in order to accommodate them to a 1-of-4 or 1-of-8 code. Note in Fig.8(a) that, since (24-1)/(22-1) = 5 is an integer, the 4bit-to-2bit conversion leads to a regular 2bit A/D/A converter with full-scale range FS = . For the 4bit-to-3bit conversion, since (24-1)/(23-1) = 2.14 is not an integer, a 3bit A/D/A converter with and an offset error of 133mV (0.25LSB) is obtained. Nevertheless, cascade multi-bit Σ∆Ms present very low sensitivity to offset errors in the DAC [8], so that the overall modulator performance is not degraded. 8. Layout and Prototyping For the layout of the 2-12mb Σ∆M, in Fig.9, the following considerations were taken into account: • Centroid techniques with unitary transistors have Fig. 7:A/D/A converter: (a) Block diagram, (b) Resolution selection, (c) Partial view of the SC implementation. + - o o + - o o - + o o (a) (c) R R R R R Rφ 2 φ 2 φ 2 φ 1 φ 1 φ 1 φ 1 φ 1 φ 1 φ 2 φ 2 φ 2 φ 2 φ 1d φ 1d φ 1d φ 1d φ 1d φ 1d v+vd 9 d 6 d 7 d 8 d 6 d 9 d 8 d 7 v o + v o - C C C ADC DAC v+ vvo+ vod0-3 d0-15*d0-7 d0-15 CONTROL CIRCUITRY S3bS2bVrVr+ d9* VDDA S3bS2b S3bS2b S3bS2b VDDA VDDA d8 d8 S3bS2b S3bS2b S3bS2bd9 d9 d8* d7* VDDA S3bS2b S3bS2b S3bS2b VDDA VDDA d6 d6 S3bS2b S3bS2b S3bS2bd7 d7 d6* S3bS2bOutput code Resolution 0 0 1-of-16 4bit 0 1 1-of-4 2bit 1 0 1-of-8 3bit 1 1 not allowed (b) 2V± FS 1.87V±= been employed for matched transistors in the amplifiers and in the regenerative latches. • Separate analog and digital power supplies have been used. Analog supplies (VDDA,V SSA) have been employed for the voltage biasing of the substrate and the well rings and for the current biasing of the analog blocks. Separated routing lanes have been assigned for that purpose. Digital supplies (VDDD,V SSD)have been used for the biasing of internal digital blocks. • In order to reduce the digital switching noise, digital supplies will eventually be reduced during testing. To enable this without affecting the modulator performance, the output stages of digital blocks driving analog parts have been biased with the analog supplies. • Powerful digital buffers have been designed for the high-speed digital outputs (Y1,Y2,Y3,0-3)of the Σ∆M. Dedicated power supplies (VDDD2,V SSD2) have been used for them, in order not to affect the performance of the remaining digital circuitry. The complete modulator occupies an area of 1.32mm2 without pads (4.30mm2pads included). The modulator power consumption −estimated through electrical simulation −is 78.3mW: 60.2mW for the analog blocks, 4.5mW for the digital part, and 13.6mW for the output drivers. The circuit is being processed by the silicon foundry and experimental results are expected to be available for the presentation at the Conference. References [1] F. Medeiro, B. Pérez-Verdú and A. Rodríguez-Vázquez: “A 13-bit, 2.2-MS/s, 55-mW Multibit Cascade Σ∆ Modulator in CMOS 0.7-µm Single-Poly Technology,” IEEE J. of Solid-State Circuits, vol. 34, pp. 748-760, June 1999. [2] A. M. Marques, V. Peluso, M. S. J. Steyaert, and W. Sansen: “A 15-b Resolution 2-MHz Nyquist Rate ∆Σ ADC in a 1-µm CMOS Technology,” IEEE J. of Solid-State Circuits, vol. 33, pp. 1065-1075, July 1998. [3] Y. Geerts, A. Marques, M. Steyaert, and W. Sansen: “A 3.3-V, 15-bit, Delta-Sigma ADC with a Signal Bandwidth of 1.1 MHz for ADSL Applications,” IEEE J. of Solid-State Circuits, vol. 34, pp. 927-936, July 1999. [4] A.R. Feldman , B. E. Boser, and P. R. Gray: “A 13-Bit, 1.4-MS/s Sigma-Delta Modulator for RF Baseband Channel Applications,” IEEE J. of Solid-State Circuits, vol. 33, pp. 1462-1469, Oct. 1998. [5] B. Brandt and B. A. Wooley: “A 50-MHz Multibit Σ∆ Modulator for 12-b 2-MHz A/D Conversion,” IEEE J. of Solid-State Circuits, vol. 26, pp. 1746-1756, Dec. 1991. [6] R. del Río, F. Medeiro, B. Pérez-Verdú, and A. Rodríguez-Vázquez. “High-Order Cascade Multi-bit Σ∆ Modulators for High-Speed A/D Conversion,” Proc. Design of Circuits and Integrated Systems Conf. (DCIS’98),pp. 76-81, Madrid, Nov.1998. [7] R. del Río, F. Medeiro, B. Pérez-Verdú, and A. Rodríguez-Vázquez: “High-Order Cascade Multibit Σ∆ Modulators for xDSL Applications,” Proc. Int. Symp. Circuits and Systems (ISCAS’2000),Geneva, to be held in May 2000. [8] F. Medeiro, B. Pérez-Verdú, and A. Rodríguez-Vázquez: “Top-Down Design of High-Performance Modulators,” Kluwer Academic Publishers, 1999. [9] R. del Río, F. Medeiro, B. Pérez-Verdú, and A. Rodríguez-Vázquez: “Reliable Analysis of Settling Errors in SC Integrators −Application to the Design of High-Speed Σ∆ Modulators,” Proc. Int. Symp. Circuits and Systems (ISCAS’2000),Geneva, to be held in May 2000. [10] J.-T. Wu and K.-L. Chang: “MOS Charge Pumps for Low-Voltage Operation,” IEEE J. of Solid-State Circuits, vol. 33, n. 4, pp. 592-597, April 1998. -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 Analog input (V) -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 Analog output (V) d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 Fig. 8:Programmable A/D/A converter: (a) 4bit-to-2bit conversion, (b) 4bit-to-3bit conversion. -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 Analog input (V) -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 Analog output (V) d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d2 d4 d1 d3 d5 d6 d7 (a) (b) d0 d0 d0 Fig. 9:Layout of the 2-12mb Σ∆M. ADC DAC CLK Integ1 Integ2 Integ3 Integ4 Digital buffers ROM