Bifurcations and synchronization using an integrated programmable chaotic circuit

International Journal of Bifurcation and Chaos 1 BIFURCATIONS AND SYNCHRONIZATION USING AN INTEGRATED PROGRAMMABLE CHAOTIC CIRCUIT M. DELGADO-RESTITUTO, M. LIÑÁN, J. CEBALLOS and A. RODRÍGUEZ-VÁZQUEZ Centro Nacional de Microelectrónica (CNM) Ed. CICA, Avda. Reina Mercedes s/n 41012 - Seville, SPAIN. This paper presents a CMOS chip which can act as an autonomous stand-alone unit to generate different real-time chaotic behaviors by changing a few external bias currents. In particular, by changing one of these bias currents, the chip provides different examples of a period-doubling route to chaos. We present experimental orbits and attractors, time waveforms and power spectra measured from the chip. By using two chip units, experiments on synchronization can be carried out as well in real-time. Measurements are presented for the following synchronization schemes: linear coupling, drive-response and inverse system. Experimental statistical characterizations associated to these schemes are also presented. We also outline the possible use of the chip for chaotic encryption of audio signals. Finally, for completeness, the paper includes also a brief description of the chip design procedure and its internal circuitry. Running Title: A Chip for Real-Time Generation of Chaotic Behaviors Contact Author: Angel Rodríguez-Vázquez Centro Nacional de Microelectrónica (CNM) Ed. CICA, Avda. Reina Mercedes s/n 41012 Sevilla, SPAIN Phone: +34 5 423 99 23 Fax: +34 5 423 18 32 E-Mail: [email protected] 2 Bifurcations and Synchronization using an Integrated Programmable Chaotic Circuit BIFURCATIONS AND SYNCHRONIZATION USING AN INTEGRATED PROGRAMMABLE CHAOTIC CIRCUIT M. DELGADO-RESTITUTO, M. LIÑÁN, J. CEBALLOS and A. RODRÍGUEZ-VÁZQUEZ Centro Nacional de Microelectrónica (CNM) Ed. CICA, Avda. Reina Mercedes s/n 41012 - Seville, SPAIN. This paper presents a CMOS chip which can act as an autonomous stand-alone unit to generate different real-time chaotic behaviors by changing a few external bias currents. In particular, by changing one of these bias currents, the chip provides different examples of a period-doubling route to chaos. We present experimental orbits and attractors, time waveforms and power spectra measured from the chip. By using two chip units, experiments on synchronization can be carried out as well in real-time. Measurements are presented for the following synchronization schemes: linear coupling, drive-response and inverse system. Experimental statistical characterizations associated to these schemes are also presented. We also outline the possible use of the chip for chaotic encryption of audio signals. Finally, for completeness, the paper includes also a brief description of the chip design procedure and its internal circuitry. 1. Introduction Chaos in electrical circuits has drawn strong attention during the last decade [Chua, 1987; Chua & Hasler, 1993]. This topic is of evident theoretical interest since circuits provide very simple vehicles for the experimental observation of chaotic phenomena (instead of only through computer simulation). Chaos is also of practical engineering interest. For instance, the inherent unpredictability of deterministic chaos has been used to design improved white and colored noise generators [McGonigal & Elmasry,1987; RodríguezVázquez et al., 1991; Murch & Bates, 1990; Delgado-Restituto et al., 1992], as well as for the generation of secure random number time-series [Bernstein & Lieberman, 1990; Rodríguez-Vázquez et al., 1991]. The random-like appearance of chaos has also proven International Journal of Bifurcation and Chaos 3 useful to improve the noise performance of switched-capacitor Σ∆ modulators, making these circuits operate in chaotic regimes [Schreier, 1991; Hein, 1993]. Chaotic circuits also exhibit potential applications in nonlinear signal processing and neural computation. On one hand, the possibility of two or more chaotic systems oscillating in a coherent, synchronized way can be exploited for signal encryption and secure communications [Carroll & Pecora, 1991; Oppenheim et al., 1992; Kocarev et al., 1992]. On the other, the fact that chaos has been identified to be behind the sensory information processing performed by natural nervous systems [Matsumoto et al., 1987; Freeman, 1992], motivates looking for artificial neural network paradigms based upon chaotic neurons, in an attempt to better emulate living beings [Aihara et al., 1990, Nozawa, 1992]. In today’s electronic systems, economic reasons dictate the convenience of having all component parts integrated on common silicon substrates, instead of breadboarded using off-the-shelf components. In this scenario, and before the potentials of chaotic circuits can be exploited into future marketable instrumentation, communication, or computing systems, it must be demonstrated that chaos can be generated in a controllable and robust form using monolithic circuits,preferably in standard VLSI technologies. Up to date, only few of the previously reported chaotic circuits have been realized as monolithic†1 integrated circuits. In 1987 [Rodríguez-Vázquez et al., 1987], the authors started a research line in this direction which has resulted in a number of CMOS chips. Some of them are described by finite-difference equations (FDE’s), while others are described by ordinary differential equations (ODE’s). In 1991 a programmable integrated noise source was presented based on the Bernoulli shift [Rodríguez-Vázquez et al., 1991]. It uses switched-capacitor techniques, the same as in the flicker noise generator presented in 1992 [Delgado-Restituto et al., 1992]. In 1993, an integrated circuit for white noise generation was presented [Delgado-Restituto et al., 1993] which uses nonlinear switched-current techniques [Rodríguez-Vázquez & Delgado-Restituto, 1994]. Although all these ICs are simple and robust, their sampled-data nature restricts the maximum frequency attainable. In 1993 an integrated chaotic generator was presented which overcomes this problem through the use of continuous-time circuitry to realize ODE’s [Rodríguez-Vázquez & Delgado-Restituto, 1993]. Other working†2 ICs intended to be used as parts (together with off-chip components) of chaotic electronic systems are found in [Cruz & Chua, 1993], [DelgadoRestituto & Rodríguez-Vázquez, 1994] and [Horio & Suyama, 1995]. However, they are basically intended to be used as modules of larger breadboarded chaotic circuits. 1. By monolithic we mean all the needed components are fabricated on the same silicon substrate. 2. Chips demonstrated only through simulation results are not included. 4 Bifurcations and Synchronization using an Integrated Programmable Chaotic Circuit The chip presented here is an updated version of that in [Rodríguez-Vázquez & Delgado-Restituto, 1993]. The original one was basically aimed to prove the possibility to build an ODE-based chaotic generator in a fully monolithic manner. Although this goal was achieved, the circuit suffered from the problems of such demonstration IC units: rather tricky controllability and difficult to use by others except the designers. The new chip overcomes these problems. It is easy to use and control, and its robustness has been significantly enhanced through system-level and circuit-level optimization. It has been fabricated in a 2.4µm double-poly double-metal CMOS technology, and occupies 5mm2 with a power consumption of 1.8mW for a 5V voltage supply. A remarkable feature of the new prototype is its versatility for the observation of bifurcation and synchronization phenomena by just controlling a few external bias currents. The outline of the paper is as follows. Section 2 introduces the state equations of the oscillator, details the output pins description of the chip as well as their electrical characteristics, and identifies which terminals serve as programming variables of the dynamic behavior. Sections 3 and 4 are tailored to illustrate the performance of the prototype through experimental measurements of bifurcation and synchronization phenomena, respectively. Finally, Sec. 5 gives a theoretical basis for the functional description introduced in Sec. 2 and presents the internal block diagram of the chaotic oscillator, ignoring as much as possible microelectronic-related details. 2. Chip Terminals and Interconnections Fig.1(a) shows the pin connections and internal structure of the integrated chaotic generator and Fig.1(b) shows the experimental setup. The chip architecture comprises a core chaotic oscillator and some auxiliary circuitry (three voltage buffers and a time constant reference unit) to increase the versatility of the prototype. The chip has 16 external pins. The most important block in the architecture of Fig.1 is the core chaotic oscillator. It implements a third order autonomous continuous-time system, which includes an odd-symmetric, three-region piecewise-linear (PWL) nonlinearity, (8) where (see Fig.2) is given by, (9) τtd dx1hx 1 ()αx2 += τtd dx2αx1x3 –()γx2 –= τtd dx3βx2 = h() hx 1 () m1x1 m0m1 – 2 ------------------- x1Bp +x1Bp ––{}+= International Journal of Bifurcation and Chaos 5 The behavior is determined by seven parameters. Four of them, , are externally programmable. The other three, , have fixed values. The programmable parameters are controlled through the low impedance inputs , , and . They have DC levels around −0.5V, and the controlling τm0m1and Bp ,, αβand γ,               Fig. 1. (a) Chip architecture; (b) Experimental setup showing oscilloscope, chip wit h four tuning resistors, and the battery pack. Core Chaotic Oscillator Reference Unit x1 x2 x3 x1,buf x2,buf x3,buf cont4 cont3 cont2 tin tout VSS VDD cont1 toff Buffered Output Pins Output        Tuning          Control contiPins Pins Pins Icont i, Rci, (a) (b) cont1cont2cont3cont4 6 Bifurcations and Synchronization using an Integrated Programmable Chaotic Circuit variables are the currents entering the terminals. Because of the low-impedance feature, each current can be generated using a simple resistance (see inset of Fig.1). sets the time constant of the chaotic oscillator ( ) which thus can vary approximately between and . and set respectively the central and outer slopes of the nonlinearity. Achievable ranges are between 0 and 5 for , and between -1 and -3 for . Finally, , together with , controls the breakpoints of the nonlinearity ( ). Table I shows the electrical characteristics of F ig. 2. Nonlinearity of the chaotic oscillator. h(x1) x1 Bp −Bp m1 m0 m1 Characteristic Symbol Min Typ Max Unit Positive Power Supply Voltage 2.0 3.0 5.0 Vdc Negative Power Supply Voltage -2.0 -3.0 -5.0 Vdc Tuning Parameter, () 1.0 1.5 5.0 µA Bifurcation Parameter, () 0.0 1.5 10.5 µA Bifurcation Parameter, () 1.0 2.5 4.5 µA Amplitude Parameter, () 0.2 0.3 0.7 µA Table I: Electrical characteristics (typical conditions are for reproducing the Chua’s double-scroll attractor). VDD VSS τ VDD VSS – 3.0 V== Icont1 m0 VDD VSS – 3.0 V== Icont2 m1 VDD VSS – 3.0 V== Icont3 Bp VDD VSS – 3.0 V== Icont4 Icont1 ττIcont1 () 12⁄– ∼ 12µs60µsI cont2Icont3m0 m1m0 m1Icont4Icont1Bp BpIcont4Icont1 () 12⁄– ∼ International Journal of Bifurcation and Chaos 7 the control pins at room temperature, as well as the range of biasing conditions of the chip, assuming that power supply is symmetrical with respect to ground ( ). Fig.3 shows the variation of the realized nonlinear characteristic for different parameter configurations. They have been obtained by varying quasi-statically from rail to rail the voltage at pin of Fig.1, while fixing the output pins and to ground. Fig.3(a) illustrates the effect of changing the biasing current , while keeping the rest of control variables constant ( , and ). Note that as the value is increased by the effect of lowering , the nonlinear characteristics suffers from a breakpoint displacement towards the power rails, which may preclude the existence of chaotic regime. This problem can be overridden by forcing a proper reduction on the current . Fig.3(b) illustrates the effect of varying while keeping the rest of control inputs fixed ( and the biasing currents and as before). Finally, Fig.3(c) and (d) show the variation of the nonlinear characteristic for different slopes and of the central and outer pieces, respectively. As previously stated, they can be externally controlled through biasing currents and applied to pins VDD VSS –= Fig. 3. Variation of the PWL characteristics of the nonlinearity with: (a) ; (b) ; (c) the central slope, (control variable ); and (d) the outer slopes, (control variable ). Icont1 Icont4m0Icont2 m1Icont3 -2.5 -1.5 -0.5 0.5 1.5 2.5 Input Voltage (V) -3.0 0.0 3.0 Output Current (µA) (a) 0.5 /div 0.6 /div (b) -2.5 -1.5 -0.5 0.5 1.5 2.5 Input Voltage (V) -3.0 0.0 3.0 Output Current (µA) 0.5 /div 0.6 /div -2.5 -1.5 -0.5 0.5 1.5 2.5 Input Voltage (V) -3.0 0.0 3.0 Output Current (µA) (c) 0.5 /div 0.6 /div (d) -2.5 -1.5 -0.5 0.5 1.5 2.5 Input Voltage (V) -3.0 0.0 3.0 Output Current (µA) 0.5 /div 0.6 /div x1x2x3 Icont1 Icont21.12µA= Icont32.7µA= Icont40.3µA= τIcont1 Icont4Icont4 Icont11.4µA= Icont2Icont3 m0m1Icont2Icont3 8 Bifurcations and Synchronization using an Integrated Programmable Chaotic Circuit and , respectively. Output pins , and are high impedance nodes which correspond to the state variables of the core chaotic oscillator. Since these state variables are voltages, and because of the high-impedance feature (about 1.5MΩ under usual operation conditions), significant loading errors may appear when measuring at these output terminals. These loading problems are alleviated by using the low-impedance buffered output pins , and (their output impedances are below 200Ω under usual operation conditions). A time-constant reference unit has been also included (see Fig.1) to guarantee proper parameter matching among synchronizing chips. For synchronization to occur, it is necessary not only to have good relative parameter matching inside each chip (guaranteed by our adopted design strategies), but also good relative matching among the same parameter at different chip instances. This is difficult to achieve without tuning because of uncontrollable random fluctuations, as well as variations with temperature and aging. Due to this, designers have to face a scenario where parameters have around 20% errors -- intolerable to guarantee the asymptotic synchronization of the oscillators. Fig.4 shows the block diagram of the automatic tuning circuitry. The on-chip reference unit simply consists of an integrator matched with those in the core chaotic oscillator. The time constant of this integrator (master system) is tuned to an accurately defined external reference frequency. If all the integrators included on-chip are simultaneously tuned, the cont2cont3 x1x2x3 x1buf,x2buf, x3buf, 1 τ ∫ F ig. 4. Automatic Tuning Mechanism. LPF Crystal Oscillator Amplitude Detector Amplitude Detector + −k A/ωτ A A sin ωt Voff VIC Icont1 Vfreq Core Chaotic Oscillator x1 x2 x3 x1,buf x2,buf x3,buf cont4 cont3 cont2 tin tout VSS VDD cont1 toff Reference Unit International Journal of Bifurcation and Chaos 9 time constant of the oscillator (slave system) is related to the reference frequency as well. The accuracy of the tuning mechanism is determined by the matching of on-chip component values (absolute errors of about 1-2% can be obtained). Note that tuning is based on amplitude detection. Pins and in Fig.1 represent respectively the input and output nodes of the integrator. A voltage-mode crystal oscillator is applied to and the changes in the output amplitude (measured at pin ) with the frequency of the reference signal, are detected and used to tune the system. The control signal generated by the system in closed loop is converted to a current and then applied to pin so that the time constant of the circuit becomes locked to that of the external crystal oscillator. Proper operation of the proposed tuning mechanism relies on the integrator be offset-free. Otherwise, the output amplitude will change linearly with time regardless of the signal provided by the crystal oscillator. To avoid this situation, an offset correction terminal (pin in Fig.1) is added to the scheme, so that any deviation can be externally compensated. 3. Experimental Bifurcations Next, we present a picture book of bifurcation sequences, chaotic attractors and periodic windows which has been measured on the silicon prototype by changing the bias currents and . The other programmable parameters were set to and . The book comprises Fig.5 through Fig.21. Among them, the first seven figures illustrate corresponding instances of a typical period-doubling route to chaos which have been obtained by only varying the biasing current while fixing . For each value of and (indicated in the associated figure captions) along the picture book we show the phase portraits of the attractor, the power spectrum of the voltage at pin , and the time waveforms of the three state variables. In both the Lissajous figures and time waveforms, the representation scale for the state variable is set to . Corresponding oscilloscope scales for the and variables are and , respectively. The waveform temporal basis is for Figs.5-8, and for Figs.9-21. Finally, for the horizontal scale of the spectrum, the left side of the display is nearly DC, with , while the vertical scale is . The experimental results obtained from the prototype are in full accordance with measurements previously reported from discrete component realizations [Chua et al., 1993]. tin tout tin tout Vfreq cont1 toff Icont2Icont3Icont11.4µA= Icont40.3µA= Icont2 Icont32.35 µA= Icont2Icont3 x1x1 350mV div⁄x2x3 200mV div⁄400mVdiv⁄0.2ms div⁄ 0.5ms div⁄ 2kHz div⁄ 10dB div⁄ 16 Bifurcations and Synchronization using an Integrated Programmable Chaotic Circuit Fig. 11. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , .x1Icont21.15 µA=Icont32.35 µA= Double Scroll Chaotic Attractor Projection x1 - x2Projection x1 - x3Projection x2 - x3 Waveform x1Waveform x2Waveform x3 Spectrum x1 International Journal of Bifurcation and Chaos 17 Fig. 12. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , .x1Icont21.24 µA=Icont32.47 µA= 3-3 Periodic Window Projection x1 - x2Projection x1 - x3Projection x2 - x3 Waveform x1Waveform x2Waveform x3 Spectrum x1 18 Bifurcations and Synchronization using an Integrated Programmable Chaotic Circuit Fig. 13. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , .x1Icont21.47 µA=Icont32.56 µA= Double Scroll Chaotic Attractor Projection x1 - x2Projection x1 - x3Projection x2 - x3 Waveform x1Waveform x2Waveform x3 Spectrum x1 International Journal of Bifurcation and Chaos 19 Fig. 14. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , .x1Icont21.62 µA=Icont32.56 µA= 4-4 Periodic Window Projection x1 - x2Projection x1 - x3Projection x2 - x3 Waveform x1Waveform x2Waveform x3 Spectrum x1 20 Bifurcations and Synchronization using an Integrated Programmable Chaotic Circuit Fig. 15. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , .x1Icont21.60 µA=Icont32.58 µA= Double Scroll Chaotic Attractor Projection x1 - x2Projection x1 - x3Projection x2 - x3 Waveform x1Waveform x2Waveform x3 Spectrum x1 International Journal of Bifurcation and Chaos 21 Fig. 16. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , .x1Icont21.65 µA=Icont32.61 µA= 5-5 Periodic Window Projection x1 - x2Projection x1 - x3Projection x2 - x3 Waveform x1Waveform x2Waveform x3 Spectrum x1 22 Bifurcations and Synchronization using an Integrated Programmable Chaotic Circuit Fig. 17. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , .x1Icont21.70 µA=Icont32.61 µA= Double Scroll Chaotic Attractor Projection x1 - x2Projection x1 - x3Projection x2 - x3 Waveform x1Waveform x2Waveform x3 Spectrum x1 International Journal of Bifurcation and Chaos 23 Fig. 18. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , .x1Icont21.72 µA=Icont32.63 µA= 6-6 Periodic Window Projection x1 - x2Projection x1 - x3Projection x2 - x3 Waveform x1Waveform x2Waveform x3 Spectrum x1 24 Bifurcations and Synchronization using an Integrated Programmable Chaotic Circuit Fig. 19. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , .x1Icont21.79 µA=Icont32.66 µA= Double Scroll Chaotic Attractor Projection x1 - x2Projection x1 - x3Projection x2 - x3 Waveform x1Waveform x2Waveform x3 Spectrum x1 International Journal of Bifurcation and Chaos 25 Fig. 20. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , .x1Icont21.81 µA=Icont32.66 µA= 7-7 Periodic Window Projection x1 - x2Projection x1 - x3Projection x2 - x3 Waveform x1Waveform x2Waveform x3 Spectrum x1 32 Bifurcations and Synchronization using an Integrated Programmable Chaotic Circuit 4.3 Inverse System Scheme Fig.27(a) shows the experimental setup used to demonstrate synchronization by the inverse system approach between two of the manufactured chips. A voltage signal is linearly converted to a current and injected in the terminal of the first chip. The voltage generated by this prototype is then transmitted to a receiving system which consists of a current detector, a voltage amplifier and a chaotic oscillator matched with that of the transmitter. In the receiver, the signal drives the current detector which is a device with one inputand two output-ports. One of the output terminals acts as a voltage buffer from the input port, and it is connected to the terminal of the second chaotic oscillator prototype. The other terminal provides a voltage proportional to the current flowing through the first output port, and it is connected to a programmable voltage amplifier. This amplifier, in turn, controls the amplitude of the voltage generated by the current detector and obtains the recovered signal . In practice, the current detector and the voltage amplifier can be funded in a single block formed by an opamp and an instrumentation amplifier. Fig.27(b) illustrates the performance of the setup. The picture on the left shows the input signal (a sine wave of 10kHz and ) and the recovered signal . As can be seen a nearly perfect synchronization is achieved. On the other hand, the picture on Fig. 26. Synchronization performance of the -drive system.x2 (a) (b) x13 buf, x23 buf, x12 buf, x11 buf, x 21 buf, x 12 buf, st() x11 Φt() x11 buf, = Φt() x21 rt() st( ) 350mVpp–rt() International Journal of Bifurcation and Chaos 33 the right of Fig.27(b) shows the waveform of the chaotic modulated transmitted signal, which clearly keeps no resemblance with the injected tone. Fig.28 shows the power spectra of the signals in Fig.27(b)-(c). Note that the signal to noise ratio of the recovered signal (Fig.28(c)) is greater than +55dB with less than -0.2dB loss of the input signal power (Fig.28(a)) †4. Also note that the spectrum of the transmitted 4. For input frequencies around 15kHz, the signal-to-noise ratio rises up to +60dB. cont4 cont3 cont2 tin tout cont1 Xtal Osc. Amp.Det. Amp. Det. Differential Amplifier Signal Conditioning toff cont4 cont3 cont2 tin tout cont1 Xtal Osc. Amp.Det. Amp. Det. Differential Amplifier Signal Conditioning toff Fig. 27. (a) Simplified experimental setup for the inverse system approach; (b) Measured performance. time st() rt() (a) (b) VIC Amp time s(t) Current Detector r(t) Φ(t) Φt() Core Chaotic Oscillator Reference Unit VSS VDD Chip 2 VSS VDD Chip 1 Core Chaotic Oscillator Reference Unit 50 µs/div 5 ms/div x12 x13 x12,buf x13,buf x22 x23 x21,buf x22,buf x23,buf 34 Bifurcations and Synchronization using an Integrated Programmable Chaotic Circuit signal does not present a peak at the input frequency, thus confirming that is completely hidden on the chaotic waveform . At lower tone frequencies, masking property still holds, but the signal-to-noise ratio of the recovered signal notably worsens. In fact, for input frequencies below 1kHz, it has been found that the signal-to-noise ratio drops down to +40dB, while retaining similar losses at the receiver. The performance of the inverse system setup in Fig.27(a) has been also statistically characterized in time domain by comparing the input signal with the recovered signal . We have assumed that consists of a single tone and have varied its amplitude and frequency. By keeping track of the recovered signal , we can identify which are the better conditions for signal transmission. Fig.29 shows the offset, variance and maximal deviation of the recovered signal with respect to the input signal. Special mention deserves the evolution of the variance with the tone amplitude, shown in Fig.29(b). Observe that for low tone amplitudes (below 350mV), the variance maintains small (less than ) for input frequencies between 1 and 25kHz. As the amplitude raises from this value, the variance abruptly increases, specially at the bounds of the input frequency range. This means that for amplitudes larger than about 350mV, synchronization is lost. We have identified two main causes for desynchronization: • The receiver is unable to keep track of the transmitted signal. • The transmitter becomes locked at a stable limit cycle regardless of . The first cause fundamentally appears at high input frequencies, while the second occurs for low input frequencies. For amplitudes lower than 350mV, the system may exhibit sporadic losses of synchronization as indicated by the maximal deviation between the input and recovered signals, shown in Fig.29(c). However, after a short transient, synchronization is again restored. st() Φt() Fig. 28. Power spectra of the (a) input signal; (b) transmitted signal; and (c) recovered signal. (b) (a) (c) st() rt() st() rt() 1.5mV2 Φt() International Journal of Bifurcation and Chaos 35 We have also experimentally evaluated the correlation index between the input and Fig. 29. Time-domain performance of the chaotic modulation synchronization scheme using two integrated prototypes. 0.0 200.0 400.0 600.0 800.0 1000.0 Tone Amplitude (mV) -75.0 -50.0 -25.0 0.0 25.0 Voltage (mV) Offset Voltage 1 kHz 5 kHz 10 kHz 15 kHz 25 kHz 0.0 200.0 400.0 600.0 800.0 1000.0 Tone Amplitude (mV) 0.0 3.0 6.0 9.0 12.0 Variance 0.0 200.0 400.0 600.0 800.0 1000.0 Tone Amplitude (mV) 0.0 50.0 100.0 150.0 200.0 Voltage (mV) Maximal Deviation (a) (b) (c) 1 kHz 5 kHz 10 kHz 15 kHz 25 kHz 1 kHz 5 kHz 10 kHz 15 kHz 25 kHz Voltage Square (mV2) 36 Bifurcations and Synchronization using an Integrated Programmable Chaotic Circuit the recovered signals. This is illustrated in Fig.30. Observe that, for tone amplitudes above 150mV, correlation index is always larger than 0.9 regardless of the input frequency. Taking this into account as well as the previous results on the variance, we conclude that the amplitude of the input signal must be comprised between 150mV and 350mV, for input frequencies between 1 and 25kHz, in order to guarantee synchronization. Taking into account the range of frequencies used for and the noise-like appearance of the transmitted signal , the synchronization scheme in Fig.27(a) could be readily exploited for audio signal encryption. To evaluate the security of the transmission, we have measured the correlation index between the input and the transmitted signal, assuming again that consists of a single tone. The results are shown in Fig.31. Note that the index is close to zero for every input frequency, excepting at 1kHz. In this last case, since the transmitter evolves into a stable limit cycle for input amplitudes above 350mV, the correlation index tends to increase. 5. Chip Function and Block Diagram This section contains the functional description and circuit realization of the core chaotic oscillator. For those readers with scarce knowledge of integrated circuit design, some fundamental concepts will be given at the front-end of this description. Fig.32 illustrates a systematic procedure for the monolithic realization of arbitrary Fig. 30. Correlation index between the input and the recovered signals. 0.0 200.0 400.0 600.0 800.0 1000.0 Tone Amplitude (mV) 0.50 0.75 1.00 Correlation Index 1 kHz 5 kHz 10 kHz 15 kHz 25 kHz st() Φt() st() International Journal of Bifurcation and Chaos 37 nonlinear dynamical systems. This procedure strongly relies upon proper hierarchical problem decomposition as shown in Fig.32, which particularizes for the well-known doublescroll attractor. The first step in the methodology is to identify the set of equations describing the dynamics. This corresponds to the behavioral level at the top of the hierarchy. The obtained description maps down to the block level, which defines a network synthesis architecture for the problem. At the block level, the different operators, or functional building blocks, required for physical realization, as well as their interconnection, are clearly identified. Each of these blocks must be subsequently mapped down to a collection of interconnected circuit elements, thus defining a circuit level. Two different sublevels can be identified; one containing only idealized elements (for instance VCCS’s), and another where these idealized elements are realized using available circuit primitives of the technology. Fig.32 illustrates both sublevels. Observe that the circuit level infers choosing the physical nature of the variables which support information flow (usually voltages, currents or both). Bottom level in the VLSI design hierarchy define the layout phase, where circuit primitives are codified into geometrical objects required for processing and fabrication. In this paper, we will be mainly interested in the two first steps of the hierarchy, i.e., in the behavioral and block level design aspects of the chaotic oscillator. Technical details at the circuit and layout levels will be published elsewhere. Fig. 31. Correlation index between the input and the transmitted signals. 0.0 200.0 400.0 600.0 800.0 1000.0 Tone Amplitude (mV) -0.25 0.00 0.25 0.50 Correlation Index 1 kHz 5 kHz 10 kHz 15 kHz 25 kHz 38 Bifurcations and Synchronization using an Integrated Programmable Chaotic Circuit Fig. 32. Synthesis route towards monolithic nonlinear circuits. τxdx dt⁄()αyx–fx()–[]= τydy dt⁄()xy–z+= τzdz dt⁄()βy–=      fx() bx ab– 2 ------------xE+xE––{}+= 1/τy −α/τx α/τx −1/τy ∑∫ f(.) 1/τy −β/τz xyz −α/τx zyx τττ + _ + _ + _ βy αw w +_ zw Vi1Vi2 IQ Polysilicon n+ diffusion Behavioral Level ∑∫ ∑∫ Block Level Circuit Level Physical Level International Journal of Bifurcation and Chaos 39 5.1 Behavioral Level Description The mathematical model of the designed chaotic oscillator is a canonical system (which will be defined below) of the family of continuous, odd-symmetric, three-region piecewiselinear (PWL) vector fields in . Members of this family, denoted hereafter by , are generally represented by the following third order continuous-time nonlinear state equation [Chua et al., 1986], (10) which can be mapped onto the analog computer concept shown in Fig.33. In the above equation, represents the time-integration constant; is the state-space vector; is a real invertible square matrix defining the linear part of the system; and are real 3-dimensional vectors; and the nonlinear map is a real-valued continuous PWL function given by (11) where is a real scale factor, with no influence on the qualitative dynamic behavior of the system. The function thus defined, divides into an inner region containing the origin, and two outer regions and , in such a way that, . According to Eq. (11), the two parallel boundary planes separating from the outer regions and , are given respectively by, ℜ3L3 τtd dxt() Fxt()[]Ax t() BfD†xt()[]+== τxt() x1t() x2t() x3t(),,[] † = Aaij []= Bbi []=Ddi []= f () Fig. 33. Block diagram for the members of the family .L3 ρ f(ρ) Bp Bp – Σ1 τ∫ A B f(•) x x .ρ D fD†xt()[] 1 2 ---D†xt() Bp +D†xt() Bp ––{}= Bp f () ℜ3D0 D+1 D1– Fx() Fx–()–= D0D+1 D1– 40 Bifurcations and Synchronization using an Integrated Programmable Chaotic Circuit (12) It is worth noting that the qualitative behavior of any member of the family is solely determined by the three eigenvalues associated to the inner region of the vector field , and the three eigenvalues associated to the outer regions [Chua et al., 1986]. By canonical systems of we mean those vector fields in such that, with only 7 nonzero parameters, are able to synthesize almost every prescribed set of eigenvalue patterns, and hence, to reproduce almost every possible qualitative dynamics in †5 [Chua & Lin, 1990; Chua, 1993]. A well-known example of canonical system in is the Chua´s oscillator which is endowed with a rich repertoire of nonlinear dynamical phenomena, including all kinds of bifurcations and routes to chaos (period-doubling, intermittency and torus breakdown). Actually the number of strange attractors which can be generated with Chua´s oscillator form a zoo with more than 30 different exemplars (see [Chua et al., 1993] for a nice collection of color plates corresponding to all these attractors). From an integrated design perspective, canonical systems deserves special attention: Since system parameters must be mapped into physical devices, those models with a minimum number of nonzero parameters will be a priori the most advantageous in terms of system complexity and area consumption. In our design, we have taken advantage of the topological conjugacy property of canonical systems in , not to reproduce as much as possible dynamic behaviors, but to identify which of these systems is the best suited for the monolithic implementation of a particular chaotic attractor. Accordingly, the behavioral level description of our prototype have been obtained after applying the following algorithm: • Calculate the eigenvalues associated with the system candidate in whose attractor is to be reproduced by canonical systems, up to topological conjugacy. • Identify the parameter values which must take every canonical system in so that corresponding eigenvalues coincide with those obtained in the previous step. • Select that canonical system of those previously identified which satisfies as close as possible a set of optimization criteria derived from microelectronic experience. 5. Properly speaking, canonical systems are said to be topologically conjugate to the class , where is a set of zero measure. U+1 xℜ3 ∈D†xBp ={}= U1– xℜ3 ∈D†xBp –={}= L3 µ1µ2and µ3 , F() ν 1ν2and ν3 , L3L3 L3 L3 ˜L3ε0 –= ε0 L3 L3 L3 L3 International Journal of Bifurcation and Chaos 41 Let us examine each step of the algorithm. The first step begins with the selection of the particular chaotic attractor to be synthesized. Among the wide number of candidates offered by the family , we have considered the so-called double-scroll attractor, shown in Fig.34, which arises from the well-known Chua´s circuit [Chua, 1992]. The reasons behind this election is threefold. First, and most important, because there are several experimental evidences using discrete components that the model allows the observation of chaos synchronization phenomena. Second, because there is an extense theoretical background concerning its dynamic behavior [Madan, 1993], what supposes an invaluable help during the synthesis root towards an integrated prototype. Finally, because it is one of the simplest models proposed so far for the generation of chaotic signals, and a priori, will result in a easier silicon implementation. It is worth noting that the double-scroll attractor has been previously synthesized by microelectronic circuits (in fully monolithic form in [Rodríguez-Vázquez & Delgado-Restituto, 1993] and in partial monolithic form in [Cruz & Chua, 1993]). A common feature of both chips is that their behavioral level description were derived directly from Chua´s circuit, and hence, no attempt of performance optimization from an IC design viewpoint was done. L3 F ig. 34. The Chua’s double-scroll chaotic attractor. 48 Bifurcations and Synchronization using an Integrated Programmable Chaotic Circuit tronic Circuits,” Part A: Tutorials and Reviews, IEEE Trans. on Circuits and Systems-I 40(10); Part B: Bifurcation and Chaos, IEEE Trans. on Circuits and Systems-I 40(11); Part C: Applications, IEEE Trans. on Circuits and Systems-II 40(10). Chua, L. O., Wu, C. W., Huang, A. & Zhong, G.-Q. [1993] “A Universal Circuit for Studying and Generating Chaos -- Part I: Routes to Chaos, and Part II: Strange Attractors,” IEEE Trans. on Circuits and Systems-I 40(10), 732-761. Cruz, J. M. & Chua, L. O. [1993] “An IC Chip of Chua’s Circuit,” IEEE Trans. on Circuits and Systems-II 40(10), 614-625. Delgado-Restituto, M., Rodríguez-Vázquez, A., Espejo, S. & Huertas, J. L. [1992] “A Chaotic Switched-Capacitor Circuit for 1/f γ Generation,” IEEE Trans. on Circuits and Systems 39(4), 325-328. Delgado-Restituto, M., Medeiro, F. & Rodríguez-Vázquez, A., [1993] “Nonlinear SwitchedCurrent CMOS IC for Random Signal Generation,” Electronic Letters 29(25), 2190-2191. Delgado-Restituto, M. & Rodríguez-Vázquez, A., [1994] “Switched-Current Chaotic Neurons,” Electronic Letters 30(5), 429-430. Freeman, W. J. [1992] “Tutorial on Neurobiology: From Single Neurons to Brain Chaos,” Int. J. Bifurcation and Chaos 2(3), 451-482. Hasler, M. [1994] “Synchronization Principles and Applications”. Proc. of the 1994 IEEE Int. Symp. on Circuits and Systems (Tutorials), Chapter 6.2, 314-327. Hein, S. [1993] “Exploiting Chaos to Suppress Spurious Tones in General Double-Loop SD Modulators,” IEEE Trans. on Circuits and Systems-II 40(10), 651-659. Horio, H. & Suyama, K. [1995] “Experimental Verification of Signal Transmission Using Synchronized SC Chaotic Neural Networks,” IEEE Trans. on Circuits and Systems-I 42(7), 393-395. Kocarev, L. J., Halle, K. S., Eckert, K., Parlitz, U. & Chua, L. O. [1992] “Experimental Demonstration of Secure Communications via Chaotic Synchronization,” Int. J. Bifurcation and Chaos 2(4), 709-713. Madan, R. N. (editor) [1993] Chua’s Circuit: A Paradigm for Chaos (World Scientific, Singapore). Matsumoto, G., Aihara, K., Hanyu, Y., Takahashi, N., Yoshizawa, S. & Nagumo, J. [1987] “Chaos and Phase Locking in Normal Squid Axons,” Phys. Lett. A123, 162-166. International Journal of Bifurcation and Chaos 49 McGonigal, G. C. & Elmasry, M. I. [1987] “Generation of Noise by Electronic Iteration of the Logistic Map,” IEEE Trans. on Circuits and Systems 34(8), 981-983. Murch, A. R. & Bates, R. H. T. [1990] “Colored Noise Generation through Deterministic Chaos,” IEEE Trans. on Circuits and Systems 37(5), 608-613. Nozawa, H. [1992] “A Neural Network Model as a Globally Coupled Map and Applications based on Chaos,” Chaos 2(3), 377-386. Oppenheim, A. V., Wornell, G. W., Isabelle, S. H. & Cuomo, K. M. [1992] “Signal Processing in the Context of Chaotic Signals,” Proc. IEEE Int. Conf. on Acoustics, Speech and Signal Processing IV, 117-120. Rodríguez-Vázquez, A., Huertas, J. L., Rueda, A., Pérez-Verdú, B. & Chua, L. O., [1987] “Chaos from Switched-Capacitor Circuits: Discrete Maps”. Proceedings of the IEEE 75(8), 1090-1106. Rodríguez-Vázquez, A., Espejo, S., Huertas, J. L. & Martin, J. D. [1990] “Analog Building Blocks for Noise and Truly Random Number Generation in CMOS VLSI,” Proc. European Conf. on Solid-State Circuits, 225-228. Rodríguez-Vázquez, A., Delgado-Restituto, M., Espejo, S. & Huertas, J. L. [1991] “Switched Capacitor Broadband Noise Generator for CMOS VLSI,” Electronic Letters 27(21), 1913-1915. Rodríguez-Vázquez, A. & Delgado-Restituto, M. [1993] “CMOS Design of Chaotic Oscillators Using State Variables: A Monolithic Chua’s Circuit,” IEEE Trans. on Circuits and Systems-II 40(10), 596-613. Rodríguez-Vázquez, A. & Delgado-Restituto, M. [1994] “Generation of Chaotic Signals using Current-Mode Techniques,” J. of Intelligent and Fuzzy Systems 2(1), 15-37. Schreier, R. [1991] “Noise-Shaped Coding,” Ph. D. Thesis, University of Toronto. 50 Bifurcations and Synchronization using an Integrated Programmable Chaotic Circuit FIGURE CAPTIONS Fig. 1. (a) Chip architecture; (b) Experimental setup showing oscilloscope, chip with four tuning resistors, and the battery pack. Fig. 2. Nonlinearity of the chaotic oscillator. Fig. 3. Variation of the PWL characteristics of the nonlinearity with: (a) ; (b) ; (c) the central slope, (control variable ); and (d) the outer slopes, (control variable ). Fig. 4. Automatic Tuning Mechanism. Fig. 5. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , . Fig. 6. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , . Fig. 7. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , . Fig. 8. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , . Fig. 9. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , . Fig. 10. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , . Fig. 11. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , . Fig. 12. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , . Fig. 13. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , . Fig. 14. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , . Fig. 15. Experimental Lissajous figures, state waveforms, and power spectrum of the Icont1 Icont4m0Icont2m1 Icont3 x1Icont21.0 µA=Icont32.35 µA= x1Icont21.04 µA=Icont32.35 µA= x1Icont21.065 µA=Icont32.35 µA= x1Icont21.07 µA=Icont32.35 µA= x1Icont21.12 µA=Icont32.35 µA= x1Icont21.135 µA=Icont32.35 µA= x1Icont21.15 µA=Icont32.35 µA= x1Icont21.24 µA=Icont32.47 µA= x1Icont21.47 µA=Icont32.56 µA= x1Icont21.62 µA=Icont32.56 µA= International Journal of Bifurcation and Chaos 51 variable for , . Fig. 16. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , . Fig. 17. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , . Fig. 18. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , . Fig. 19. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , . Fig. 20. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , . Fig. 21. Experimental Lissajous figures, state waveforms, and power spectrum of the variable for , . Fig. 22. (a) Experimental setup for an -linear coupling synchronization scheme; (b)-(c) Correlation indexes between and , respectively. Fig. 23. Synchronization performance of the -linear coupling system for . Fig. 24. Measurements from an -linear coupling synchronization scheme. (a)-(b) Correlation indexes between and , respectively. (c)-(d) Synchronization performance for . Fig. 25. (a) Master-Slave simplified experimental setup; (b)-(c) Measured performance. Fig. 26. Synchronization performance of the -drive system. Fig. 27. (a) Simplified experimental setup for the inverse system approach; (b) Measured performance. Fig. 28. Power spectra of the (a) input signal; (b) transmitted signal; and (c) recovered signal. Fig. 29. Time-domain performance of the chaotic modulation synchronization scheme using two integrated prototypes. Fig. 30. Correlation index between the input and the recovered signals. x1Icont21.60 µA=Icont32.58 µA= x1Icont21.65 µA=Icont32.61 µA= x1Icont21.70 µA=Icont32.61 µA= x1Icont21.72 µA=Icont32.63 µA= x1Icont21.79 µA=Icont32.66 µA= x1Icont21.81 µA=Icont32.66 µA= x1Icont21.85 µA=Icont32.66 µA= x1 x 12 buf,x22 buf, – x 13 buf,x23 buf, – x1 R1200kΩ= x2 x 11 buf,x21 buf, – x 13 buf,x23 buf, – R225kΩ= x2 52 Bifurcations and Synchronization using an Integrated Programmable Chaotic Circuit Fig. 31. Correlation index between the input and the transmitted signals. Fig. 32. Synthesis route towards monolithic nonlinear circuits. Fig. 33. Block diagram for the members of the family . Fig. 34. The Chua’s double-scroll chaotic attractor. Fig. 35. Evolution of the linearized system eigenvalues with parameter . Fig. 36. (a) Gm − C block diagram of the core chaotic oscillator; (b) Ideal model for the linear transconductors; (c) Ideal model for the PWL blocks. L3 m