A new nonlinear time-domain op-amp macromodel using threshold functions and digitally controlled network elements

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, RO. 4, AUGUST 1988 959 A New Nonlinear Time-Domain Op-Amp Macromodel Using Threshold Functions and Digitally Controlled Network Elements BELEN PEREZ-VERDU, JOSE L. HUERTAS, MEMBER, IEEE, AND ANGEL RODR~GUEZ-VAZQUEZ, MEMBER, IEEE Abstract -In this paper we present a new general-purpose nonlinear macromodel for the time-domain simulation of integrated circuit operational amplifiers (op amps), either bipolar or MOS. We can mention three main differences between this macromodel and those previously reported in the literalure for the time domain. First, all the opamp nonlinearities are simulated using threshold elements and digital components, thus making the macromodel well suited for a mixed electrical/ logical simulator. Second, the new macromodel exhibits a superior.performance in those cases where the op amp is driven by a very large signal. Finally, the macromodel is advantageous in terms of CPU time. Several examples are included illustrating all of these advantages. The main application of this macromodel is for the accurate simulation of the analog part of a combined analog/digital integrated circuit. I. INTRODUCTION S digital/analog integrated systems are becoming A more and more popular, the demand for simplified but still accurate models which handle analog subsystems is continuously growing. Analog chip designers ask for models that allow them to combine as much accuracy as possible with a maximum simulation speedup. Resorting to macromodels instead of device-level models is a widely used strategy that allows the designer to reduce the high computation time required when simulating complex systems. This is particularly true in many analog applications where the basic component is the operational amplifier (op amp). Op amps are usually composed of 15-30 transistors and, in circuits incorporating tens (or even hundreds) of them, considerable savings in time can be obtained using a macromodel. A secondary advantage of macromodels is that determining the parameters of every op-amp circuit component (transistor, capacitor, etc.) is not needed. Since macromodels only reflect the input-output behavior of the op amp, the macromodel parameters can be calculated from measurements made at the op-amp terminals. Finally, it is worthwhile to mention Manuscript received February 13, 1987; revised November 10, 1987. The authors are with the D artamento de Electricidad y Electrbnica, IEEE Log Number 8821659. Facultad de Fisica, Universid2 de Sevilla, 41012 Sevilla, Spain. that macromodels allow us to derive meaningful design equations in many practical cases where device-level models are senseless due to their inherent high complexity. Several op-amp macromodels have been reported in the past [1]-[MI, [21], [22]; but only some are intended for nonlinear transient simulation [1]-[7], [18], [21], [22], the others being exclusively valid or intentionally oriented for the frequency domain [8]-[17]. However, two points must be put in the foreground with respect to these time-domain macromodels. First, they have been developed at a circuit level, this fact rendering them specially suited for electrical simulators (like SPICE2 [23]) but not adequate for timing or switch-level programs. Second, some of them exhibit specific problems in those cases where very large amplitude driving signals are involved [19]. In particular, these limitations have considerable influence in nonlinear applications, such as oscillators, A/D converters, etc. In modem-day integrated systems, where digital and analog circuits coexist on the same chip, both drawbacks become more and more important. On the one hand, a switch-level simulator would be able to handle this kind of complex system in a more efficient way; on the other hand, those systems have to be adurately analyzed although they are very nonlinear in nature. This paper addresses both points. Section I1 gives a critical view of op-amp macromodels in the time domain. Based on those criticisms, Section I11 develops the basis for a new macromodel suited for timing simulators. Finally, Section IV presents results showing the relative performance for the new macromodel as compared with the ones previously reported in the literature. 11. A CRITICAL GLIMPSE AT OP-AMP MACROMODELS Actual op amps differ significantly from their ideal behavior in many aspects. Let us focus on the most important of these nonidealities, namely, the frequencydependent voltage gain, the finite input and output resistances, the offset voltage, the slew-rate limitation, and the 0018-9200/88/0800-0959$01.00 01988 IEEE Authorized licensed use limited to: Universidad de Sevilla. Downloaded on March 19,2020 at 15:40:36 UTC from IEEE Xplore. Restrictions apply. 960 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO. 4. AUGUST 1988 * tio I 0 E+ Fig. 1. Conceptual op-amp macromodel using nonlinear-controlled sources [l]. slope Ga 1 I Fig. 1. Conceptual op-amp macromodel using nonlinear-controlled sources [l] Fig. 2. Circuit diagram of the op-amp macromodel by Weil and McNamee [7] 'DD 1 -'ss Fig. 3. Circuit diagram of the MOS op-amp macromodel by Turchetti and Massetti [SI. output voltage-saturation mechanism.' Essentially, all of the previously reported macromodels [1]-[7], [18], [21], [22] are based on a dominant storage element (a linear capacitor) and use some linear-controlled sources for modeling the frequency-dependent gain. However, they differ significantly in the devices used to represent both the slew rate and the voltage saturation. Since the way they represent such nonlinearities has a big influence on our ability for using each macromodel in a given simulator, it is worth discussing the different implementation alternatives. Namely, we will consider the following: 'In MOS amplifiers, the settling time is a very important parameter. However, it can be calculated from the slew rate and the frequencydependent gain [5]. Class Z - macromodels based on nonlinear-controlled sources 111, [2], a typical example of whch is shown in Fig. 1; Class IZ - macromodels using semiconductor diodes [6], [7], the most representative being the one shown in Fig. 2 [7]; and Class III -macromodels resorting to twoand threeterminal semiconductor devices [ 31-[5], as the one shown in Fig. 3 [5]. Macromodels from Class I cannot be incorporated into general-purpose simulation programs because nonlinearcontrolled sources are not available in those simulators. On the contrary, such macromodels are the most adequate for design purposes, since closed expressions can be deAuthorized licensed use limited to: Universidad de Sevilla. Downloaded on March 19,2020 at 15:40:36 UTC from IEEE Xplore. Restrictions apply. P~ZREZ-VERD~ et ai. : NONLINEAR TIME-DOMAIN OP-AMP MACROMODEL 961 Fig. 4. Simplified Weil-McNamee macromodel for modeling the frequency-dependent gain, the slew rate, and the output-voltage saturation. rived more easily for circuits where the op amp is represented by controlled sources than for those where macromodels of the other classes (using semiconductor devices) are used. A typical macromodel from Class I1 is the one proposed in [7], which is shown in Fig. 2; a simplified version, which only covers the aspects we are interested in, is represented in Fig. 4. Qualitative as well as quantitative simulation results can be read from [19], and we must assert that, in our experience, it fits well with the examples we have tried. However, two drawbacks are worth consideration in this case. First, this macromodel uses semiconductor diodes for simulating the static and dynamic nonlinearities of an op amp; since semiconductor devices other than MOS transistors are not available in many timing simulators, the range of usefulness of this macromodel is restricted to electrical simulators, which are not well-suited for combined digital/analog systems. Of course, diodes can be substituted by diode-connected MOS transistors, but if this is the case, we will handle again a high number of transistors. The second problem is concerned with the diodes themselves because of the exponential nature of the diode function. Thus, a trade-off must be established between accuracy and speed for any situation. In principle, macromodels pertaining to Class 111 can be exclusively used at the electrical level (in SPICE2 [23], for instance) because bipolar devices are not available at a higher abstraction level. However, in some cases [5] we can resort to either electricalor switch-level (DIANA [24], SPLICE [25], etc.) simulators, since a model for the MOS transistor is usually included in these two simulation levels. Anyhow, in the latter case: 1) the overall simulation accuracy is very much dependent on the MOS model itself, this model being much more precise at the electrical level than at the switch level; 2) the number of three-terminal devices means a relatively high calculation overhead as well as the need of determining many parameters; and 3) since diodes have to be simulated by MOS transistors, a difficult compromise between accuracy and speed must be established a priori. In fact, each macromodel class is different from the others in its particular way of charging a linear capacitor and modeling the nonlinear dynamics of the op amp. Thus, the general working principle of both Classes I1 and I11 can be roughly understood from the study of the conceptual model included in Class I. Therefore, although Jl slope G Yl 1 slope 1 Fig. 5. Simplified conceptual o amp macromodel for modeling the frequency-dependent gam, the sfiw rate, and the output-voltage saturation. there is an intimate connection among the three classes, in the next section we will pay attention to the first one because we will derive a new interesting class from it. 111. A NEW MACROMODEL FOR THE TIME DOMAIN A. Objectives Evolving from considerations made in the preceding section, we faced the problem of developing a new timedomain macromodel following three guidelines: 1) the macromodel has to be built from the component set available in a timing or switch-level simulator, i.e., two-terminal linear elements, linearly controlled sources, switches, digital gates, etc.; the new model must be able to handle both the lowand the high-frequency range of the op-amp behavior, including its nonlinearities. That means potential for accurate nonlinear transient analysis; and the macromodel must retain a basic analytical form, thus allowing formulation of meaningful design equations for any practical circuit composed of op amps. 2) 3) These three objectives can be reached when a Class I macromodel is modified in two ways: first, eliminating some drawbacks of that model due to an incomplete representation of its dynamics, and second, implementing the model nonlinearities by using a combination of linearcontrolled sources, switches, and digital gates. Authorized licensed use limited to: Universidad de Sevilla. Downloaded on March 19,2020 at 15:40:36 UTC from IEEE Xplore. Restrictions apply. 962 IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 23. NO. 4. AIJGIJST 1988 - - (b) macromodel. Fig. 6. Wien-Bridge oscillator: (a) circuit diagram; and (b) conceptual B. Inaccuracies in Class I Macromodels A macromodel of Class I is shown in Fig. 1 [l]. This model is simplified for our purposes in Fig. 5, where the circuit elements used to represent the input and output resistances as well as the hgher frequency poles of the op amp have been dropped for simplicity, since they are not important in ths discussion and can be added very easily. Let us consider the Wien-Bridge oscillator shown in Fig. 6(a). Fig. 6(b) depicts an equivalent circuit when the macromodel in Fig. 5 is employed for substituting the op amp. A routine analysis gives the state equations for the network: where (3) (4) fc(x) =:[Ix + E-1IX - E+(+ E+ - E-]. (6) We have proceeded to design and build up several oscillators, by changing K and the RC product. These circuits were based on the use of pA741 op amps, whose TABLE I EXPERIMENTAL RESULTS AND SIMULATION RESULTS USING THE DIFFERENT OSCILLATION FREQUENCIES MODEL IN [I] FOR THE WIEN-BRIDGE OSCILLATOR AND FOR I Design values 1 Experimental results I Simulation results I Errors, Yo I parameters were measured in the laboratory. When the above general equations are simulated using a fourth-order Runge-Kutta integration algorithm, the result is Table I, which gives a comparison between predicted and empirical data for the actual oscillators that were under study. In all the cases, the value of the amplitude corresponds to the signal uc2 measured at the positive input lead of the op amp. The op-amp output voltage saturation levels were = - + 15 V. For low oscillation frequencies ( G 12.2 kHz in our case), the output of the op amp is saturated and an important disparity between simulation and experience is exhibited. On average, an error higher than 20 percent could be expected in both the frequency and the amplitude of the oscillations. For hgh frequencies (212.2 kHz), the accuracy in the calculation of the frequency increases a lot (average error of 0.7 percent) while the improvement in the accuracy of the amplitude is not significant. A qualitative interpretation of these disparities can be derived from Fig. 7, where some interesting waveforms are plotted for both an experimental circuit (Fig. 7(a)) and its simulated counterpart (Fig. 7(b)). These signals correspond to the Wien-Bridge oscillator in Fig. 6(a) with the design parameters trimmed to be K = 3.5 and (1/RC) = 11 915 s-'. For the sake of clarity we have divided the time axis in Fig. 7 into several intervals, whch are associated with different mechanisms during the network operation. Thus, inside (a, b) the circuit and its model are operating in the positive output saturation region. After the time instance t = b there is an important disparity between the two entities, since the actual circuit goes out of saturation while the model still remains in saturation until the time instance t = b'. A similar situation happens in the negative saturation region. Looking at Fig. 6(b), we postulate that the delays appearing in the simulation could be due to the accumulation of a supplementary charge in the capacitor C, during the time interval in which the output of the op amp is saturated, accumulation which does not correspond to a physical mechanism. In other words, the disparities are due to the absence in the macromodel of a circuit element that can stop the process of delivering charge to C, when the output saturation is reached. Authorized licensed use limited to: Universidad de Sevilla. Downloaded on March 19,2020 at 15:40:36 UTC from IEEE Xplore. Restrictions apply. P~REZ-VERD~J et ai.: NONLINEAR TIME-DOMAIN OP-XMP MACROMODEL 963 vol volta 7- ~ V I I d L t I (a) (b) Fig. 7. (a) Experimental waveforms measured from the circuit in Fig. 6(a) for K = 3 5 and (l/RC) = 11 915 SKI; and (b) corresponding simulated waveforms obtained from the model in Fig. 6(b). I 1 t fa(*' Fig. 8. Modified conceptual op-amp macromodel. C. Basic Digital& Controlled Macromodel gain, the different op-amp nonlinearities being modeled by digitally controlled analog switches. Let us explain in more Turning back to the conceptual model in Fig. 5, we will detail the of these nohearities. consider first the introduction of a network mechanism for = limiting the charge of capacitor ca. It Can be done bY is implemented in Fig. 9 by a linear voltage-conconnecting a nonlinear resistor across this resistor trolled current source,.. two constant current sources, and having the CUrrent-VOltage characteristic Shown in Fig. 8. the three switches labeled s,, s,, and s,, are However, the model in Fig. 8 is not adequate for Our controlled by the digital variables Z,, Z,, and Z,, respecPurposes be~ause: a) it relies On ~~nh~-contro~led tively. These digital variables are generated by the circuit sources, not available in timing ShUlatOrs, and b) it is in Fig. 9(b), which employs two threshold elements. When prone to numerical latch-up [19]. the op-amp differential input is higher than d+, switch S, In order to Circumvent both drawbacks We propose to is closed and switches s, and s, are open. Then, the use the threshold elements introduced by Arnout and current charging c, is 1,.2 When the op-mp input is de Man for modeling digital MOS circuits [20]. These lower than - d-, the charging current is 1. Finally, if the lators [24], [25]. For the we will charging current depends linearly on U,. It should be noted that asymmetries in the slewing behavior are modeled by reproduce herein the definition of such elements. this circuit by means of the two constant sources (I, and The nonlinear voltage-controlled current source, kinds of components are available in several timing simuinput voltage is in the interval f (- d-, d+ ), the Of Definition I: I,) and two switches (S, and S,). This allows a slew (74 Here we assume that the current flowing through the resistor R, is = TR(u" E ). (7b) neilected. As a matter of fact, the highest value of this current is given by E+/R,, while the value of I, is given by I, - SR+C,, where SR' is the properly designed op amp, we can neglect the current fl&&g throuz U, > E { y: elsewhere linearly controlled source for modeling the low-frequency qi!(ut, E) = Fig. 9 shows the new macromodel. Note that we use a Value of the POSitive-go~g slew rate. As SR+ E+/(R c for eve R,. Authorized licensed use limited to: Universidad de Sevilla. Downloaded on March 19,2020 at 15:40:36 UTC from IEEE Xplore. Restrictions apply. 964 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO. 4, AUGIJST 1988 V ?+ 22 'a "a z3 (b) (C) (4 Fig. 9. Basic digtally controlled op-amp macromodel: (a) circuit diagram using analog switches; (b) electrical to logical converter for obtaining the variables Z,-Z,; (c) electrical to logical converter for obtaining Z,; and (d) truth table for the digital part of the circuit in Fig. 9(c). I , I Input I va I Intermediate/ vc I Output I 8 tage stage stage A 6 e - V. electrical-logical Control stage level "0 Fig. 10. Conceptual block diagram showing the architecture of the macromodel proposed in this paper. enhancement in one direction and a slew degradation in the other, as is observed in practice [26]. The other nonlinearities are implemented by the switch SI, the corresponding control circuit being the one shown in Fig. 9(c). Since S, is connected in series to the capacitor, no charge is flowing into Ca in the case when U, is at one of the output saturation levels. Thus, both the output-voltage saturation mechanism and the charge limitation mechanism are simultaneously implemented by S,. For a better understanding of how the controlling circuit of ths switch works, we must refer to Fig. 9(d), where its truth table is represented. From this last figure, we see that the logic variable depends on both the op-amp differential input voltage and the op-amp output voltage. The dependence on U, is obtained through the upper threshold elements, while the dependence on ua is obtained via the lower ones. The different element values for the basic macromodel can be calculated from the data sheets using the following equations: (8) Ga - = Aowl ca (9) If Ir 'a 'a d-=f=- (10) GaRa = A, - SR' - = SR_I SRI, SR' d+=-=- 'a '001 Ga A0w1 where A, is the dc gain of the op amp, w1 is the lowfrequency pole, and SR' (alternatively SR-) is the positive-going (negative-going) slew rate. D. Extending the Capabilities of the Macromodel Note from Fig. 9 that there are four different stages in the new macromodel. A block diagram illustrating the way these stages are interconnected is shown in Fig. 10, where Authorized licensed use limited to: Universidad de Sevilla. Downloaded on March 19,2020 at 15:40:36 UTC from IEEE Xplore. Restrictions apply. PBREZ-VERD~ er al. : NONLINEAR TIME-DOMAIN OP-AW MACROMODEL 965 Rid/2 - c v. * 4 Fig. 11. Circuit diagram for the input stage of the enhanced macromodel. + V Q, GbVb - Fig. 12. Circuit diagram showing the intermediate stage to be used in case a hi frequency pole is included in the small-signal frequency response of the macromodef? we distinguish two different levels: a) an electrical level comprising the input, intermediate, and output stages, and b) an electrical-logical level comprising the control stage. The different stages in either the electrical or the electrical-logical level are connected by voltage-controlled sources. In the next paragraphs we will show how to modify the different stages in order that all the relevant characteristics of the op-amp performance-with the exception of noise and thermal effects-can be modeled in a way compatible with timing simulators. I. Modifications of the Input Stage: Taking into account considerations reported elsewhere [7], [15]-[18], we propose the input stage shown in Fig. 11. It simulates the finite input bias current, the offset voltage, the commonmode gain, the differential-mode input resistance, and the common-mode input resistances. By elementary analysis of the circuit in Fig. 11 and assuming G,, e 2, we find U+ + ul: .,=(U' -U1:)+- 2 and thus it follows that 1 Gcm = - CMRR = V,, = offset voltage (12) where both the common-mode rejection ratio (CMRR) and the offset voltage can be read from the op-amp data sheets. With regard to the other elements appearing in Fig. 11, their values can be directly obtained from the corresponding parameters in the data sheets. 2. Modifications of the Intermediate Stage: The smallsignal frequency response of the basic macromodel in Fig. 9 is given by a1 which accounts for a phase shift of 90" at the unity-gain frequency, i.e., at a frequency such that lA(juOdB) = 11. The excess phase shift appearing in practical op amps can be modeled by including one or more high-frequency poles in the macromodel frequency response. Fig. 12 shows the intermediate stagerfix a case in which a two-pole behavior is exhibitedadditional high-frequency poles can be included by adding more stages as the one on the right side of Fig. 12. The small-signal frequency response of a macromodel including the intermediate stage of Fig. 12 is given by - A0 - CI b A(s) = (1 + sRaCu)(l + sRbcb) [I+ :][I+ ;] . (14) If we choose GbRb = 1, then @)-(lo) are still applicable. The values of the elements Rb, Gb, and cb can be calculated using 1 R,= - O2'b 1 Authorized licensed use limited to: Universidad de Sevilla. Downloaded on March 19,2020 at 15:40:36 UTC from IEEE Xplore. Restrictions apply. 966 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO. 4, AUGUST 1988 Gv Fig. 13. Alternative circuit diagrams for the output stage of the enhanced macromodel: (a) circuit for modeling the finite output resistance; and (b) circuit for modeling both the finite output resistance and the high-frequency pole. where the value of w2 can be either read from the data sheets or calculated using the unity-gain frequency wo,, and the phase margin am. As a matter of fact, assuming w2 >> wl, we get 1 OdB w21 = -tg [ ; - am]. w 3. Modifications of the Output Stage: In Fig. 13 we show two alternatives for modeling op-amp output stages. In both cases, we assume that the dc gain of the output stage is unity, i.e., we choose GcRo=l, which ensures that (8)-(10) remain valid. Note that the circuit in Fig. 13(b) introduces a high-frequency pole in the small-signal op-amp frequency response. Thus, it can be used as an alternative way to include the second pole influence, instead of using the intermediate stage in Fig. 12. This alternative scheme is specially suited for those cases where only capacitive loads are significant, as happens in MOS op amps used in switched-capacitor circuits. The design equations are the following: where (17a) is valid for both circuits in Fig. 13 and (17b) is only valid for the one in Fig. 13(b). In the latter case, C, is the load capacitor and a, can be either directly read from the data sheets or calculated using (16). 4. Modifications of the Control Stage: The modifications of the control stage to be considered herein account for a more detailed modeling of the op-amp dynamic behavior when the output voltage is at any of the saturation states (either positive or negative), and it is driven out of this state. This has not yet been studied in detail, but in some cases it becomes important enough to justify its modeling. For instance, in [19] we have shown that frequency errors can appear when designing op-amp-based oscillators if these dynamics are not taken into account. Also, we have found that the effect of this is a time delay when leaving the saturation region. That delay is not symmetric; instead, it is in general different for the positive-going output and Fig. 14. Circuit diagram for a positive gain amplifier reahzed using an OP amp. for the negative-going one. The way we have chosen for incorporating this effect is a delay associated with the logic variables labeled as K, and K, in Fig. 9. It can easily be included in the model for the logic elements used in DIANA. IV. MACROMODEL PERFORMANCE The validation of a new macromodel has to be done at different levels. First of all, we need to investigate the qualitative and the quantitative performance of the model referred to the electrical characteristics of actual op amps. A second point is the comparison between the macromodel and device-level models, the keys being here the accuracy as well as the simulation speedup. Finally, the performance and properties of the new macromodel have to be compared with those from other macromodels previously proposed in the literature. Concerning these aspects, we have carried out many experiments. In particular we will include herein several examples that we consider significant for validating our macromodel. A. Positive Gain Amplifiers The circuit of Fig. 14, for a value of K = 3.5, has been built using off-the-shelf components (pA741 for the op amp). The agreement between the circuit and the model performances was found to be excellent; specifically, Fig. 15 shows a case for which other op-amp macromodels are less accurate than ours, namely, for a 10-V square wave of 10 kHz. Fig. 15(a) corresponds to the experimentally observed output waveform, Fig. 15(b) depicts the response for one of those macromodels-in this case, it was obtained using the model by Weil and McNamee [7] in SPICE2, and Fig. 15(c) plots the output as obtained by our model when implemented in DIANA. As can be seen from this figure, a delay due to the output saturation dynamics Authorized licensed use limited to: Universidad de Sevilla. Downloaded on March 19,2020 at 15:40:36 UTC from IEEE Xplore. Restrictions apply. P~RL-VERD~J et (11. : NONLINEAR TIME-DOMAIN OP-AMP MACROMODEL 15jvolts/ k-no delay 96 7 0 5E-5 time,sec (C) Fig. 15. Experimental and simulation results for the positive-gain amplifier: (a) measured waveforms showing a delay in the output response corresponding to the falling edge of the input; (b) simulation results obtained using SPICE2 and the model by Weil-McNamee [7]; and (c) simulation results obtained using DIANA and the new model. Fig. 16. Circuit diagram for a phase-compensated positive-gain amplifier [27] is shown by the actual circuit as well as by our macromodel. Weil-McNamee's model fails in exhibiting that effect. Consider now the composite amplifier in Fig. 16 [27]. We have selected K, = K, = 3 and built the circuit by using a pA747. Fig. 17(a) shows the experimental waveforms observed when a sinusoidal input of 6 V and a frequency of 10 kHz is applied. Fig. 17(b) depicts the corresponding waveforms obtained when using our model in DIANA. B. Wien -Bridge Oscillator Using a pA741, we have compared an experimental circuit for the Wien-Bridge oscillator with its model following our approach. A detailed consideration of many circuit value combinations can be found in [19]. Table I1 shows a comparison made by using the macromodels in [l] and [7], the new macromodel, and the empirical results for several designs. The errors in predicting both the amplitude and the frequency of every oscillator prove the superior performance of our approach. Fig. 18 shows the waveforms for a particular design condition, namely for (1/RC) = 71 269 s-l and K = 3.5. Fig. 18(a) corresponds to the experimental result. Fig. 18(b)-(c) has been obtained using special-purpose programs [I 91 and shows the simulation results when using either our model (Fig. 18(b)) or the model in [l] (Fig. 18(c)). Finally Fig. 18(d)-(e) shows the results obtained when using our model in DIANA (Fig. 18(d)) and when using the model in [7] in SPICE2 (Fig. 18(e)). C. A MOS Unity-Gain Buffer The experimental comparisons we have detailed above exclusively deal with bipolar op amps. The new model is also suitable for MOS amplifiers. To illustrate this we have selected one of the four NMOS op amps given in [5], namely, the so-called design D. This is a case where the settling behavior corresponds to a two-pole transient characteristic. The amplifier was connected in a unity-gain configuration and driven by a positive voltage step of 1 V. Authorized licensed use limited to: Universidad de Sevilla. Downloaded on March 19,2020 at 15:40:36 UTC from IEEE Xplore. Restrictions apply.