Analysis and design of the second order delay-lock loop in a CDMA system

ANALYSIS AND DESIGN OF THE SECOND ORDER DELAY-LOCK LOOP IN A CDMA SYSTEM J.J.Olmas, R.Agustf Dept. de Teoria del Senyal i Comunicacions Universitat Polithica de Catalunya (vpc) A@. 30.002, OSOSO Barcelona, SPAIN ABSTRACT In CDMA systems a DLL is used to keep a fine alignment between sequences. The differential equation of an incoherent second-order DLL has been programmed. By numerical simulation we have obtained the Mean *e to Lose Lock of the DLL as a function of the signal to noise ratio in the data bandwidth. This result is important in a mobile environment where a deep fading may result in a practically instantaneous loss of lock. INTRODUCTION CDMA systems require synchronization between the received sequence and the locally generated sequence. Once the coarse alignment of the codes has been achieved, the received code phase has to be tracked in order to compensate for the doppler effect and (or) clock rate mismatch. This is done by means of a Delay-Luck Loop (DLL). Second order DLL's are able to track a frequency error without a constant phase error. This capability is important in CDMA mobile communications, where a first order DLL would easily lose lock, [l]. The differential equation of an incoherent secondorder DLL has been programmed. The program allows us to obtain the maximum frequency offset that the DLL can absorb in terms of the natural frequency of the loop. Knowing this we design the optimum loop filter. We have found a formula that gives the minimum achievable timing jitter in terms of the signal to noise ratio, the product of the VCO frequency stability times the system processing gain and the time offset between the early and late codes in the DLL. The Mean Time to Lose Lock (MTLL) of the DLL is a very importaut design parameter. By numerical simulation we have obtained this parameter as a function of the timing jitter. Furthermore, an exponential regression formula has been obtained from the sample points in order to easily predict the MTLL. Combining this formula with the formula of the jitter we are able to plot the MTLL as a function of the signal to noise ratio in the data bandwidth. This result is again important in a mobile environment where a deep fading may result in a practically instantaneous loss of lock. DLL DESCRIPTION The block diagram of an incoherent DLL is shown in figure 1. b BPSK signal F3gure 1: Block diagram of an incoherent DLL where a(t) is the tmsmitted PN sequence, b(t) is the data sequence and oo and 8 are, respectively, the carrier pulsation and phase. a(t) takes on values from the set 221 0-7803-0673-2192 $3.00 1992 IEEE {*I) each T, seumds (chip period), and b(t) takes on valw from the set {*I) each T d (bit period), whereT,T,. Pisthe~ivsd~ig~lpowermd~istlse propagation delay to which the DLL must lock. n(t) is white gaussian noise with spectral density G,fl =Nd2. In figure 1, 26 is the off& between the early and late codes, and thebandwidthof theband-p~~ filters, B=l/T allows the filtering of the data signal without distortion. The behavior of the DU can be &scribed by a differential equation, [2]: de1 dr -- - - -KPflt) * ( s(e,;S) +N(z) ) a? T, dr (2) In (2), en(s-+)/Tc is the &if? between the Id and the received sequence in chips, ds/& is the initial clock frequency offset, K is the VCO umstant, f(t) is the lowpass filter impulse response, S(e,b) is the .S"-cum and N(t) is noise with spectral density near the origin given by, PI: Y where y=P/N,-,B is the signal to noise ratio in the data bandwidth, and 1-26, (0S;SSO.S) g(b)= ( 0, (6>0.5) The loop W-curve is shown in figure 2. It can be shown that its slope at the origin is 4(I-6). The second order DLL parameters: natural frequency, damping factor and equivalent noise bandwidth axe, respectively: where s1 and s2 are the time constants of the first order active loop filter. Using the bear model, which is valid for le1 -0, is easy to show that the residual jitter in e is 222 1.5 1 9.5 E -9.5 -1 -1.5 -2 -1.5 -I -8.5 E 8.5 1 1.5 2 E 2: "S" curve for 6=0.25,0.50 and 0.75. given by: SIMULATION DESCRIPTION Assuming active first-order loop filter, with a transfer function given by: 0 1 72 F(s)= -+- Sri 71 the differential equation (2) can be written as: v(r)= S(r(t),b) +N(Z) In order to simulate by computer equation (8), we can envisage a recursive method to update e every To seconds, where To is an arbitrary time interval much shorter thau Bil. So, the main loop in the simulation program is equivalent to To seconds of real time. The recursive equation is: c(R+l)= r(k) +To+ -- where k is the present update instant and i is the clock frequency offset. SIMULATION RESULTS To check the validity of our program we have first obtained the simulated DLL behavior during the acquisition process. For example, taking =O. 7071, 6=0.5 and y=IOOdB, figure 3 shows some trajectories of the alignment error and its derivative in the phase plane. Fwre 3: DLL acquisition in the phase plane Similar plots have been obtained for different values of 6. From these results we can state that in the presence of an initial clock frequency offset i and in a noiseless situation, the lock-in of the DLL is not guaranteed unless i/o,<26. This is quite exact for 6<0.5 and somewhat pessimistic for 6>0.5. As the initial clock frequency offset is mainly due to the VCO, we have that with an active loop filter and =O. 7071 there is a lower bound for the noise bandwidth of the loop given by: 0.53 *AfvcO*Rc= 0.53 *Afvco*B-PG (10) BL 1 26 26 where Afvco is the VCO stability and Rc=Ti' is the sequence chip rate. Notice that R, can be expressed as B times the system processing gain (PG). Now, taking (10) with equality and substituting BL/B in (6) we get the expressions for the minimum jitter. I 0.53 ;f7 PG [I+&] (6lO.5) 7 -+-I 1 1 (0.5 < 6 < 1) 26 4~6(1-6)~ (11) where X(O,6) and I-?@) have been evaluated according to (4). Expression (11) gives the minimum achievable jitter unless some special action is taken to reduce the loop bandwidth once the DLL is locked. We have not considered this possibility. Figure 4 shows the jitter as a function of y for different values of 6 and for Afvco.PG=IU3. Dashed curves are for 6<0.5 and continuous line means 620.5. The step in 6 is 0.05. 1.1 I 0.9 0.8 0.7 5 0.6 0.5 0.4 0.3 0.2 0.1 0 t .A -7 -15 -I4 -13 -12 -11 -10 -9 -8 -7 d -5 I (dB) Fm 4: Jitter (in chips) for Afvco.PG= la3 As the loop "S"-curve is not periodic, due to the presence of noise the DLL will sooner or later lose lock. The Mean Time to Lose of Lock (MTLL) is a very important design parameter. We have obtained this magnitude, for the second order DLL, by computer simulation. To obtain the MTLL we run the program until I E I lies outside of the range of values for which the "S"curve is not zero. This is considered as an out-oflock condition and then E is reset to zero and the program is started again. When 100 out-of-lock situations have been counted, the MTLL is approximated by the total processed time (in terms of Bi') divided by 100. Taking Afvco.PG=IU3 we need BL/B=5.3.104 (for 6=0.5) or BL/B=3.533.104 (for 6=0.75) in order to guarantee the lock of the DLL. Assuming these data in figure 5 we plot the logarithm of the obtained MTLL (in terms of Bi') versus the jitter. The square and the triangle marks are the points obtained by simulation. The CUNM presented correspond to an exponential regression that fits quite well to the simulation points. The regression equations are: I 223 1 6 5 A' 53 d IIm 02 I d 9 -I 9.1 6.2 8.3 6.4 6.5 8.6 8.7 8.8 9.9 jitter Now, as BLD is known, combining (12) with the expressions of the jitter (ll), we can plot the logarithm of the kITLLu as a frmction of 7. Figure 6 shows tbedt~ obt.io6d. Infip6 it csnbenoticedthatthe h4TL.L is very dtive to the signal to noim ratio, since a chge of one dB is srdficiglt to have the MTU divided by tea. Another conclusion that can be derived from figure 6 is that the DLL with b=0.75 has a be#er performaace that the DLL with 8=0.5 only for y>-ladB. Thie is cluc to the frrct that, although for the 8ullc jitter the DLL with 6-0.75 has higher MTU than the DLL with 6=0.5, for the 8pme signal to mise ratio it also has a higher midud jitter. The txmsidemd value of 4fvm-~=1u3 may cormpod, for example, to a processing gpin. system with m vco stability of IUS and 2aiB of CONCLUSIONS p&lu~ 5: MTLJ-, in terms of 4". U a function of the jitter 19 : : : : : : : : : ......... ......... A simulation program for the second order DLL has been developed. The program allows an optimum design of the loop low-pass Mter in order to -& the right clock frequency acquisition and minimum residual jitter. The MTLL of the DLL bas also been obtained by compufer simulation for two different shifts between early and late codes. Results show a remarkable btivity to the signal to noise ratio in the dats bandwidth. ......... ......... d ......... ........ :, :::::::::I ......... , ACKNOWLEDGMENT ..... ..... This work has been supported by ALCATEL .... .... .... .... SESA. REFERENCES [l] R.KARMY, B.Z.BOBROVSKY, Z.SCHUSS, "Loss of Lock Induced by Doppler or Code Rate Mismatch in Code Tracking Loops", MILCOM 1987. ......... ......... 3 .'.l*l*l*l.l*l.lt'* -IS -I4 -13 -12 -11 -16 -9 -7 -6 5 7 (dB) prrUre 6: MTLL, in terms of E', as a function of the signal to noise NtiO iog(tLBj - 9.34 (1.27 10-~)~* (b=O.5) iog(tLBj= ii.m-(8.11 10-~p (64.75) (12) 224 [2] A.POLYDOROS, C.L.WEBER, "Analysis and Optimization of Correlative Code-Tracking Loops in Spread-Spectrum Systems", IEEE Trans. on COIUIXI. Vol COM-33, NO.l, 1985.