Design and implementation of a 2048FFT capture spectrum analyzer

MELECON '85/ Volume 11: Digital Signal Processing A. Luque, A. R. Figueiras Vidal, V. Cappellini (eds .) Elsevier Science Publishers B. V. (North·Holland) I© IEEE 1985 295 DESIGN ~ND IMPLEMENTATION OF A 2048 -FFT CAPTURE SPECTRUM ANALYZER M. ~m e ngual, J. Casamajor, G. Vazquez, J. Labarta Depto. Procesado de Se~al en Comunicaciones E.T.S.I. Telecomunicaci6n. Apdo. 30002, 08071 Barcelona, Spain This paper describes the hardware implement.ation of a digital :Spectrum analyzer which, by using a capture process of the signal under processing, performs some non parametric signal processing techniques. All the possibilities to implement a spectrum analyzer will arise to a bank filter analysis approach. When the instrument works as an off-line processor, the bank filter can be a linear transform, which results in a FFT as concerns with the analysis of the power density content of the data sample. Thus the FFT processor can be viewed as a set of equispaced filters with non-ideal cut-off and secondary lobes but optimum to analyze pure tones in a white noise environment. 1. INTRODUCTION Given a random process x ( t) , a way to characterize it is by means the power spectral density. This is an ideal function which relates how the signal power is distributed in the frecuency domain. ~11 the methods for estimating the power spectrum arise from a bank of band-pass filters (although they mustn't be implemented necessarily so). If these filters are signal dependent, parametric methods arise and the non-parametric at any other case. Among the last ones, the most popular are those which make use of the FFT algorithm. One of these methods is the W.O.S.A. (weighting overlapped spectrum averaging). ~nalyzer architecture has been designed to acomplish with this method. The technique to estimate the spectrum by means the W.O.S.A. is the following: given a signal sample record x(n), O.,:n.,:M-1, it is divided into L segments (with possible overlapping between them) of N points each one. Where N is the FFT size that processes the analyzer. Each segment is windowed (three possible windows are available: rectangular, Barlett and Hanning) and FFT processed. Finally, the modified periodograms are averaged, by means of an uniform or exponential averager, to achieve the spectral estimate. 2. IMPLEMENTATION For implementing the W.O.S.A. method, several architecture models are employed, which are complexity-price dependents. If the FFT processor is high speed enough, it could be thought to disposse two memory buffers; while one of them is adquiring signal, CH 2185-7/85/0000-0295(8)/$01.00 ©19851EEE the FfT of the other is the way in which anal yzers. To achieve audio frequencies, it techniques and, in any purpose architectures. one is evaluated. This work real time spectrum real time analysis upon is necessary bit-slice case, the use of special This is a tradeoff when one is not interested in an expensive instrument. The other possibility is that of adquiring the signal under test ("capture"), storing it in a memory buffer and estimating the power spectrum density off-line. An architecture to achieve this idea is much more simple and allows the use of conventional 16 bit microprocessors. Although a ]JP design can't achieve real time processing upon a bandwidth of 20 KHz, however it is possible real time pro·cessing until 2 KHz (depending upon the speed processing and the FFT size). Our design is accordingly with this philosophy. For capturing the signal it is provided 20 K word of static RAM. All the associated functions the analyzer achieves are supported in a 2048 sample FFT. It is well known that spectral resolution is closely related to the inverse of the time domain width of the window. So that spectral resolution in the W.O.S.~. method 1s dependent upon the time duration of the 2048 points. However, because of the 20 K words of signal stored, it is possible throughout the built in "zoom FFT" to achieve a spectral resolution ten times greater the W.O.S.~. Besides, another 12 K word static [lM·I are supported in the basic model to allow intennediate results. ~ further enlargement of 32 K\·1. is foreseen. So it will be possible to slore ideal measurements and compare with actual one's. 296 M. Amengual et al. RAM ~OM ·~u-~tu ::=:::;> kT ~ltloiAL C:otcTil•UJUI. \tlfj C.P.V. I "' .I ;"P. tiC 6IDaO ! IIWU+-- lt&I!&O~O ~ -(- c:.>~.,A.OLJ.QI. 4~ ~ ~ AfniA&.INOiNc; - Sg_ - "'lo T t-1 1011\1 j::j 8 8 1 . ._ _...,, .I +--- <.-. ,...__~ . -- Figure 1. General Block diagram. The ROM memory unit is also 32 KW size. It isn't too large because datum tables must be stored besides references and program itself. The adquisition unit consist in an antialiasing analog filter bank (C.C.D); a sample and hold and a 12 bit A/D converter, from which an input dynamic range of about 72 dB is attained. The analyzer has also been fitted with the IEEEbus, by means of a bus controller chip. So that, it can work as a peripheric from a host computer To perform the different processing possibilities, the user manages the analyzer throughout a key board; so that, the hardware design also incorporates a programmable keyboard controller. Among the features of this keyboard controller chip are: to establish serial communications (RS-232) with peripherical devices, as printers or plotters, and also programable tone generator which sample and hold unit. provides a governs the Gra!=hic results, and different menus are displayed in an intelligent graphic terminal which is ~P controlled (by a Z-80 ~P). Communications between the CPU and the grafic terminal are also provided throughout the IEEEbus. The global architecture of the analyzer can be viewed in figure (1). In this design, the control unit, so as the computational unit is the ~p MC68000. THis CPU disposses of 16 intern registers of 32 bit ( 8 data registers and 8 address registers). Interaction between the adquisition unit or the keyboard and the CPU is achieved by interruptions. While the graphic terminal communications and the RS-232 ones (provided by the keyboard controller) are polling performed. Three internal interrupt levels are allowed. At the higher one, unit adquisi tion and keyboard are disabled; this corresponds to the CPU processing time. At the next level, unit adquis i tion is enabled and keyboard disabled and at the third level, keyboard and unit adquisition are enabled, but only keyboard is functionally enabled because the keyboard clock is reset, so the adquisition unit is in idle state. Communications with a host computer, although, it isn't still software developped, also will Implementation of a 2048-FFT Capture Spectrum Analyzer 297 be interrupt performed vin the IEEE-bus. The presentation unit, i.e. the !Jl-,lphic tet:minal has been designed intelligent (it is supported by a Z-80) to discharge the MC6BOOO from taskes being not typically computationals. This disposses of a graphic screen controller performs a 512 point resolution in the horizontal axis and 256 point resolution in the unit that vertical one. It can be seen at figure 1, that no floatingpoint coprocessor is included. Because of this, all the mathematics operations (either linear or non-linear) must be performed by the 68000 CPU in fixed-point format. Special routines have been developped to evaluate non-linear mathematics functions: logarithms, exponentials and phases. Evaluation of lhal functions is rwt·(ot·mcd with aid [o some significativc values which arc stored in the 110~1 memory . For the logat:ithm evaluation, it has been implemented the algorithm li) log x = log 2 + log x/2 ( 1) This recursion is followed until x is less or equal than a certain value ( 1024), in which case, the logarithm value is found at the table. Exponential recursion is just the inverse than the logarithm one. If xis less than log (1024), then ex may be obtained directly from the logarithms table; if x is greather than log 1024 it will be x=n log 2 + log u, where log u < log 1024, so the problem now is to find e1n u at the table and finally ex=2n e1n u For calculating phases, the algorithm followed has been (2) arc tg x=TT/2 - arc tg 1/x; if x>l ( 2) If x<l then arc tg x is obtained from tabulated values. Obviously, since the CPU works over integer numbers, all numbers that are less than one must be left shifted decimal point stored. Also it is stored in ROM the cosinus and sinus necessary values for computing a 2048 point F.F.T. For computing a 2048 point F.F.T. it is necessary (3). sen 21! i 20411 cos 211 i 20~0 . i =" 0, ... 1023 102 3 It could be sufficient store (4), i.e. a quadrant ( 3) sen 2TT i 2048 ( 4) Out !'or optimicing execution time it has been tabulated (5) scn 21! i 2048 i 0, ... 1535 ( 5) Indexing from i=O sinus are obtained and from i=0+512, cosinus do . Also it has been tabulated the bit-reversed f_ unction. The functions included in software options are: W.O.S.A., signal enhacement, spectrum averaging, zoom-FFT, autocorrelation, Hilbert transform, envelope, instantaneous frequency, minimum phase and complex and real cepstrum. Other graphic features are included which allow online signal edition both in time and frequency do111ain. It is expected to extend the system for performing two channel signal processing.