TA12-384: Enhancing Neuromorphic Tolerance to Radiation through Algorithm-Hardware Linking (ENTHRAL)

https://radnext.web.cern.ch/ https://www.linkedin.com/company/radnext EDMS NO. 3328320 VALIDITY Released REV. 1.0 DOI: 10.5281/zenodo.17288061 RADNEXT Transnational Access Summary Report Project title Enhancing Neuromorphic Tolerance to Radiation through Algorithm-Hardware Linking (ENTHRAL) Project TA identifier TA12-384 General application Space, high-reliability ground level Type of test SEE Group leader, Institute Marco Ottavi Co-authors, Institutes Bruno Endres Forlin, University of Twente Elijah Cishugi, University of Twente Tijmen Smit, University of Twente Date(s) of the experiment 03 May 2025 to 05 May 2025 Facility ChipIR Amount of access granted 48 h Objectives of the experiments This proposal aims to evaluate the reliability of neuromorphic processors against radiation-induced faults. Neuromorphic processors mimic the neural architecture of the human brain and offer efficient, low-power computation across various applications. However, understanding their resilience to radiation is crucial, particularly in critical environments like automotive, space, nuclear facilities, and medical devices. While a few studies have examined their reliability, we focus on iterative design techniques to improve reliability at the architecture level, using Flash-based FPGAs. Neuromorphic processors offer significant advancements in computational efficiency and real-time processing capabilities. However, their unique architecture and algorithmic choices may introduce vulnerabilities to radiation-induced faults that have yet to be fully explored. By leveraging Flash based FPGAs, we aim to more accurately mimic the behaviour of dedicated ASIC units, providing a more reliable assessment of radiation tolerance compared to traditional SRAM FPGA-based evaluations. Experiment test report The experimental setup consisted of 10xSmartFusion 2 Flash FPGAs and 1xPolarFire Flash FPGA. SmartFusions were used to test multiple hardware implementations of hardware accelerators and RISC-V soft cores, the PolarFire FPGA was used to test the performance of online learning for Neuromorphic processing architecture. A brief description of each experiment follows: 1. Validation of probabilistic error detection mechanisms 2. Validation of software reliability mechanisms 3. Characterization of a custom RISC-V operating system EDMS 3328320 v.1 status In Work access Restricted PDF from TA12-384-Zenodo.doc modified 2025-10-07 16:11 https://radnext.web.cern.ch/ https://www.linkedin.com/company/radnext EDMS NO. 3328320 VALIDITY Released REV. 1.0 4. Characterization of online learning on a Neuromorphic processor. Each experiment had multiple configurations to validate different parameters. The measurements from each experiment consisted of performing a specific computation routine with a known result. The output of the computation was transmitted out of the Device Under Test (DUT) via a UART/Ethernet adapter. The validation of the correct result is done entirely in post-processing. A preliminary overview of the results of each experiment follows: 1. This experiment is a follow up from our previous ChipIR campaign. Improvements to the probabilistic structures were implemented and tested. Results are currently being processed, but preliminary results show that the modifications were successful in improving the results from previous campaigns. 2. These experiments were performed in cooperation with the University of Purdue and aimed at validating compiler-based fault reliability methods executing on a RISC-V processor. The results are currently being evaluated by the Purdue team. 3. This custom RISC-V operating system has been in development for the past 3 years. The goal of this campaign was to validate the software detection mechanisms to improve the detection of SDCs that would otherwise be undetectable. The results show that indeed our methodology works and has discovered more errors than it itself caused. A journal paper is currently being written. 4. This work was part of a master thesis assignment. The student implemented neuromorphic computing architecture on a Flash FPGA. Results show that the network is to a certain extent resilient to errors and online learning can improve results, but at the same time, the architecture consists of many ACE bits (critical single points of failure). Therefore, hardening is necessary regardless of training method to maintain a high accuracy. Outcome of the experiments Please indicate what the experiment is likely to lead to by putting an ‘X’ next to one or more of the possible outcomes below. Journal publication x Data for Thesis x Follow-up experiment at same facility x Follow-up experiment at another facility x Other As a RADNEXT user, we encourage you to submit the scientific results of your experiments to journals as well as to the NSREC and RADECS data workshops. Please remember to include the RADNEXT acknowledgment into your publications! RADNEXT acknowledgment: This project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 101008126.