Optimization Techniques for Source Follower Based Track-and-Hold Circuit for High Speed Wireless Communication

International J ournal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, DOI : 10.5121/vlsic.2011.2105 O PTIMIZATION TECHNIQU FOLLOWER BASED HIGH SPEED WIRELESS Manoj Kumar 1 Department of Electronics & Comm., Vidya College of Engg., Meerut (U.P) 2 Department of Electronics & Comm., NIT Hamirpur, Hamirpur (H.P) A BSTRACT Since the current demand for high - need for track and hold amplifiers (T&H) operating at RF frequencies. A circuit is the key element in any modern wideband data acquisition system. Applications like a cable or a broad variety of different radio standards require high processing speeds with high resolution. The track-and-hold (T&H) c ircuit is a fundamental block for analog allows most dynamic errors of A/D converters to be reduced, especially those showing up when using high frequency input signals. Having a wideband and precise acquisition system today’s trend towards multistandard flexible radios, with as much signal processing as possible in digital domain. This work investigates effect of various design schemes and circuit topology for track and-hold circuit to achieve acc eptable linearly, high slew rate, low power consumption and low noise K EYWORDS Track and Hold Circuit , Low Power Consumption, Slew Rate, Analog to Digital Converter 1. I NTRODUCTION Track and hold circuit is the fundam and hold circuit is inserted in front of a comparator array of a flash A/D converter to keep comparator’s input voltages constant while the comparators are settling their output voltage levels. Trac k and hold architecture can be classified into two classes (fig.1): open closed-loop architecture [1]-[5]. Figure 1a. Openloop T/H The open loop T/H circuit is suitable for high precision but not T/H circuits proposed/implemented so far employ closed 8 bit accuracy. However closed loop architectures suffer from relatively lower sampling frequency and higher power consumption as compa ournal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March PTIMIZATION TECHNIQU ES FOR SOURCE FOLLOWER BASED TRACK - AND - HOLD CIRCUIT FOR HIGH SPEED WIRELESS COMMUNICATION Manoj Kumar 1 and Gagnesh Kumar 2 Electronics & Comm., Vidya College of Engg., Meerut (U.P) [email protected] Electronics & Comm., NIT Hamirpur, Hamirpur (H.P) [email protected] - resolution and fast analog to digital converters (ADC) is driving the need for track and hold amplifiers (T&H) operating at RF frequencies. A very fast and linear T&H circuit is the key element in any modern wideband data acquisition system. Applications like a cable or a broad variety of different radio standards require high processing speeds with high resolution. The ircuit is a fundamental block for analog - to digital (A/D) converters. Its use allows most dynamic errors of A/D converters to be reduced, especially those showing up when using high frequency input signals. Having a wideband and precise acquisition system is a prerequisite for standard flexible radios, with as much signal processing as possible in This work investigates effect of various design schemes and circuit topology for track eptable linearly, high slew rate, low power consumption and low noise , Low Power Consumption, Slew Rate, Peak Power, Sampling S Track and hold circuit is the fundam ental block for analog to digital (A/D) converters. Track and hold circuit is inserted in front of a comparator array of a flash A/D converter to keep comparator’s input voltages constant while the comparators are settling their output voltage k and hold architecture can be classified into two classes (fig.1): open loop T/H Figure 1b. Closedloop T/H The open loop T/H circuit is suitable for high precision but not for high speed. Most CMOS T/H circuits proposed/implemented so far employ closed - loop architecture to obtain better than 8 bit accuracy. However closed loop architectures suffer from relatively lower sampling frequency and higher power consumption as compa red to openloop architecture [6]. Open March 2011 45 ES FOR SOURCE HOLD CIRCUIT FOR COMMUNICATION Electronics & Comm., Vidya College of Engg., Meerut (U.P) Electronics & Comm., NIT Hamirpur, Hamirpur (H.P) resolution and fast analog to digital converters (ADC) is driving the very fast and linear T&H circuit is the key element in any modern wideband data acquisition system. Applications like a cable -TV or a broad variety of different radio standards require high processing speeds with high resolution. The to digital (A/D) converters. Its use allows most dynamic errors of A/D converters to be reduced, especially those showing up when using is a prerequisite for standard flexible radios, with as much signal processing as possible in This work investigates effect of various design schemes and circuit topology for track - eptable linearly, high slew rate, low power consumption and low noise . S witch, Flash ental block for analog to digital (A/D) converters. Track and hold circuit is inserted in front of a comparator array of a flash A/D converter to keep comparator’s input voltages constant while the comparators are settling their output voltage k and hold architecture can be classified into two classes (fig.1): open -loop and loop T/H for high speed. Most CMOS loop architecture to obtain better than 8 bit accuracy. However closed loop architectures suffer from relatively lower sampling loop architecture [6]. Open - International J ournal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, loop architectures tend to consume lower power and work at high sampling frequencies than closed-loop ones. Open-loop architectures have been used Source-followerbased T/H circuit has be speed and power consumption. This paper investigates effect of various design schemes and circuit topology for track-andhold circuit to achieve acceptable linearly, high slew rate, low power consumption a nd low noise. Superior speed & makes it promising candidate for the purpose of this work. 2. SAMPLING SWITCHES FO The sampling network consists of a sampling switch (M value of sampled signal during the hold mode. During the tracking phase, the combination of the switch and the capacitor forms a first maximum achievable sampling frequency. The speed of sampling netwo serious limitation in this work because as will be seen the chosen operating frequency is far less than the timeconstant of the switch network and is basically limited by other parts of the circuit [15]. The noise contribution du e to the sampling network is dependent on the sampling capacitance value and the width of the switching transistor. In addition to the noise added by the switch, the non-linearity due to the signal - linearity of the T/H circuit. 2.1. Single MOS Switch The maximum output voltage that an NMOS transistor can deliver is approximately equal to V dd -V th. Figure 2. Single MOS sampling switch The on-resistance of a longchannel MOS device operating in the linear (triode) regions is given by: From the above expression it is clear that the resistance of NMOS a pproaches infinity when Vin approaches Vdd transistor [10]. 2.2. TransmissionGate Switch To circumvent the above problem with a varying switch resistance the benefit of NMOS for low input voltages and the PMOS for connecting them in parallel and thereby forming a transmission gate ournal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 loop architectures tend to consume lower power and work at high sampling frequencies than architectures have been used in highspeed ADCs [3][4]. based T/H circuit has be en optimized with respect to linearity, noise, and This paper investigates effect of various design schemes and hold circuit to achieve acceptable linearly, high slew rate, low nd low noise. Superior speed & acceptable linearity of source makes it promising candidate for the purpose of this work. SAMPLING SWITCHES FO R T / H The sampling network consists of a sampling switch (M sw ) and a hold capacitor (C s ) to store the value of sampled signal during the hold mode. During the tracking phase, the combination of the switch and the capacitor forms a first -order RC network, the timeconstant of which sets the maximum achievable sampling frequency. The speed of sampling netwo rk appears not to be a serious limitation in this work because as will be seen the chosen operating frequency is far less constant of the switch network and is basically limited by other parts of the e to the sampling network is dependent on the sampling capacitance value and the width of the switching transistor. In addition to the noise added by the switch, the - dependent behaviour of the switch can degrade the overall The maximum output voltage that an NMOS transistor can deliver is approximately equal to Single MOS sampling switch channel MOS device operating in the linear (triode) regions is given From the above expression it is clear that the resistance of NMOS switch is nonlinear that is pproaches infinity when Vin approaches Vdd - Vth,which is the upper limit of the NMOS Gate Switch To circumvent the above problem with a varying switch resistance the benefit of NMOS for low input voltages and the PMOS for high input voltages can be Utilized.it is done simply by connecting them in parallel and thereby forming a transmission gate . March 2011 46 loop architectures tend to consume lower power and work at high sampling frequencies than speed ADCs [3][4]. en optimized with respect to linearity, noise, and This paper investigates effect of various design schemes and hold circuit to achieve acceptable linearly, high slew rate, low acceptable linearity of source -followers ) to store the value of sampled signal during the hold mode. During the tracking phase, the combination of constant of which sets the rk appears not to be a serious limitation in this work because as will be seen the chosen operating frequency is far less constant of the switch network and is basically limited by other parts of the e to the sampling network is dependent on the sampling capacitance value and the width of the switching transistor. In addition to the noise added by the switch, the dependent behaviour of the switch can degrade the overall The maximum output voltage that an NMOS transistor can deliver is approximately equal to channel MOS device operating in the linear (triode) regions is given linear that is Vth,which is the upper limit of the NMOS To circumvent the above problem with a varying switch resistance the benefit of NMOS for high input voltages can be Utilized.it is done simply by International J ournal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, Figure 3. Transmission gate sampling switch NMOS transistor shows the non transistor works poorly for high voltages. A PMOS transistor on the other hand , is known to work poorly for low voltages and rather for high voltages. The transmission-gate-switch ( the solution to the problem faced by single NMOS and PMOS switches. As seen in figure, the resistance for the transmission switches can be wise choice to get acceptable li Figure 5. 3. CONVENTIONAL T / H USING SOURCE FOLLO Source follower was used in this work to drive the load c devices in the sourcefollower contribute to the noise in both the track and hold modes of ournal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 Transmission gate sampling switch Figure 4. Onresistance of the transmission gate the non - linear characterisitcs for high voltages. This is why NMOS transistor works poorly for high voltages. A PMOS transistor on the other hand , is known to work poorly for low voltages and rather for high voltages. NMOS-andPMOS transistor connected in parallel the solution to the problem faced by single NMOS and PMOS switches. As seen in figure, the resistance for the transmission -gateswitch is much linear that is why transmission choice to get acceptable li nearty and large output gain [18]. Resistance magnitude of sampling switches H USING SOURCE FOLLO WER Source follower was used in this work to drive the load c apacitance of the T/H stage. The active follower contribute to the noise in both the track and hold modes of March 2011 47 resistance of the linear characterisitcs for high voltages. This is why NMOS transistor works poorly for high voltages. A PMOS transistor on the other hand , is known to PMOS transistor connected in parallel ) might be the solution to the problem faced by single NMOS and PMOS switches. As seen in figure, the switch is much linear that is why transmission -gateapacitance of the T/H stage. The active follower contribute to the noise in both the track and hold modes of International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 48 operation. The noise of these devices mainly due consists of channel thermal noise and gate flicker noise. 3.1. Analysis of T/H Circuit Using NMOS Sampling Switch A conventional source follower T/H circuit basically consists of input, output buffers, a switch and a sampling capacitor. An output buffer is usually used to charge and discharge the input capacitances of following comparators. A T/H circuit has two operation phases named “track phase” and “hold phase”. During a track phase the switch is shorted and V out becomes equal to V in . On the other hand, during a hold phase the switch is opened and the T/H circuit keeps its output voltage equal to the value at end of track phase. A required hold time of a T/H circuit is usually decided by a settling time of the following comparators since the comparators must settle their output voltage during a hold time [9]. Figure 6. Single ended conventional T/H Table 1. Design specification of T/H Power supply voltage 1.8 v Maximum input signal frequency 500 MHz Sampling frequency 1GHz Maximum output voltage swing (Ain) 1 Vp-p Resolution 6 bit Load capacitance (C L ) 10pf Input offset 0.8 v CMOS technology 0.18µm An input voltage represented by     sin     (2) Where A in is equal to the maximum input voltage given by the specifications and ω in is set to 2π ( f s /2 ). f s means its sampling frequency. 3.2. Analytical Modeling of Conventional T/H Circuit Figure 7. Small signal model of conventional T/H International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 49 A Transfer functions from V in to V 1 , and from V 1 to V out is represented by            1 1      1        1 1  3         !    1 1    "  1     1 1  4 Respectively, where   and   is time constant which is defined by     $  % &'   ( ,    * + % & ,  5    ,   "   , 1    . /  . /   . 0      , r 23  .β 4 √ α 4  . β 4 τ  C   6  Where/  , 0  is defined as follows /   89 :; <9 => ?% &'  , 0   " ;@' , A ; 9 BB C > 89 :; <9 D> ?  E ;@' 7 On the assumption that an acceptable gain error at the input buffer of the T/H circuit is e 1 an optimum   must satisfy | T   j ω KLM  |  1 . 1  ω KLM  τ  2  1 P e   8  and v VWX  t   L <  [ 1 1  s τ  . V   s  ^  9  Where V 1 (s) is the output of the input buffer of conventional T/H circuit. Table 2. Hspice smulation of conventional T/H circuit Vout 1.46 v Average power consumption 76.94 mw peak power over a cycle 89.08 mw Slew rate 89.64 mv/ns Track time 0.92 ns Hold time 0.76 ns Figure 8. Output waveform for conventional T/H International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 50 3.2.1 Noise Analysis of Conventional T/H Circuit Table 2. Noise results of conventional T/H Total output noise voltage 6.945e-01 Sq V/Hz=833.37p V/Rt(Hz) Transfer function value ( Vout/Vin ) 1.64882n Equivalent input noise at Vin 505.43604m Total equivalent input noise voltage 1.14265K V Figure 9 . Output n oise of c onventional T/H 3.3. Analysis of T/H Circuit using Transmission-Gate Sampling Switch Here NMOS sampling switch is replaced with Transmission-gate sampling switch. As discussed earlier that On-resistance of Transmission-gate shows the linear characteristics hence linearity in output waveform is expected this is confirmed by the HSPICE simulation result. It improves the linearity but at the cost of area overhead. We require one more clock to use transmissiongate sampling switch Figure 10. Conventional T/H using Transmission-gate sampling switch Table 3. Hspice simulation results for conventional Track-and-Hold using Transmission-Gate V out 1.57v Average power consumption 78.33 mw Peak power over a cycle 90.91 mw Slew rate 110.48 mv/ns Track time 0.92 ns Hold time 0.81 ns Figure 11. Output waveform for T/H using Transmission-gate sampling switch International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 51 From the output waveform it is clear that V out is linear in behaviour. 3.3.1 Noise Analysis of Conventional T/H Circuit using Transmission-Gate Table 4. Noise results of conventional T/H using Transmission-Gate Total output noise voltage 4.473e-019 Sq V/Hz = 668.83807p V/Rt(Hz) Transfer function value (Vout/Vin) 1.06742n Equivalent input noise at Vin 626.59340m Total equivalent input noise voltage 1.43876K V Figure 12. Output noise of conventional T/H using Transmission-Gate 3.4. Analysis of Pseudo-differential T/H circuit The T/H circuit is implemented in a pseudo-differential fashion to suppress even–order nonlinearities as well as offset and common-mode noise. The biasing branch of the sourcefollower is, however, shared between the two half circuits to cancel the noise contribution of biasing devices. Figure 13. Pseudo-deferential T/H Figure 14. Output waveform for pseudodeferential T/H Table 5. Hspice Simulation Result of Pseudo-Differential T/H Vout 1.50 v Average power consumption 93.64 mw Peak power over a cycle 103.5 mw Slew rate 135mv/ns Track time 0.88 ns Hold time 0.77 ns International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 52 3.4.1 Noise Analysis of Pseudo-differential T/H circuit Table 6. Noise results of conventional T/H using Transmission-Gate Total output noise voltage 5.674e-019 Sq V/Hz =753.29254p V/Rt(Hz) Transfer function value (Vout/Vin) 1.04183n Equivalent input noise at Vin 723.05050m Total equivalent input noise voltage 1.63118K V Figure 15. Output noise of pseudo-differential T/H 3.5. Analysis of fully-differential T/H circuit Figure 16. shows that input and output buffers of conventional Track-and-Hold circuit are modified in differential manner so that common mode noise could be suppressed. This architecture suppress the noise upto 60-70% as compared to conventional one but at the cost of power consumption and area overhead. Figure 16. Fully-deferential T/H Figure 17. Output waveform of fullydeferential T/H Table 7. Hspice simulation results of fully-differential T/H Vout 1.56 v Average power consumption 162 mw Peak power over a cycle 182 mw Slew rate 181 mv/ns Track time 0.92 ns Hold time 0.81 ns International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 53 3.5.1 Noise Analysis of fully-differential T/H circuit Table 8. Noise results of fully differential T/H circuit Total output noise voltage 2.981e - 019 Sq V/Hz = 546.01522 p V/Rt(Hz) Transfer function value (Vout/Vin) 0 Equivalent input noise at Vin 0 Total equivalent input noise voltage 0 V Figure 18. O/P Noise of fully-differential T/H 3.5. Analysis of Two-Stage T/H using Conventional T/H Circuit In two-stage T/H circuit, two conventional T/H circuits are connected in cascade. The output of the first T/H serves as the input to the next T/H. If the input voltage of a T/H circuit is kept constant during its track phase, only one of charging or discharging is occurred in a track phase. In this case the output voltage of the T/H circuit settles monotonously into the constant voltage from the beginning of the track phase and its hold time must be as long as possible. This reduction of the tracking time results in a low power consumption. In order to apply such a constant voltage to the T/H circuit an additional small T/H circuit is inserted in front of the original T/H circuit as shown in Figure 19. Inverting and non-inverting clocks are applied to the two switches, Msw0 and Msw1, respectively so that the two T/H circuits act reciprocally. Figure 19. Two stage T/H circuit Figure 20. Output waveform of two stage T/H circuit When the second T/H circuit is in a track phase the first T/H circuit is always in a hold phase whose output voltage is constant. The first T/H circuit also charges and discharges its load capacitance during a track phase, however, it can operate very fast because its load capacitance is much smaller than that of the conventional T/H circuit. The first T/H circuit consumes very low power when the first T/H circuit and the conventional one have the same operation speed. The output voltage of the first stage is applied to the second T/H circuit. When the second T/H circuit is in the track phase, its input voltage is always constant because the first T/H circuit is already in the hold phase. Therefore, its output voltage approaches to the final value directly and it’s settling time decreases drastically [8].