Comparative loss evaluation of SiC semiconductors and capacitors in 800-V DC-Link for NPC family structures

This is the accepted version of a paper published in Power Electronics and Motion Control Conference (PEMC), IEEE, 2024. The final version is available at IEEE Xplore: 10.1109/PEMC61721.2024.10726330. This research received funding from the EU Horizon Europe MSCA Doctoral Network [HIPO], Grant Agreement No. [101072580]. LUT Group Confidential - Other information (3Y) Comparative loss evaluation of SiC semiconductors and capacitors in 800-V DC-Link for NPC family structures Saeid Deliri School of Energy Systems Lappeenranta-Lahti University of Technology Lappeenranta, Finland [email protected] Pasi Peltoniemi School of Energy Systems Lappeenranta-Lahti University of Technology Lappeenranta, Finland [email protected] Lassi Aarniovuori School of Energy Systems Lappeenranta-Lahti University of Technology Lappeenranta, Finland [email protected] Abstract—Power losses play a crucial role in the performance of an electric drive, and inverters are one of its constituent parts. This paper evaluates power losses and the possibility of increasing the power density by decreasing power losses, the size of the DC-link capacitors, and the number or size of the semiconductors. Besides the selection of components and operating switching frequency, the structure of an inverter affects the power density. Different kinds of capacitors and semiconductors are compared and analyzed in this paper in different 3-level inverter topologies. NPC, ANPC, and T-type NPC (TNPC) are compared in a range of switching frequencies from 10 kHz to 50 kHz to find the best topology, capacitor, and semiconductor in every single step of switching frequency. A constant thermal situation is considered to meet needed temperature restrictions and have a fair comparison. Simulations and calculations are performed for 800 V DC-Link voltage, 70 A peak output current NPC, ANPC, and TNPC inverters in MATLAB Simulink and PLECS blockset software linked together. Keywords—power losses, NPC structures, SiC semiconductors, CeraLink capacitors, optimum switching frequency I. INTRODUCTION Inverters are one of the most important parts of electric drives due to their effect on most important factors like efficiency, volume, cost, heat dissipation, EMI, etc., directly or indirectly. Power conversion from DC to AC is the main but not the only rule of inverters in an electric drive. Three level inverters have higher efficiency in higher output voltage and switching frequency than two level inverters in the cost of more semiconductors in their structures [1, 2]. However, more semiconductors mean more components to divide voltage stress and even current stress on, leading to lower switching and conduction losses [3]. In this way, despite increasing the number of semiconductors, it is still possible to keep the volume of the inverter in a reasonable range due to the lower required voltage and current for semiconductors. This becomes more important when low voltage stress on components enables higher DC-link voltage up to double that in two-level inverters, which is beneficial for other parts of a driver discussed in [4]. All the included components affect the performance of the inverters and raise the question of which topology and components could improve efficiency and power density and keep the cost in a reasonable range. Different targets, such as efficiency, cost, lifetime, or volume, could be considered before designing an inverter. Power density improvement has gained growing attention in electric vehicles, and extensive research has been done in the literature. However, it is still an interesting area to work on and improve further, enabled explicitly by developing semiconductor technologies [5, 6]. DC-Link capacitors occupy a considerable part of the housing of the inverter, and decreasing the volume by selecting the optimum capacitor considering needed capacitance, voltage, and current results in higher power density [7]. On the other hand, increasing the switching frequency effectively decreases total volume more and more because increasing the switching frequency decreases the voltage ripple on capacitors, and it means that lower capacitance is needed at higher frequencies, and in this way, the volume of capacitors is reduced. At the same time, Wide Band Gap (WBG) semiconductors made it easier to increase the switching frequency even at high power ranges. However, while increasing the switching frequency is very useful for power density targets utilizing WBG semiconductors, the dv/dt of WBG semiconductors causes some serious issues to overcome [8]. The higher switching speed of WBG semiconductors reduces the switching losses, but lower rise time means lower dt and higher du/dt. If dt becomes smaller using WBG semiconductors, it would be necessary to decrease dv as an achievable solution using multilevel inverters [9]. This is another reason highlighting the importance of utilizing 3-level inverters in high voltage output and switching frequency electric drives [1]. In this paper, different comparison analyses are done on capacitors and semiconductors in the 3-level neutral point clamped topologies to achieve the lowest power losses and volume by varying the switching frequency. Section II compares the most well-suited capacitors in DC-link, which meet the required capacitance and current with the minimum size and total ESR. The NPC, ANPC, and TNPC structures and their benefits compared to each other are presented in Section III. A list of SiC switches is simulated and compared in a switching frequency range to find the optimum structure and switch for each switching frequency point in Section IV. Simulations are done in MATLAB and PLECS software in sections II and IV, and conclusions are presented in Section V. LUT Group Confidential - Other information (3Y) II. DC-LINK CAPACITOR SELECTION As mentioned in the introduction, decreasing the size of the inverter, besides power loss reduction, is the main target, specifically in electric vehicle applications, which is the purpose of this study, too. Since capacitors occupy a remarkable volume in an inverter [9], finding the optimum capacitor is crucial to decreasing the inverter size. In other words, it seems easier to reduce the total volume of the inverter by decreasing the needed capacitance or current ripple rather than decreasing the number of semiconductors or using compact ones. To achieve this, a list of capacitors with higher operating temperature limits and higher current and capacitance density are selected to be compared as the first step. Film capacitors are commonly used in EV applications due to their ability to work up to a temperature of 100125 ℃ and higher current density than electrolytic capacitors [10]. Film capacitors from different companies, such as Vishay, Panasonic, and TDK, are used in this comparison. Recently, a kind of ceramic capacitor called CeraLink capacitors or lead–lanthanum–zirconate–titanate (PLZT) capacitors has been used to benefit from its higher current density and operating temperature advantage. In [10], an F10 type of them has been utilized, which is a pack of this capacitor with ten single capacitor cells. There are also F2 and F3 versions, and all these capacitors are available in 500 V, 700 V, and 900 V. Solder Pin (SP) CeraLink capacitors with a similar appearance to film capacitors but with higher current and capacitance density have been used in [11]. Since the height of capacitors is a kind of limit for the dimension of the inverter besides semiconductors chip area and needed heatsink in PCB design, the lower height of SP CeraLink capacitors helps to decrease the total volume of the inverter, in turn. The other significant benefit of these capacitors is their maximum allowed working temperature, which is even more than film capacitors up to 150 ℃. This is very crucial for high-current applications or any other high-temperature applications like integrated electric drives, in which the temperature of the machine affects the driver casing integrated. This can be even more important when semiconductor technology is developing quickly to increase switching frequency, current rate, and higher junction temperature capability, requiring the same operating temperature improvements in the other nearby components. TABLE I. COMPARED CAPACITORS Type and Name of Capacitor Appearance Manufacturer CeraLink Capacitors FA10 FA3 FA2 TDK FA20 (SP) TDK Film Capacitors Vishay TDK Panasonic 𝑛𝑝= max⁡(𝐼𝑜 𝐼𝑐,𝐶𝐷𝐶 𝐶𝑐𝑎𝑝) () Table I shows all considered capacitors and the companies whose datasheets were used for comparison in this paper concerning the needed capacitance to meet the maximum allowed voltage and current ripple. The comparison is done for almost 40 capacitors from all types above. Since the maximum output current is 70 A, and the current ripple on each DC-Link capacitor is not more than 30 A. Hence, a 40 A minimum current is considered for both upper and lower capacitors. The DC-Link voltage is 800 V, which is divided between capacitors, and the voltage stress on each one is almost 400 V. Therefore, the minimum voltage level for all paralleled capacitors should be more than 500 V, considering a safety margin. There are two main restrictions for the desired capacitor besides the needed voltage: the first one is capacitance, and the second one is current ripple. It is necessary to parallel more than one capacitor for almost all capacitors to satisfy both desired values for capacitance and current ripple. The capacitance is considered to be 50 µF, but it can be changed based on the maximum allowed voltage ripple on DC-Link capacitors or output current rate. Most probably, both of these requirements do not occur with the same number of capacitors. If ‘n’ is the number of capacitors needed to meet the minimum current and ‘m' is the number of capacitors required to create enough capacitance, the number of paralleled capacitors (nP) should equal the maximum value to include enough capacitors with minimum capacitance and current. To calculate ‘n’ and ‘m’, the output current (Io) and total capacitance of the DC-Link (CDC) should be divided by the maximum current of the capacitor (IC) and capacitance of each single capacitor (Ccap) as presented in (1). According to Fig. 1, the number of paralleled capacitors for CeraLink capacitors is determined by minimum needed capacitance, while for others, minimum current ripple is the main limit, and total capacitance is already more than the required value. This means that, in the case of selecting these capacitors to utilize, the voltage ripple of capacitors in DC-link will be much lower than the allowed value. However, excessive capacitance could result in some safety issues and discharging problems because of the high amount of stored energy [12]. TDK film capacitors have better specifications than other film capacitors because both capacitance and current limits are so close together. On the other hand, between CeraLink capacitors, FA2, which is the top one between green dots, is in a better situation if a higher current is needed. Besides the smaller size, lower Equivalent Series Resistance (ESR) is also desirable to increase power density by decreasing power losses. The power loss analysis of topologies using different capacitors is also a part of this study, but 40 capacitors are selected to compare, and having 3 topologies requires simulations to be done for 120 cases, while the only changed part will be ESR. So, the comparison of topologies is done only in the semiconductors comparison part (Section IV), in which 9 switches and 3 topologies are there to be compared with 27 simulation cases. The ESR value for CeraLink capacitors is very low and suitable for high switching frequency applications because in this kind of capacitor, ESR even decreases more with increment of switching frequency (×1/f), while it LUT Group Confidential - Other information (3Y) remains constant for film capacitors from 10 kHz to 100 kHz [10]. Regarding temperature, ESR is a constant value for film capacitors, while it has a downward trend in CeraLink capacitors even at high temperatures between 75 °C and 150 °C. All these benefits make these capacitors superior to film or even other well-known capacitors. Fig. 2 verifies that CeraLink capacitors have lower total ESR except for the FA20 solder pin capacitor. FA2, FA3, and FA10 have the lowest ESR values, and TDK film capacitors are in second place with a total capacitance of 50 µF up to 70 µF. The total ESR (ESRT) value is also affected by the number of paralleled capacitors used to prepare the minimum total capacitance, as presented in (2), which is why TDK film capacitors have lower ESR than the other film capacitors with the same capacitance. 𝐸𝑆𝑅𝑇(𝑛)=𝐸𝑆𝑅(𝑛) 𝑛𝑝 () Finally, the most effective approach is to define a function with different weights for ESR, capacitance, volume, current ripple capability, or any other desired advantages [13]. Based on the priorities of each application, these weights can be varied to find the optimum capacitor. TDK CeraLink capacitors include FA2, FA3, FA10, and FA20 with green dots, while 20 different Panasonic film capacitors are shown with red hexagrams, 7 Vishay film capacitors with blue pentagrams, and 7 TDK film capacitors with black square shapes. Fig. 1. Total current of capacitors against related total capacitance. Fig. 2. Total ESR of capacitors against related total capacitance. Current Density (CD) or capacitance density, ESR, maximum possible operating temperature, or cost could be the main target in this case. To come up with a solution on which capacitor fits better for a specific operating point, defining a function with multiplied weight (Wi) can be helpful [13]. Based on the importance of each factor, higher weight should be dedicated. In this study, this function has been defined as follows: 𝑓(𝑛)= 𝑊1×𝐶𝐷(𝑛) 𝑀𝑎𝑥⁡𝐶𝐷 + 𝑊2 𝑀𝑖𝑛⁡𝐸𝑆𝑅𝑇 𝐸𝑆𝑅𝑇(𝑛) +𝑊3×𝐶𝑎𝑝𝑇(𝑛) 𝑀𝑎𝑥⁡𝐶𝑎𝑝𝑇 (3) 𝐶𝐷(𝑛)=𝐶𝑢𝑟𝑟𝑒𝑛𝑡(𝑛) 𝑉𝑜𝑙𝑢𝑚𝑒(𝑛) () Where n is the number of compared capacitors, CapT is the total capacitance of paralleled capacitors, and f(n) is the supremacy function for the nth capacitor. The higher value for f(n) means a better candidate with considered priorities using Wi weights. The current density is calculated from (4) to be used in (3) by dividing it by the maximum current density. Maximum current density and maximum total capacitance are the highest values for current density and total capacitance between all capacitors in this comparison. Dividing the current density and total capacitance of each capacitor by their maximum value helps to have a fair comparison between current density, ESR, and capacitance factors. Since the higher value is determined as a criterion of supremacy for f(n), the lower value should be considered a positive point for ESR, and due to this purpose, the minimum total value of ESR between all capacitors is divided by the total ESR of the nth capacitor. Meanwhile, it was reversed for the current density and total capacitance. It is noticeable that the total value is not used for current density because it doesn’t affect the result despite ESR and capacitance. In this study, W1 is considered to be more than W2, and W2 is deemed more than W3. According to these considerations, FA2 has gained the maximum value from the defined function and is relatively superior to the other capacitors. III. INVERTER TOPOLOGIES In this paper, NPC, ANPC, and TNPC 3-phase topologies are considered to analyze the performance of semiconductors. Fig. 3-5 shows NPC, ANPC, and TNPC topologies, respectively. The number of semiconductors in NPC and ANPC is six for each phase, while it is four for TNPC. All semiconductors in ANPC are switches, but NPC includes four switches and two diodes, and these differences between them and TNPC cause different efficiency values in different switching frequencies. In TNPC, two Hswitches have higher voltage stress while T-leg switches have half of that voltage stress value but double current stress compared to H-leg switches. Also, heat dissipation between switches in ANPC is better than in NPC due to using diodes in NPC [14]. The efficiency of these topologies is extracted from simulating the conduction and switching losses of semiconductors. The temperature of semiconductors affects the switching and conduction losses of the inverter. So, the thermal consideration of semiconductors is important to aim for accurate losses as much as possible. The thermal models LUT Group Confidential - Other information (3Y) created by manufacturer companies for each semiconductor in PLECS software are used to simulate the circuit in more actual temperature to achieve switching and conduction losses. These models include thermal chain values, turn-on and off losses, and conduction losses graphs from the datasheet. Thermal resistance is also considered between the heatsink and the ambient to simulate the performance of the heatsink. At the same time, enough simulation time is needed to reach steady state temperature and calculate the efficiency at this temperature. Furthermore, the ON resistance of switches and forward voltage drop of diodes are added to the simulation model using datasheet values for operating current and temperature. Fig. 3. 3-phase NPC structure. Fig. 4. 3-phase ANPC structure. Fig. 5. 3-phase TNPC structure. IV. SIMULATION RESULTS TO FIND OPTIMUM SEMICONDUCTOR FOR DIFFERENT SWITCHING FREQUENCIES To evaluate the share of power losses of semiconductors in the inverter, NPC, ANPC, and TNPC structures are simulated in PLECS blockset software using different SiC semiconductors to find optimum semiconductors for each switching frequency range of these 3-level topologies. All effective parameters, such as capacitance of capacitors in DC-link, input DC voltage, fundamental frequency, output current, modulation method, and thermal resistance from case to heatsink, are considered the same to make a fair comparison. Simulations are done from 10 kHz to 50 kHz with a step size of 5 kHz for a group of semiconductors with 1200 V listed in Table II for NPC, ANPC, and TNPC. DC-Link input voltage is 800 V, and the output peak current is 70 A. To meet the thermal restrictions, thermal resistance has been selected in such a way that the junction temperature is much lower than the restricted values. Subsequently, the case temperature is not higher than 90°C for the highest switching frequency and the worst semiconductor in this case. So, the current rate for all semiconductors is lower than the maximum current value at this temperature. At the same time, some heatsinks are available in the market for used thermal resistance value. It is worth noting that current values in Table II are for 25 °C case temperature. However, for the maximum temperature of each semiconductor, the current rate is still lower than the mentioned value in the datasheet for that temperature. TABLE II. SEMICONDUCTORS AND THEIR SPECIFICATION No. Semiconductor continuous Drain Current at 25 ℃ (A) Ron Typ. (mΩ) Sw1 C3M0016120D 115 16 Sw2 C3M0021120D 81 21 Sw3 C3M0032120D 63 32 Sw4 C3M0032120K 63 32 Sw5 C3M0040120D 66 40 Sw6 MSC025SMA120B 103 25 Sw7 MSC025SMA120J 77 25 Sw8 MSC025SMA120S 89 25 Sw9 MSC040SMA120B 66 40 The schematic of a 3-phase TNPC topology of this paper has been illustrated in Fig. 6, while gate pulses come from a 3-level SVPWM generator block from Simulink, and the total power loss of semiconductors will be calculated using the switch loss calculator block in PLECS. The power loss data has been returned to the Simulink to generate power loss for each topology in Figs. 7-10. Table III shows the simulation parameters, while capacitance and ESR values of capacitors are variant and thus not included in the table. 1a S 1 C DC V 2a S 3a S 4a S 1c S 4c S 2 C a V b V c V 1b S 2b S 3b S 4b S 2c S 3c S 1a S 1 C DC V 2a S 3a S 4a S 1b S 4b S 2b S 3b S 2c S 1c S 4c S 3c S 2 C a V b V c V 5a S 6a S 5b S 6b S 5c S 6c S 1a S 1 C DC V 2a S 3a S 4a S 1b S 4b S 2b S 3b S 2c S 1c S 4c S 3c S 2 C a V b V c V LUT Group Confidential - Other information (3Y) Fig. 6. 3-phase TNPC topology simulation schematic in PLECS. TABLE III. SIMULATION PARAMETERS Parameter Value Unit DC Link Voltage 800 V Peak Output Current 70 A Fundamental Frequency 50 Hz Switching Frequency 10-50 kHz Heatsink Thermal Resistance (Rth) 0.3 K/W Ambient Temperature (Tamb) 25 °C The total power loss results of the compared structures are presented in Fig. 7-9. Fig. 7 illustrates the results for NPC topology from 10 kHz to 50 kHz. Also, the C4D30120D diode is used in simulations that are done in PLECS. Based on this figure, Sw4 has lower total power losses from 10 kHz to 50 kHz. For ANPC topology, at a switching frequency of less than 40 kHz, Sw1, and for higher than 40 kHz, at least up to 50 kHz, Sw7 gains the lowest power losses according to Fig. 8. However, Sw8 has competitive results with Sw1, and Sw7, specifically at high switching frequencies. The same happens for TNPC, as seen in Fig. 9. But in this topology, Sw7 has lower power losses for a range of switching frequencies from 25 kHz to 50 kHz, and for lower switching frequencies, Sw1 has lower power losses. In TNPC, Sw6 and Sw8 have very low power losses compared to other switches. Based on comparison results, the TNPC structure has lower power losses compared to NPC and ANPC in this switching frequency range. If the number of used semiconductors is taken into account, TNPC has only four semiconductors in its structure, while NPC and ANPC include six semiconductors in each phase. So, TNPC is expected to have a lower volume and higher power density in the same situations. The results for higher switching frequencies are more important because increasing the switching frequency decreases the voltage ripple of capacitors and needed capacitance, which helps to reduce the size of DC-Link capacitors. It is also essential to consider EMI issues besides temperature limits at higher switching frequencies, which are not subjects of this study. Of course, case and junction temperatures are lower than the maximum allowed values. Fig. 7. Switching and conduction losses of each switch of the NPC structure as a function of the switching frequency. Fig. 8. Switching and conduction losses of each switch of the ANPC structure as a function of the switching frequency. Fig. 9. Switching and conduction losses of each switch of the TNPC structure as a function of the switching frequency. LUT Group Confidential - Other information (3Y) Fig. 10. Minimum values achieved for total losses of semiconductors in compared structures at a switching frequency of 50 kHz. Fig. 10 illustrates the lowest power losses between all semiconductors used in NPC, ANPC, and TNPC structures at a switching frequency of 50 kHz. Between the best results, six switches are for the TNPC structure, including three first switches. Sw8 and Sw7 have the lowest power losses of 307 W and 309 W if used in the TNPC structure. NPC structure utilizing Sw4 has the lowest power loss among all switches in NPC and ANPC structures. Also, for the ANPC structure, the lowest power losses have been presented for Sw7, Sw8, and Sw1, respectively. V. CONCLUSION This paper presented a comparative study on 3-level NPC, ANPC, and TNPC structures. Over 40 capacitors are analyzed as the best candidates for an 800 V DC-Link in NPC topologies. The best capacitance is FA2 based on the considered priorities between ESR, current density, and capacitance. In the second part of the comparisons, the most well-suited semiconductors for this operating current and voltage with available PLECS thermal models are analyzed in the 3-level NPC structures. Based on simulation results, TNPC topology utilizing Sw8 has lower power loss than other semiconductors in different 3-level topologies. The first 10 combinations of topologies and semiconductors are presented if there is any limitation or priority is the case. The simulation results are presented for 70 A and 800 V output peak current and voltage, 50 Hz output fundamental frequency, and switching frequency from 10 kHz to 50 kHz using the SVPWM method, and the best candidates at different switching frequencies can be extracted from power loss results. The best capacitor, semiconductor, and topology combination is presented to minimize the power losses and the volume to achieve the maximum possible power density. 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