Multi-Objective Optimization for Power Conversion System Design in Grid-Connected Hybrid Energy Storage System.

Multi-Objective Optimization for Power Conversion System Design in Grid-Connected Hybrid Energy Storage System Oriol Esquius-Mas, Alber Filba-Martinez, Claudia Cabre-Piqueras and Lluis Trilla Institut de Recerca en Energia de Catalunya, 08930 Barcelona, Spain; [email protected] (O.E.-M.); [email protected] (A.F.-M.); [email protected] (C.C.-P.); [email protected] (L.T) Abstract: The increasing integration of renewable energy sources and energy storage systems into the electrical grid demands the development of high-performance power conversion technologies. In this context, the design of efficient and reliable power conversion systems (PCS) is crucial for the integration of these energy sources. The use of optimization tools facilitates the selection of power conversion architectures and converter topologies that enhance overall efficiency and reliability while reducing development time. This paper presents an advanced optimization tool developed for designing the dc-ac PCS of HESS, which integrates a lithium-titanate-oxide (LTO) battery and an aqueous-organicredox-flow (AORF) battery for grid connection. Four conversion architectures are explored with different degrees of dc-dc and dc-ac module parallelization. A set of optimization problems is defined to obtain the Pareto front of solutions for each architecture, resulting in different trade-offs between the system’s performance metrics. 1. Introduction Hybrid energy storage systems (HESS) have become a popular solution to address the intermittency of renewable energy sources, such as solar and wind [ 1 – 4 ]. The design of efficient and reliable power conversion systems (PCS) represents a key challenge in the integration of the HESS into the grid. Optimization processes are often used in order to identify the optimum PCS design in terms of efficiency, capital and operational costs, power density, and other performance indicators [ 5 – 7 ]. These processes enable a systematic evaluation of trade-offs, obtaining a PCS ensuring good results in the performance indicators. This paper presents an advanced optimization tool developed for designing the optimum power conversion architecture of the dc-ac PCS of a HESS integrating a lithiumtitanate-oxide (LTO) battery and an aqueous-organic-redox-flow (AORF) battery to the grid. The optimization process presented in this paper focuses on comparing the performance of four different power conversion architectures in terms of power losses and cost. The candidate conversion architectures use a two-stage power conversion: the first stage comprises dc-dc converters interfacing the dc ports of the LTO and AORF batteries, while the second stage features dc-ac converters connecting the dc bus of the dc-dc stage to the grid. Dual Active Bridge (DAB) converters are used in the first power conversion stage, featuring bidirectional power flow capability, high performance and galvanic isolation [8–12], and three-phase PWM dc-ac converters are used in the second stage. The rest of the paper is structured as follows. Section 2presents the candidate power conversion architectures. Then, Section 3introduces the electrical model of the HESS batteries and power converters. Section 4, Section 5, Section 6and Section 7describe the losses, thermal, reliability, and cost models for the PCS. Then, Section 8presents the multi-objective optimization function and the results of the optimization process. Finally, Section 9discusses the implications of the optimization tool. 2. Candidate power conversion architectures Figure 1shows the four candidate conversion architectures. Architecture A is the most parallelized architecture, using three parallel dc-dc converters and a separate dcac converter for each battery. In contrast, Architecture D presents the lowest level of February 21, 2025 1 of 25. February 21, 2025 2 of 25 parallelization, with a single dc-dc converter per battery and a single dc-ac converter connecting the common dc bus to the ac grid. Architectures B and C offer intermediate levels of parallelization: Architecture B uses a single dc-ac converter and three dc-dc converters per battery, and Architecture C employs a single dc-dc converter and a dcac converter per battery. These four architectures provide different configurations for optimizing system performance. Figure 1. Candidate conversion architectures. 3. HESS electrical model 3.1. LTO and AORF batteries LTO and AORF batteries are modeled as a constant and ideal voltage source connected in series to a resistor (Figure 2). Table 1shows the electrical parameters of the HESS batteries. Both batteries are configured to operate at their nominal voltage and power ratings. The ideal voltage sources VLTO and VAORF represent the nominal voltage of the batteries. When operating at nominal power and voltage, the internal resistance voltage drop is 5% for the LTO battery and 19% for the AORF battery. Figure 2. LTO and AORF batteries electrical model. Table 1. Electrical ratings of the HESS batteries. Battery Nominal voltage [V] Nominal power [kW] Internal resistance [mΩ] LTO 330 50 100.8 AORF 50 9 42.6 February 21, 2025 3 of 25 3.2. DAB converter The DAB converters used in the analyzed architectures exhibit a dual-sided configuration: the low voltage (LV) side interfaces with the energy storage elements (LTO and AORF batteries), while the high voltage (HV) side is connected to the common dc-link shared with the dc-ac inverter modules. The DAB (Figure 3) features two active bridges connected through a high-frequency (HF) transformer, where power flow is controlled by implementing single phase-shift modulation between the bridges’ ac output voltages. The phase-shift angle φ induces a current through the converter’s high-frequency (HF) inductor, L, enabling bidirectional power flow control. Figure 3. Electrical scheme of the DAB. Figure 4. Electrical scheme of the DAB. Figure 4depicts the DAB currents and voltages. The instantaneous current through the inductor, iL, is defined over a switching period as iL(θ) =                                            VLV +VHV n 2πfDABLθ− VLV π 2+VHV nφ−π 2 2πfDABL, 0 ≤θ<φ VLV −VHV n 2πfDABL(θ−φ)+ VLVφ−π 2+VHV n π 2 2πfDABL,φ≤θ<π − VLV +VHV n 2πfDABL(θ−π) + VLV π 2+VHV nφ−π 2 2πfDABL,π≤θ<π+φ − VLV −VHV n 2πfDABL(θ−π−φ)− VLVφ−π 2+VHV n π 2 2πfDABL,π+φ≤θ≤π , (1) February 21, 2025 4 of 25 where fDAB is the converter’s switching frequency and n is the inverse of the transformer’s turns ratio, rt. The LV and HV side instantaneous currents, iLV and iHV, are defined as iLV(θ) =                VLV +VHV n 2πfDABLθ− VLV π 2+VHV nφ−π 2 2πfDABL, 0 ≤θ<φ VLV −VHV n 2πfDABL(θ−φ)+ VLVφ−π 2+VHV n π 2 2πfDABL,φ≤θ<π (2) iHV(θ) =                − VLV +VHV n 2πfDABLn θ+ VLV π 2+VHV nφ−π 2 2πfDABLn , 0 ≤θ<φ VLV −VHV n 2πfDABLn (θ−φ)+ VLVφ−π 2+VHV n π 2 2πfDABLn ,φ≤θ<π , (3) and the active power transferred by the converter form the LV side to the HV side is PDAB =V2 LV 2πfDABLdφ1−|φ| π, (4) where d=VHV/(VLVn)is the LV-side-referred dc-voltage gain of the converter. Due to the internal resistance of the battery, VLV decreases as PDAB increases, as described by VLV(PDAB)=Vbat +qV2 bat −4RbatPDAB 2. (5) From [ 8 ], when d= 1, zero-voltage switching (ZVS) is achieved during the switches turn-on transitions at both sides of the converter across the full power range. Soft-switching transitions result in reduced switching losses and improved efficiency, particularly at high switching frequencies. For d= 1, soft switching is lost in the low-power range, leading to increased switching losses; i.e., hard switching, which negatively affects efficiency. Additionally, when d≫ 1 or d≪ 1, the converter conduction and switching losses increase due to increased RMS currents in the switches and magnetic components, as well as higher switching currents in the switches. Figure 5shows the relation between φ and PDAB for the AORF DAB converter. When rt is set for VLV(PDAB,nom) (Section 3.2), the converter will feature hard-switching losses in the low-power range. This is avoided when rt is set for VLV(PDAB,nom/2) (Section 3.2). Although setting rt for VLV(PDAB,nom) allows lower conduction and switching losses in the high-power range, efficiency is greatly diminished in the low-power range. The described performance characteristics are also featured in the LTO DAB converter. Thus, to maintain a fairly constant efficiency in the whole power range, rt is defined for AORF and LTO DAB converters as rt =1 n=VLV(PDAB,nom/2) VHV . (6) February 21, 2025 5 of 25 Figure 5. AORF-DAB-converter relation between the phase shift and the transferred power considering the battery voltage drop (blue line). Shaded areas indicate hard-switching regions. 3.3. dc-ac converter Figure 6depicts the electrical scheme of the three-phase PWM dc-ac converter, used in the second stage of the candidate conversion architectures to connect the high-voltage dc bus to the ac grid. This converter has bidirectional power flow capability and is controlled using the sinusoidal pulse-width modulation (SPWM) technique. Figure 6. Electrical scheme of the dc-ac. The fundamental component of the phase voltages synthesized by the dc-ac converter are                va,1(θ) = Vinv,1 sin(θ+φV,inv,1) vb,1(θ) = Vinv,1 sinθ−2π 3+φV,inv,1 vc,1(θ) = Vinv,1 sinθ+2π 3+φV,inv,1 , (7) where Vinv,1 is defined as Vinv,1 =maVHV 2, (8) ma is the modulation index and φV,inv,1 is the phase shift between the converter reference phase voltages and the grid voltages. February 21, 2025 6 of 25 Considering the converter ac-side phase currents to be sinusoidal, these are defined as                ia(θ) = I1sin (θ+φI,inv,1) ib(θ) = I1sinθ−2π 3+φI,inv,1 ic(θ) = I1sinθ+2π 3+φI,inv,1 (9) where I1 is the grid currents fundamental component amplitude and φI,inv,1 is the grid currents phase shift with respect to the grid voltages. The active and reactive power transferred by the converter to the grid are        P=3 2Vgrid I1cos(φinv) Q=3 2Vgrid I1sin(φinv), (10) respectively, where Vgrid is the amplitude of the grid phase voltages and φinv =−φI,inv,1 is the power-factor angle at the grid. 4. PCS losses model This section presents the model used in the optimization process to compute the power losses of the components of the PCS. The model accounts for losses in semiconductors, magnetic elements, and capacitors, providing a comprehensive assessment of system efficiency. 4.1. Semiconductor losses The semiconductor devices considered for the four converter architectures are Si and SiC MOSFETs for the DAB LV side, and SiC MOSFETs for the DAB HV side and the dc-ac converter. As the DAB converter works under soft-switching conditions, and the MOSFET body diode turn-on switching losses are considered negligible, semiconductor losses are limited to MOSFET conduction and turn-off losses, as well as body diode conduction losses. In the dc-ac converter, losses include MOSFET conduction, turn-on, turn-off, and reverse diode conduction and turn-off losses. 4.1.1. Conduction losses MOSFET conduction losses (for both Si and SiC devices) consist of on-state conduction losses, proportional to the drain-to-source on-state resistance rds,on,k , and reverse conduction losses in the MOSFET body diode, determined by the on-state diode voltage drop Vf0,k , and the diode equivalent resistor rf,k . These parameters are temperature-dependent and are linearly adjusted to the junction temperature at the operating point, Tj,k. Then, the on-state conduction losses for the kMOSFET device are defined as Pcond,MOS,on−state,tot(Tj,k) = ∑ k rds,on,k(Tj,k)·I2 rms,MOS,k, (11) where Irms,MOS,kis the rms current flowing through the kMOSFET device. In reverse conduction mode the source-to-drain voltage is defined as vsd,k(t) = rds,on,k(Tj,k)·iMOS,k(t)(12) where iMOS,k(t)is the reverse current flowing through the channel resistance. In the third quadrant, reverse current may flow through either the channel resistance or the body diode, and the portion of current flowing through each path is not constant. Consequently, third quadrant conduction losses are analyzed in two distinct time intervals. February 21, 2025 7 of 25 Linearizing the body diode’s third quadrant characteristics using Vf0 and rf reveals that no current flows through the parasitic diode when Vsd ≤Vf0 . Under these conditions, the entire current flows through the MOSFET channel, and the source-to-drain voltage is defined as vsd,k(t) = rds,on,k(Tj,k)·iD,k(t)(13) where iD,k(t) is the total reverse current in the device, in this case flowing entirely through channel resistance rds,on,k. The instant tlim is defined as the time when Vsd =Vf0 , and the source-to-drain voltage is rds,on,k(Tj,k)·iD,k(tlim,k)=Vf0,k . (14) When Vsd >Vf0 , that is iD,k(t)>iD,k(tlim) , a portion of the current flows through the body diode, while the remainder flows through the MOSFET channel. In this case, iD,k(t) = iMOS,k(t) + idiode,k(t)(15) where idiode,k(t) is the reverse current flowing through the body diode. Also, the diode anode-to-cathode voltage is equal to the MOSFET source-to-drain voltage. Therefore, Vf0,k +idiode,k(t)·rf,k(Tj,k) = rds,on,k(Tj,k)·iMOS,k(t)(16) It is possible then to determine the expression of the instantaneous current flowing through the body diode and through the MOSFET channel during reverse conduction, iMOS,k(t) = Vf0,k(Tj,k) + iD,k(t)·rf,k(Tj,k) rds,on,k(Tj,k) + rf,k(Tj,k)(17) idiode,k(t) = iD,k(t)·rds,on,k(Tj,k)−Vf0,k(Tj,k) rds,on,k(Tj,k) + rf,k(Tj,k), (18) and the reverse conduction losses are defined as Pcond,MOS,rev,tot =∑ k (rds,on,k·1 ∆t1,k ·Ztlim,k ti,k iD,k(t)2·dt+ rds,on,k·1 ∆t2,k ·Ztf,k tlim,k iMOS,k(t)2·dt+ rf,k·1 ∆t2 ·Ztf,k tlim,k idiode,k(t)2·dt +Vf0,k·1 ∆t2 ·Ztf,k tlim,k idiode,k(t)·dt) (19) where ∆ t1 is the time interval during which Vsd ≤Vf0 , and ∆ t1 is the time interval during which Vsd >Vf0 , and ti and tf are the instants when the reverse conduction starts and ends. Pcond,MOS,tot =Pcond,MOS,on−state,tot +Pcond,MOS,rev,tot (20) 4.1.2. Si MOSFET switching losses Datasheets for Si MOSFETs often omit explicit information on energy loss per switching event. Then, the energy lost during a turn-off transition can be approximated as Esw,off,k=Ztru+tf i 0vds,k(t)·id,k(t)·dt =VDD,k·ID,k·tru,k+tfi,k 2, (21) where ID,k is the switching current, VDD,k is the blocking voltage and tru,k and tfi,k are the voltage rising time and current falling time during the turn-off transition, respectively. Then, the turn-off losses for Si MOSFET devices are defined as Psw,off,MOS,tot =fsw,k∑ k Esw,off,k. (22) February 21, 2025 8 of 25 4.1.3. SiC MOSFET switching losses Datasheets for SiC MOSFET devices typically specify reference values for turn-on and turn-off energy loss, Esw,on,ref,k and Esw,off,ref,k respectively, and for the body diode turn-off energy loss, Esw,rec,ref,k . These values are provided under defined operating conditions, including a reference drain-to-source voltage, Vds,ref,k , switching current Isw,ref,k , gate resistor RG,ref,k and junction temperature Tref,k . Using the information provided in the datasheets, the MOSFET turn-on and turn-off energy losses and the body diode turn-off losses are adjusted to the actual operating conditions using linear regressions. Then, the switching losses for SiC MOSFET devices are computed as Psw,on/off/rec,SiC,tot =∑ k fsw,k·Esw,on/off/rec,kTj,k,Vds,k,Isw,k,RG,k. (23) 4.2. Magnetic elements losses Magnetic element losses can be categorized into winding dc copper losses, winding ac copper losses, and magnetic core losses. Winding dc losses arise from the Joule effect caused by dc and low-frequency current components in the conductor material, such as copper. In contrast, winding ac losses result from the skin and proximity effects, which reduce the effective cross-section for current flow at high frequencies, increasing Joule losses. Finally, high-amplitude ac currents in the winding can induce considerable magnetic core losses due to energy dissipation within the core. In DAB inductors ( Lsx ) and transformers ( Tax ), only ac copper losses and magnetic core losses are considered due to the high-frequency currents and voltages without dc bias. Conversely, the filter inductors ( Llx ) in the dc-ac converter are designed to achieve low current total harmonic distortion (THD), resulting in low-frequency currents with minimal high-frequency ripple and no dc bias. Consequently, these inductors present dc copper losses and magnetic core losses, with ac copper losses being negligible. 4.2.1. Conduction losses Losses on a magnetic device with k windings due to the dc and low frequency components of the winding current are modeled as Pdc = k ∑ j=1 Rdc,j·I2 j(24) where Ijis the rms current of winding j and Rdc,j=ρj·nj·MLT npwj·Aw,j (25) is winding j dc resistance, where ρj and Aw,j are winding j wire resistivity and crosssectional area, respectively, nj and MLT are the number of turns and the mean length turn of winding j , respectively, and npwj is the number of wire conductors connected in parallel in winding j. The ac copper losses in winding jare defined as Pac,j= Mj ∑ mj=1 Pac,mj=I2 1,j·Rdc,j·Rac,j. (26) where Rac is the winding ac resistance, which value is obtained from the magnetic element dimensions and material as discussed in [13]. 4.2.2. Core losses Magnetic losses in the core material arise from two primary mechanisms: hysteresis losses, associated with energy dissipation in the magnetic-field hysteresis loop, and eddy February 21, 2025 9 of 25 current losses, resulting from the induction of currents within the electrically conductive core material. These losses can be effectively modeled using the Steinmetz equation as PFe =KFe0·fξ 1·∆Bβ·Nc·Ac·lm, (27) where KFe0 , ξ , and β are parameters coming from selected magnetic material, Nc is the number of stacked cores, Ac is the cross-sectional area of a single magnetic core, lm is the core magnetic path length, and ∆B is half of the core flux density swing in the hysteresis cycle, defined as ∆B=γ 2·nj·Nc·Ac, (28) where γ is the volts-seconds applied to any of the windings, defined as the integral of the voltage over half a period. 4.3. Capacitor losses Capacitor losses are mainly caused by joule-effect losses on its parasitic resistance and can be modeled as Pcap =ESR ·I2 c(29) where ESR is the capacitor equivalent series resistance and Ic is the capacitor rms current. 5. PCS thermal model This section introduces the thermal model used in the optimization process to compute the heat dissipation of PCS components. the model includes the heat dissipation in semiconductors, magnetic elements and capacitors. 5.1. Semiconductors heat dissipation To dissipate the heat generated by MOSFET power losses, a heatsink is attached to the devices. MOSFETs may be individually packaged or grouped into modules, with each discrete device having its own heatsink or sharing one when connected in parallel. For module-based configurations, one heatsink is used per module. Heat flows from the chip junction to the heatsink and then to the ambient air, with thermal resistances defined by junction-to-case (Rth,j−c), case-to-heatsink (Rth,c−h), and heatsink-to-ambient (Rth,h−a). Power losses in each semiconductor depend on its junction temperature. Since all semiconductors attached to a heatsink share the same Rth,j−c , Rth,c−h , and power losses, the junction ( Tj,n ) and case ( Tj,c ) temperatures of a semiconductor device n are defined using the following system of linear equations                                      Pcond,n+Psw,n=fTj,n Pcond,1Tj,1=Pcond,2Tj,1=. . . =Pcond,nTj,n Psw,1Tj,1=Psw,2Tj,2=. . . =Psw,nTj,n Rth,j−c,1 =Rth,j−c,2 =. . . =Rth,j−c,n Rth,c−h,1 =Rth,c−h,2 =. . . =Rth,c−h,n Tc,n=Ta+Rth,h−a·N·(Pcond,1 +Psw,1) Tj,n=Tc,n+Rth,j−c,n+Rth,c−h,n·(Pcond,n+Psw,n) ,n=1, 2, . . . , N, (30) where N is the number of semiconductors attached to the heatsing, Pcond,n and Psw,n are the conduction and switching losses of semiconductor n, and Tais the ambient temperature. February 21, 2025 16 of 25 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 Losses [p.u.] Architecture A Best results (WS1) Best results (WS2) Best results (WS3) Pareto front (WS1) Pareto front (WS2) Pareto front (WS3) Opt. results (WS1) Opt. results (WS2) Opt. results (WS3) Architecture B Best results (WS1) Best results (WS2) Best results (WS3) Pareto front (WS1) Pareto front (WS2) Pareto front (WS3) Opt. results (WS1) Opt. results (WS2) Opt. results (WS3) 234567 Cost [p.u.] 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 Losses [p.u.] Architecture C Best results (WS1) Best results (WS2) Best results (WS3) Pareto front (WS1) Pareto front (WS2) Pareto front (WS3) Opt. results (WS1) Opt. results (WS2) Opt. results (WS3) 2 3 4 5 6 7 8 Cost [p.u.] Architecture D Best results (WS1) Best results (WS2) Best results (WS3) Pareto front (WS1) Pareto front (WS2) Pareto front (WS3) Opt. results (WS1) Opt. results (WS2) Opt. results (WS3) Figure 8. Losses and cost values obtained with the top 10% best results for each architecture and weight set. Pareto front lines for the optimum solutions shown in dotted lines. Optimum solutions shown with black and white markers. Table 2. Values of the objective function, cost, and losses provided by the optimum solution for each architecture and weight set. Architecture Weight set Gx,w[p.u.] σ′ x,w[p.u.] ζ′ x,w[p.u.] A WS1 2.80 3.96 1.64 WS2 3.44 3.82 1.91 WS3 1.96 4.85 1.24 B WS1 2.60 3.66 1.53 WS2 3.18 3.47 2.00 WS3 1.81 4.55 1.13 C WS1 2.06 2.63 1.49 WS2 2.21 2.20 2.10 WS3 1.66 3.09 1.30 D WS1 1.75 2.12 1.39 WS2 1.76 1.76 1.75 WS3 1.45 2.90 1.09 Figure 9presents a break down of the cost for the optimum solutions across each architecture and weight set. For all architectures and weight sets the semiconductors February 21, 2025 17 of 25 account for almost 50 % of the system cost. The second largest capital cost are magnetic elements, followed closely by the reparation cost, the cooling system cost (heatsinks and fans), and the capacitors cost. The cost of the auxiliary components and the cost penalty from revenue losses are marginal in all cases (≤6%). Overall, architectures C and D feature lower material costs. Although there is some linear dependency of each component cost with its current rating, capacity, thermal resistance, etc., still a fixed cost is present (package cost, labour cost, auxiliary components, etc.) and it is approximately the same for all components of the same type. Therefore, a higher number of components leads to higher system costs, explaining the reduction in capital costs from architectures A to D. However, some exceptions occur. The cost of capacitors decreases when reducing the number of dc-ac converters (architectures A to B and C to D), but increases when reducing the number of dc-dc converters (architectures A to C and B to D). Although the total number of capacitors across the dc-dc converters in architectures A and B is higher than on Architectures C and D, the required total capacitance is lower thanks to the interleaving of the three dc-dc converters, thus reducing the overall capacitor costs. Regarding the operational costs, the system reparation cost is greater in architectures A and B, mainly because they feature more components, and thus the probability of a failure occurring is greater. The energy revenue loss in all architectures is similar. Thus, having more redundancy does not necessarily mean a lower operation cost derived from failures. Nonetheless, if the penalty cost for total system shutdown is increased, this would increase architectures C and D revenue loss cost, stopping them from being competitive compared to architectures A and B in terms of operational cost. Figure 10 details the losses of the optimum solutions for each architecture and weight set. In architectures B, C, and D, semiconductor losses dominate (50%-60% of total losses), followed by magnetic losses (35%-45%). Architecture A is an exception, with magnetic losses (50%) exceeding semiconductor losses (45%), due to the reduced magnetic core losses in architectures C and D. These losses are mainly dependent to the battery and HV dc-link voltage, the switching frequency, and the number of cores. The higher these values are, the higher the core losses. Since the voltages and switching frequencies are similar, the greater number of cores in architectures A and B leads to higher core losses. The most parallelized architectures (C and D) feature on average lower semiconductor conduction losses, since these losses are proportional to the squared RMS current. For instance, if the MOSFETs employed in the dc-dc converters in architectures A and B (with 3 converters) and C and D (with 1 converters) feature the same on-state resistance, the total MOSFET conduction losses in architectures A and B dc-dc modules are approximately onethird of those in C and D. When looking at Figure 23, the average (across WSs) conduction losses across WSs of architectures A and B are actually 5/6 of C and D. This is due to the MOSFETs selected by the optimization algorithm in A and B featuring on average higher on-state resistance than those in C and D, and the dc-dc converters in C and D featuring up to 4 MOSFETs in parallel, reducing effective on-state resistance. Nonetheless, the magnetic elements’ copper losses do not follow this trend. On average across WSs, the copper losses in architectures with two dc-ac converters are larger than those with a single dc-ac converter. This is because the number of turns in Ll inductors increases when the converter power decreases to limit the current total harmonic distortion (THD), resulting in higher copper losses. This can be compensated by increasing the number copper area at the expense of a higher cost. Overall, architectures A and B feature slightly more switching losses than C and D. However, this trend is inverted when prioritizing the minimization of the losses (WS3). In this solution, the number of MOSFETs in parallel in architectures C and D is higher than in WS1 and WS2, resulting in overall more switching instances, and thus higher switching losses. In all architectures, capacitor losses are marginal (around 5%). February 21, 2025 18 of 25 Figure 9. Cost distribution for the optimum solution on each architecture and weight set. 9. Discussion This study presents an optimization tool for the design of a PCS in a HESS integrating a LTO battery and an AORF battery to the grid, balancing cost, efficiency, and reliability. The optimization is performed considering four system-architecture candidates featuring different degrees of power-converter parallelization. Moreover, the optimization problem is defined with comprehensive electric, losses, reliability, and cost models of the components in the power converters, and a wide design space is defined to determine the specifications of the different power-converter elements. The optimization targets the minimization of the system conversion losses and cost, where the cost accounts for the capital expenditure, the system failure reparation, and the revenue loss from the energy not delivered due to system partial or complete shutdown caused by failures. A set of optimization problems are defined for each architecture, assigning different priorities to the minimization of losses and cost. The results obtained from the optimization process show that lower levels of parallelization tend to reduce costs significantly due to a decrease in the number of components, February 21, 2025 19 of 25 Figure 10. Losses distribution for the optimum solution on each architecture and weight set. such as converters, magnetic elements, and capacitors, resulting in low capital and maintenance cost, which can be critical in cost-sensitive applications. Conversely, architectures with higher parallelization feature higher fault tolerance and operational flexibility. By connecting multiple converters in parallel, these architectures can continue operating under partial failures, ensuring greater reliability. The results also show the importance of semiconductor and magnetic losses across all architectures. In highly parallelized systems, magnetic core losses are particularly significant due to the increased number of magnetic components, while systems with lower parallelization present higher conduction losses due to higher current density. For the present HESS, the architecture featuring a single DAB converter per battery and a single three-phase dc-ac converter stands as the optimum solution. Moreover, the solution given by WS2 features the best trade-off in terms of cost and efficiency. Future work should extend this analysis by considering multiple operation points of the PCS, to enhance the applicability of the optimization process, and experimental validation. February 21, 2025 20 of 25 Appendix A This appendix presents a list of the optimization variables used in the optimization process and their corresponding design space. The optimization-variables set, presented in Table A1, is composed of 81 discrete variables. Each optimization variable can be either numeric (real or integer) or text, and can take values that are part of a set of values defined by the user, that is, the design space. The design-space value sets are presented in A2. Table A1. Optimization variables. Parameter Description npar,sw,DAB,LV,b Number of switches connected in parallel in the LV side of the DAB converter(s) connected to the bbattery npar,sw,DAB,HV,b Number of switches connected in parallel in the HV side of the DAB converter(s) connected to the bbattery npar,sw,dc−ac,b Number of switches connected in parallel in the dc-ac converter connected to the bbattery typesw,DAB,LV,LTO Type of switch used in the LV side of the DAB converter(s) connected to the LTO battery modelsw,DAB,LV,b Switch model in the LV side of the DAB converter(s) connected to the bbattery modelsw,DAB,HV,b Switch model in the HV side of the DAB converter(s) connected to the bbattery modelsw,dc−ac,bSwitch model of the dc-ac converter connected to the bbattery VHV HV dc link voltage fs,DAB,b Switching frequency of the DAB converter(s) connected to the b battery mf,bm f factor for the dc-ac converter connected to the bbattery modelHS,DAB,LV,b Heatsink model to dissipate the heat generated by the switches in the LV side of the DAB converter(s) connected to the bbattery modelHS,DAB,HV,b Heatsink model to dissipate the heat generated by the switches in the HV side of the DAB converter(s) connected to the bbattery modelHS,dc−ac,b Heatsink model to dissipate the heat generated by the switches of the dc-ac converter connected to the bbattery LHS,DAB,LV,b Length of the heatsink for the switches in the LV side of the DAB converter(s) connected to the bbattery LHS,DAB,HV,b Length of the heatsink for the switches in the HV side of the DAB converter(s) connected to the bbattery LHS,dc−ac,b Length of the heatsink for the switches of the dc-ac converter connected to the bbattery February 21, 2025 21 of 25 Parameter Description npar,cap,LV,b Number of parallel capacitors in the LV side of the DAB converter(s) connected to the bbattery npar,cap,HV,b Number of parallel capacitors in the HV dc link between the DAB converter(s) and the dc-ac converter connected to the bbattery modelcap,LV,b Capacitor model in the LV side of the DAB connected to the b battery modelcap,HV,b Capacitor model in the HV side of the DAB connected to the b battery ncore,L,DAB,b Number of cores stacked in parallel in the inductor in the DAB converter(s) connected to the bbattery ncore,Tx,DAB,b Number of cores stacked in parallel in the transformer in the DAB converter(s) connected to the bbattery ncore,L,dc−ac,b Number of cores stacked in parallel in the inductors of the dc-ac converter connected to the bbattery modelcore,L,DAB,b Core model in the inductor of the DAB converter(s) connected to the bbattery modelcore,Tx,DAB,b Core model in the transformer of the DAB converter(s) connected to the bbattery modelcore,L,dc−ac,b Core model in the inductors of the dc-ac converter connected to the bbattery typewire,L,DAB,b Wire type used in the inductor of the DAB converter(s) connected to the bbattery typewire,Tx,DAB,b Wire type used in the transformer of the DAB converter(s) connected to the bbattery typewire,L,DAB,bWire type used in the inductors of the dc-ac converter connected to the bbattery modelwire,L,DAB,b Wire model used in the inductor of the DAB converter(s) connected to the bbattery modelwire,Tx,DAB,b Wire model used in the transformer of the DAB converter(s) connected to the bbattery modelwire,L,DAB,b Wire model used in the inductors of the dc-ac converter connected to the bbattery nt,L,DAB,b Number of turns in the inductor of the DAB converter(s) connected to the bbattery nt,Tx,DAB,b Number of turns in the transformer of the DAB converter(s) connected to the bbattery February 21, 2025 22 of 25 Parameter Description nt,L,dc−ac,b Number of turns in the inductors of the dc-ac converter connected to the bbattery npwL,DAB,b Number of parallel conductors in the inductor of the DAB converter(s) connected to the bbattery npw,Tx,DAB,LV,b Number of parallel conductors in the LV side of the transformer of the DAB converter(s) connected to the bbattery npwTx,DAB,HV,b Number of parallel conductors in the HV side of the transformer of the DAB converter(s) connected to the bbattery npwL,dc−ac,b Number of parallel conductors in the inductor of the dc-ac converter connected to the bbattery Table A2. Design space. Parameter Design space npar,sw,DAB,LV,b1 to 4 npar,sw,DAB,HV,bUp to 2 npar,sw,dc−ac,bUp to 2 typesw,DAB,LV,LTO Discrete Si MOSFET, Discrete SiC MOSFET modelsw,DAB,LV,bLTO battery: - Si MOSFET: IRF100P218,IRF100P219,IPP023N10N5, IPP030N10N5,STF150N10F7,IPB120N10S4-03,SUP70090E, IPD122N10N3G,IPP126N10N3G - SiC MOSFET: UF3SC065007K4S AORF battery: Si MOSFET: SiHG018N60E,SiHG026N60EF,IPZ60R017C7, IPW60R017C7,IPW60R018CFD7,IPW60R024CFD7,IPW60R024P7, IPZA60R024P7,IPW60R041P6,IPW60R060P7 modelsw,DAB,HV,b SiC MOSFET modules: CAB006M12GM3,CAB008M12GM3, CAB011M12FM3,CAB016M12FM3 modelsw,dc−ac,b SiC MOSFET modules: CAB006M12GM3,CAB008M12GM3, CAB011M12FM3,CAB016M12FM3,CCB021M12FM3, CCB032M12FM3 VHV 700 V, 750 V, 800 V fs,DAB,b20 kHz, 24 kHz, ..., 92 kHz, 96 kHz, 100 kHz mf,b201, 219, 237, ..., 687, 705, 723 modelHS,DAB,LV,b February 21, 2025 23 of 25 Parameter Design space modelHS,DAB,HV,bFrom Advanced Thermal Solutions extrusion heat sinks catalogue: ATS-EXL6, ATS-EXL59, ATS-EXL66, ATS-EXL67, ATS-EXL68, ATS-EXL75 modelHS,dc−ac,b LHS,DAB,LV,b 2 to 8 inches LHS,DAB,HV,b LHS,dc−ac,b npar,cap,LV,b1 to 8 npar,cap,HV,b modelcap,LV,bLTO battery: - From Cornell Dubilier Electronics film capacitors: 935C1W3K-F, 935C1W20K-F,935C1W30K-F - From Cornell TDK film capacitors: B32529 AORF battery: From Cornell Dubilier Electronics film capacitors: UNL6W30K-F, UNL6W80K-F, UNL7W20K-F, UNL7W50K-F modelcap,HV,b From Cornell Dubilier Electronics film capacitors: 947D152K901DLRSN,947C102K901DCHS,947D112K102DLRSN, 947C641K102DBHS,947C321K122DAHS,944U101K122AC, 944U660K102AA ncore,L,DAB,b1 to 5 ncore,Tx,DAB,b1 to 5 ncore,L,dc−ac,b1 to 5 modelcore,L,DAB,b - From Magnetics cores catalogue: 0077164A7 (Powdercore), 0077169A7 (Powdercore), 0077101A7 (Powdercore), 0077336A7 (Powdercore), 0077614A7 (Powdercore), 0077869A7 (Powdercore), 0059188A2 (Edge), 0059909A2 (Edge), 0077327A7 (Powdercore) modelcore,Tx,DAB,b - From Magnetics cores catalogue: 00K114LE060 (Powdercore), 0077740A7 (Powdercore), 0077778A7 (Powdercore), 0077098A7 (Powdercore), 00K160LE026(Powdercore), 0077339A7 (Powdercore), 00K8038U026 (Powdercore), 0077165A7 (Powdercore), 0077169A7(Powdercore) modelcore,L,dc−ac,b - From Magnetics and TDK Electronics cores catalogue: E32/16/11 (Ferrite), 00K3112U090 (Powdercore), 00K114LE014 (Powdercore), 0077740A7 (Powdercore), 0077778A7 (Powdercore), 00K114LE060 (Powdercore), 0077620A7 (Powdercore), 0077098A7 (Powdercore), 00K160LE026 (Powdercore), 0077339A7 (Powdercore), 00K8038U026 (Powdercore), 0077165A7 (Powdercore) typewire,L,DAB,bRound, Foil, Litz February 21, 2025 24 of 25 Parameter Design space typewire,Tx,DAB,bRound, Foil, Litz typewire,L,DAB,bRound, Foil, Litz modelwire,L,DAB,bRound wires: 2 AWG to 30 AWG - Litz wires: from 0.04 mm diameter strand and 45 conductors per litz, to 0.28 mm diameter strand and 1350 conductors per litz modelwire,Tx,DAB,b modelwire,L,DAB,b nt,L,DAB,bUp to 80 turns nt,Tx,DAB,bUp to 80 turns nt,L,dc−ac,bUp to 80 turns npwL,DAB,bUp to 8 conductors npw,Tx,DAB,LV,bUp to 8 conductors npwTx,DAB,HV,bUp to 8 conductors npwL,dc−ac,bUp to 8 conductors February 21, 2025 25 of 25 References 1. Srivastava, A.K.; Kumar, A.A.; Schulz, N.N. Impact of Distributed Generations With Energy Storage Devices on the Electric Grid. IEEE Systems Journal 2012,6, 110–117. https://doi.org/10.1109/JSYST.2011.2163013. 2. Babatunde, O.M.; Munda, J.L.; Hamam, Y. A comprehensive state-of-the-art survey on power generation expansion planning with intermittent renewable energy source and energy storage. International Journal of Energy Research 2019,43, 6078–6107, [https://onlinelibrary.wiley.com/doi/pdf/10.1002/er.4388].https://doi.org/https://doi.org/10.1002/er.4388. 3. Zsiborács, H.; Baranyai, N.H.; Vincze, A.; Zentkó, L.; Birkner, Z.; Máté, K.; Pintér, G. Intermittent Renewable Energy Sources: The Role of Energy Storage in the European Power System of 2040. Electronics 2019,8.https://doi.org/10.3390/electronics8070729. 4. Suberu, M.Y.; Mustafa, M.W.; Bashir, N. Energy storage systems for renewable energy power sector integration and mitigation of intermittency. Renewable and Sustainable Energy Reviews 2014,35, 499–514. 5. D’Antonio, M.; Shi, C.; Wu, B.; Khaligh, A. Design and Optimization of a Solar Power Conversion System for Space Applications. IEEE Transactions on Industry Applications 2019,55, 2310–2319. https://doi.org/10.1109/TIA.2019.2891228. 6. Ralph, B. Comparative -- Pareto Optimization of Si and SiC Multi-Level Dual Active Bridge Topologies with Wide Input Voltage Range. IEEE Transactions on Power Electronics 2016,PP, 1–1. https://doi.org/10.1109/TPEL.2016.2614139. 7. Chong, L.W.; Wong, Y.W.; Rajkumar, R.; Rajkumar, R.; Isa, D. Hybrid energy storage systems and control strategies for stand-alone renewable energy power systems. Renewable and Sustainable Energy Reviews 2016,66, 174–189. https://doi.org/10.1016/j.rser.20 16.07.059. 8. De Doncker, R.W.; Divan, D.M.; Kheraluwala, M.H. A three-phase soft-switched high-power-density DC/DC converter for high-power applications. IEEE transactions on industry applications 1991,27, 63–73. 9. Ferreira, H.J.; Kouro, S.; Rojas, C.A.; Muller, N.; Rivera, S. Bidirectional Partial Power DC-DC Configuration for HESS interface in EV Powertrains. In Proceedings of the 2021 22nd IEEE International Conference on Industrial Technology (ICIT), 2021, Vol. 1, pp. 327–332. https://doi.org/10.1109/ICIT46573.2021.9453530. 10. Wang, C.S.; Li, W.; Wang, Y.F.; Han, F.Q.; Meng, Z.; Li, G.D. An Isolated Three-Port Bidirectional DC-DC Converter with Enlarged ZVS Region for HESS Applications in DC Microgrids. Energies 2017,10.https://doi.org/10.3390/en10040446. 11. Ankar, S.J.; Gangwar, A.; P, P.K. Efficient Bidirectional Power Flow Management in EV Powertrain: A Partial Power DC-DC Configuration for HESS Integration. In Proceedings of the 2024 IEEE 8th Energy Conference (ENERGYCON), 2024, pp. 1–6. https://doi.org/10.1109/ENERGYCON58629.2024.10488797. 12. Tian, J.; Ren, C.; Jia, Y.; Han, X.; Wang, P. Control strategy of HESS with dual active bridge bidirectional DC/DC converter in DC microgrid. In Proceedings of the 2017 12th IEEE Conference on Industrial Electronics and Applications (ICIEA), 2017, pp. 1449–1453. https://doi.org/10.1109/ICIEA.2017.8283067. 13. Erickson, R.W.; Maksimovic, D. Fundamentals of power electronics; Springer Science & Business Media, 2007. 14. Sorsdahl, T. Magnetic Design for High Temperature, High Frequency SiC Power Electronics. 2013. 15. Magnetics Inc. Powder Cores Catalog, 2011. 16. Defense, U. MIL-HDBK-217F reliability prediction of electronic equipment. Defense, US Department of 1995,28. 17. Burkart, R.; Kolar, J.W. Component cost models for multi-objective optimizations of switched-mode power converters. In Proceedings of the 2013 IEEE Energy Conversion Congress and Exposition, 2013, pp. 2139–2146. https://doi.org/10.1109/ECCE. 2013.6646971. 18. Azurza Anderson, J.; Zulauf, G.; Kolar, J.W.; Deboy, G. New Figure-of-Merit Combining Semiconductor and Multi-Level Converter Properties. IEEE Open Journal of Power Electronics 2020,1, 322–338. https://doi.org/10.1109/OJPEL.2020.3018220. 19. Burkart, R.M.; Kolar, J.W. Comparative Life Cycle Cost Analysis of Si and SiC PV Converter Systems Based on Advanced η - ρ - σ Multiobjective Optimization Techniques. IEEE Transactions on Power Electronics 2017,32, 4344–4358. https://doi.org/10.1109/ TPEL.2016.2599818.