Near-Data Computing: High Performance with Smart Data Processing for Data-Intensive Applications

cognizancejournal.com Pramod Peethambaran et al, Cognizance Journal of Multidisciplinary Studies, Vol.5, Issue.10, October 2025, pg. 356-364 (An Open Accessible, Multidisciplinary, Fully Refereed and Peer Reviewed Journal) ISSN: 0976-7797 Impact Factor: 5.183 Index Copernicus Value (ICV) = 92.57 ©2025, Cognizance Journal, ZAIN Publications, Fridhemsgatan 62, 112 46, Stockholm, Sweden, All Rights Reserved 356 Near-Data Computing: High Performance with Smart Data Processing for Data-Intensive Applications Pramod Peethambaran; Somnath Roy; Harsh Roogi; Mandar Sawant; Mayank Saxena https://semiconductor.samsung.com/about-us/locations/us-rnd-labs/memory-labs/data-fabric-solutions/ Samsung Semiconductors Inc., USA DOI: 10.47760/cognizance.2025.v05i10.032 cognizancejournal.com Pramod Peethambaran et al, Cognizance Journal of Multidisciplinary Studies, Vol.5, Issue.10, October 2025, pg. 356-364 (An Open Accessible, Multidisciplinary, Fully Refereed and Peer Reviewed Journal) ISSN: 0976-7797 Impact Factor: 5.183 Index Copernicus Value (ICV) = 92.57 ©2025, Cognizance Journal, ZAIN Publications, Fridhemsgatan 62, 112 46, Stockholm, Sweden, All Rights Reserved 357 Abstract: Near-data computing represents a paradigm shift in addressing challenges faced by data-intensive applications in modern computing systems. This comprehensive overview examines how computational bottlenecks arise from the fundamental separation of storage and processing in traditional architectures, necessitating extensive data movement that consumes significant energy and introduces substantial latency. Several innovative solutions are presented, including Computational Storage Drives (CSDs) that integrate processing capabilities directly within storage media, and Processing-in-Memory (PIM) technologies that incorporate computational elements into memory structures. Samsung's pioneering efforts in both domains demonstrate considerable improvements in performance, energy efficiency, and data transfer reduction across multiple application domains. The article explores memory-centric computing techniques leveraging technologies like Compute Express Link (CXL) and specialized architectures such as IMPICA for pointer chasing acceleration. Practical implementations, including RowClone for bulk data operations and ReRAM-based structures for neural networks, illustrate the transformative potential of near-data processing. The DAMOV benchmark suite provides a structured evaluation of processing-in-memory architectures through carefully designed case studies examining load balancing, accelerator performance, core models, and instruction offloading strategies. Keywords: Near-data Computing, Processing-in-Memory, Computational Storage, Energy Efficiency, Data Movement Reduction 1. Introduction Modern data-intensive applications face significant challenges in managing the massive data volumes being generated daily. With 2.5 EB of data created every day from text to images, music, and videos, data centers struggle with storage and computational demands as the bottlenecks shift across the system hierarchy [2]. As HeydariGorji et al. highlight, in I/O-intensive applications, the bandwidth mismatch between storage and processing units can become the primary bottleneck, with studies showing that up to 70% of training time for deep neural networks can be wasted on blocking I/O operations [2]. This inefficiency is further compounded when considering that data transferred from storage to the processor consumes 5,000× more energy and introduces 2,500× more latency compared to loading from volatile memory [2]. To address these challenges, computational storage drives (CSDs) have emerged as a promising solution. CSDs augment storage drives with processing resources while eliminating unnecessary data transmission to the host's CPU [2]. HeydariGorji et al. demonstrate that CSDs can achieve up to 3.1× speedup in processing while reducing energy consumption and data transfer by up to 67% and 68%, respectively, compared to regular enterprise solid state drives [2]. These improvements result from bringing computation directly to the storage medium, minimizing the movement of raw data to processing units. Complementing storage-level innovations, Samsung has pioneered Processing-in-Memory (PIM) technology that addresses challenges at the memory level. Samsung has become the first company in the cognizancejournal.com Pramod Peethambaran et al, Cognizance Journal of Multidisciplinary Studies, Vol.5, Issue.10, October 2025, pg. 356-364 (An Open Accessible, Multidisciplinary, Fully Refereed and Peer Reviewed Journal) ISSN: 0976-7797 Impact Factor: 5.183 Index Copernicus Value (ICV) = 92.57 ©2025, Cognizance Journal, ZAIN Publications, Fridhemsgatan 62, 112 46, Stockholm, Sweden, All Rights Reserved 358 industry to integrate PIM in High Bandwidth Memory (HBM) configurations by incorporating an AI engine called the Programmable Computing Unit (PCU) directly in the memory core [3]. This approach enables certain logic functions to be processed where the data resides, stimulating growth in AI applications that require continuous performance improvements [3]. Samsung's PIM technology in real-world testing for AI applications such as speech recognition has demonstrated a 2 times increase in performance compared to existing HBM [3]. Beyond performance gains, PIM significantly reduces power consumption—a critical concern for AI applications processing huge amounts of data. By implementing PIM, energy consumption is reduced by 70% in systems compared to existing HBM, making it particularly suited for AI applications with high power requirements [3]. A key advantage of both CSD and PIM approaches is their integration flexibility. Samsung's PIM can be applied without changing existing memory ecosystem environments and can be integrated with HBM, LPDDR, and GDDR memory [3]. For AI applications, PIM enables higher performance in capabilities like speech recognition, translation, and recommendation, unlocking the power of AI for changing business and everyday life [3]. 2. Compute Near Storage Approaches Samsung's Cognos [1] addresses the challenge of data movement by implementing a Zero-ETL approach. According to Lee et al., their Zero-ETL technology demonstrated 40% faster speed compared to AWS EMR-based ETL [4]. This performance gain comes from reducing analytics engines and eliminating bulk data transfers from storage to analytics engines for batch processing. Samsung's multi-phased approach incrementally scales data processing by moving compute functions to the data source. Their performance testing reveals consistent improvements across different data volumes, with latency reductions ranging from 38% to 42% compared to traditional EMR approaches. The framework provides integration through REST API to AI applications or Software Defined Storage hosts, making adoption straightforward for customers seeking to reduce cloud operational expenses [4]. Complementing this approach, Vinçon et al. present nKV, a RocksDB-based key/value store utilizing native computational storage with near-data processing. Operating directly on NVM/Flash storage, nKV eliminates intermediary layers along the I/O stack, particularly file systems [5]. Their implementation demonstrates notable performance improvements of 1.4×-2.7× over traditional approaches when executing operations on real hardware. The GET operation latency improved by 1.4×, SCAN bandwidth by 2×, and Betweenness Centrality by 2.7×. These gains come from intervention-free NDP-execution, where the device has complete address information, interprets data formats, and accesses data in situ without host interaction [5]. The system precisely controls physical data placement on chips and channels, critical for utilizing on-device I/O properties and compute parallelism. As demonstrated in their evaluation on a 2.4GB graph dataset with 48 million KV-pairs, nKV can execute various operations as software NDP on ARM cores or with FPGA hardware support, with complex operations showing the most significant improvements when hardware/software co-design is employed [5]. cognizancejournal.com Pramod Peethambaran et al, Cognizance Journal of Multidisciplinary Studies, Vol.5, Issue.10, October 2025, pg. 356-364 (An Open Accessible, Multidisciplinary, Fully Refereed and Peer Reviewed Journal) ISSN: 0976-7797 Impact Factor: 5.183 Index Copernicus Value (ICV) = 92.57 ©2025, Cognizance Journal, ZAIN Publications, Fridhemsgatan 62, 112 46, Stockholm, Sweden, All Rights Reserved 359 Both approaches highlight how computational storage delivers substantial performance benefits by minimizing data movement and bringing computation closer to data, particularly for data-intensive applications requiring complex processing operations. Operation/Approach Traditional Execution Time Computational Storage Execution Time SCAN Bandwidth (nKV) 553.0 MB (Deviceto-Host) 492.4 MB (NDP: Software Implementation+Hardware Acceleration) Betweenness Centrality (nKV) 6.958 sec 2.549 sec (NDP: Software Implementation+Hardware Acceleration) ETL Processing (Samsung Cognos) 5K years 7.65 min 4.4 min ETL Processing (Samsung Cognos) 10K years 15.27 min 8.8 min Table 1: Performance Comparison: Traditional vs. Computational Storage Approaches [4,5] 3. Memory-Centric Computing Solutions Near-data computing can be implemented at the system memory level through advanced technologies like Compute Express Link (CXL) and Processing-in-Memory (PIM). These approaches address dataintensive applications' increasing memory bandwidth demands, where conventional architectures encounter significant bottlenecks. According to Hassanpour's survey of near-data processing architectures for neural networks, modern data-driven applications are fundamentally limited by traditional computing systems based on the von-Neumann architecture, which separates memory from computing units [6]. The main performance and energy bottleneck is the memory hierarchy due to the huge number of inputs, weights, and partial outputs, resulting in numerous data movements that incur higher energy consumption than the operations themselves [6]. 3.1 CXL-Based Memory Computing Compute Express Link (CXL) technology enables memory-centric computing by providing coherent access to memory resources. Hassanpour's survey examines memory-centric approaches that employ coherent memory access technologies to alleviate the memory wall problem, which has become the main bottleneck of data-centric applications [6]. As shown in the performance gap analysis in Hassanpour's survey, while both processor and memory performance have been improving exponentially, the exponent for the processor is significantly higher than that of memory, in such a way that the difference between the two has also grown exponentially [6]. cognizancejournal.com Pramod Peethambaran et al, Cognizance Journal of Multidisciplinary Studies, Vol.5, Issue.10, October 2025, pg. 356-364 (An Open Accessible, Multidisciplinary, Fully Refereed and Peer Reviewed Journal) ISSN: 0976-7797 Impact Factor: 5.183 Index Copernicus Value (ICV) = 92.57 ©2025, Cognizance Journal, ZAIN Publications, Fridhemsgatan 62, 112 46, Stockholm, Sweden, All Rights Reserved 360 Hsieh's research on pointer chasing provides complementary insights into memory-bound workloads. Their profiling of real applications demonstrates that pointer chasing requires much higher cycles per instruction (6× in Memcached, 1.6× in DBx1000) and spends a much larger fraction of cycles waiting for last-level cache misses (16× in Memcached, 1.5× in DBx1000) compared to other application code [7]. This inefficiency stems from inherent serialization when accessing consecutive nodes, which limits available instruction-level and memory-level parallelism, as well as irregular allocation, causing frequent cache and TLB misses [7]. 3.2 Processing-in-Memory (PIM) Processing-in-Memory represents one of the most ambitious approaches to near-data computing, integrating computational logic directly within memory devices. Hassanpour's survey categorizes PIM architectures for neural networks based on memory technology, computational capabilities, and integration approach [6]. By moving computation closer to data, PIM aims to resolve the "Memory Wall" problem that has become the main bottleneck of data-centric applications [6]. Hsieh's research introduces the In-Memory PoInter Chasing Accelerator (IMPICA), which leverages the logic layer of 3D-stacked memory to accelerate pointer chasing operations [7]. Their evaluation shows that IMPICA improves the performance of pointer chasing operations in linked lists, hash tables, and Btrees by 92%, 29%, and 18%, respectively, while enhancing transaction throughput in a real database application by 16% and reducing latency by 13% [7]. IMPICA also significantly reduces system energy consumption (41%, 23%, and 10% for the three data structures, and 6% for a real database workload), while requiring only 7.6% of the area of a small embedded core [7]. Metric Improvement (%) Linked list traversal performance improvement 92% Hash table performance improvement 29% B-tree performance improvement 18% DBx1000 transaction throughput improvement 16% Energy reduction for linked list traversal 41% Energy reduction for hash table 23% Energy reduction for B-tree 10% Table 2: Performance and Energy Characteristics improvement with Near-Data Processing [6,7] 4. Workload Optimization and Performance Analysis Near-data computing offers substantial benefits for data-intensive workloads by minimizing costly data movement between processing units and memory. Seshadri et al. demonstrated that in modern systems, up to 42% of the energy required to access data from memory is consumed in driving the high-speed cognizancejournal.com Pramod Peethambaran et al, Cognizance Journal of Multidisciplinary Studies, Vol.5, Issue.10, October 2025, pg. 356-364 (An Open Accessible, Multidisciplinary, Fully Refereed and Peer Reviewed Journal) ISSN: 0976-7797 Impact Factor: 5.183 Index Copernicus Value (ICV) = 92.57 ©2025, Cognizance Journal, ZAIN Publications, Fridhemsgatan 62, 112 46, Stockholm, Sweden, All Rights Reserved 361 memory bus [8]. Their analysis revealed that bulk data operations significantly degrade system performance and energy efficiency as existing systems transfer large quantities of data across the memory channel, even though these operations require no computation. To address this challenge, Seshadri et al. proposed RowClone, a mechanism that performs bulk data operations entirely within DRAM. RowClone exploits the internal organization of DRAM to efficiently transfer an entire row (multiple KBs) of data with minimal changes to DRAM peripherals. Their evaluation showed that RowClone reduces the latency of a 4KB bulk copy operation from 1046ns to 90ns (11.6× improvement) and decreases energy consumption from 3.6μJ to 0.04μJ (74.4× reduction) compared to conventional systems [8]. For 4KB bulk zeroing operations, RowClone achieved 6.0× latency reduction and 41.5× energy savings. For neural network applications, Chen et al. highlighted how ReRAM-based in-memory computing architectures effectively address the memory wall problem. The ReRAM crossbar structure can transform matrix-vector multiplication computational complexity from O(n²) to O(1) while eliminating parameter fetching operations [9]. Chen et al.'s PRIME architecture demonstrated how preprogramming weight matrices into ReRAM cells enables efficient neural network acceleration. By performing computations directly within memory arrays, PRIME improved overall performance by approximately 2360× and reduced energy consumption by 895× compared to traditional architectures [9]. Chen et al. emphasized that ReRAM-based processors significantly enhance convolutional neural network efficiency by performing matrix-vector operations directly in memory. The evaluation of execution time showed that architectures like PRIME eliminated memory access time entirely, dramatically reducing processing latency compared to other designs where memory access constitutes nearly 100% of energy consumption [9]. Both approaches demonstrate that processing in or near memory provides substantial benefits for specific computational patterns. For bulk data operations, RowClone achieved over 11× performance improvement, while ReRAM-based architectures showed orders of magnitude efficiency gains for neural network computations. These results underline the critical importance of minimizing data movement for future computing systems focused on energy efficiency and performance enhancement. Architecture & Memory Technology Optimization Target Key Mechanism Performance Benefit Energy Benefit RowClone - DRAM Bulk Data Copy Fast Parallel Mode (FPM) using row buffer 11.6× faster for 4KB copy 74.4× less energy for a 4KB copy Bulk Data Zeroing FPM with reserved zero row 6.0× faster for 4KB zeroing 41.5× less energy for 4KB zeroing Inter-Bank Copy Pipelined Serial Mode (PSM) 1.9× faster for 4KB copy 3.2× less energy for 4KB copy Table 3: Analysis of DRAM-based In-Memory Processing Approaches [8,9] cognizancejournal.com Pramod Peethambaran et al, Cognizance Journal of Multidisciplinary Studies, Vol.5, Issue.10, October 2025, pg. 356-364 (An Open Accessible, Multidisciplinary, Fully Refereed and Peer Reviewed Journal) ISSN: 0976-7797 Impact Factor: 5.183 Index Copernicus Value (ICV) = 92.57 ©2025, Cognizance Journal, ZAIN Publications, Fridhemsgatan 62, 112 46, Stockholm, Sweden, All Rights Reserved 362 5. Case Studies The DAMOV benchmark suite provides a comprehensive framework for evaluating processing-inmemory (PIM) architectures through four case studies that systematically investigate data movement bottlenecks [11]. As Oliveira et al. demonstrate, these studies address critical challenges in near-data processing (NDP) implementation. The first case study examines load balancing and inter-vault communication in NDP systems. Using a 6×6 mesh Network-on-Chip (NoC) configuration, the analysis reveals that approximately 40% of memory requests travel 3-4 hops through the network, while less than 5% of requests are issued to local vaults [11]. This pattern emerged consistently across functions with different memory access behaviors, indicating significant communication overhead in current NDP architectures. As Mutlu et al. explain, such overhead significantly diminishes the theoretical bandwidth and latency benefits of placing computation near memory [10]. The second case study evaluates NDP accelerator performance across different application bottleneck classes using the Aladdin simulator. For the DRKYolo function (Class 1a - DRAM bandwidth-bound), the NDP accelerator achieves a 1.9× performance improvement compared to a compute-centric configuration. The PLYalu function (Class 1b - DRAM latency-bound) shows a 1.25× speedup, while PLY3mm (Class 2c - compute-bound) shows no improvement [11]. These findings align with Mutlu et al.'s observation that applications with poor locality and high memory intensity benefit most from PIM architectures [10]. The third case study conducts an iso-area and iso-power evaluation of different core models in NDP systems. Under the 4.4mm² area and 312 mW power constraints of a single HMC vault, researchers compared four out-of-order host CPU cores against two NDP configurations: six out-of-order cores or 128 in-order cores [11]. For DRKYolo, the in-order NDP configuration delivers 2× the performance of the out-of-order NDP configuration, despite the 21× difference in core count [11]. This demonstrates the tradeoffs in core complexity versus parallelism that Mutlu et al. identify as critical for efficient PIM implementations [10]. The final case study explores fine-grained instruction offloading by identifying "hottest" basic blocks responsible for most last-level cache misses. In LIGKcrEms, a single basic block generates 95.3% of LLC misses, while in HSJPRH, 90.9% of misses come from 10% of basic blocks [11]. Offloading these critical blocks provides up to 1.25× speedup compared to full function offloading, suggesting more targeted approaches to PIM acceleration, as advocated by Mutlu et al. for practical PIM adoption [10]. These studies collectively demonstrate that the DAMOV methodology provides valuable insights for developing efficient PIM architectures for diverse computational workloads [11]. cognizancejournal.com Pramod Peethambaran et al, Cognizance Journal of Multidisciplinary Studies, Vol.5, Issue.10, October 2025, pg. 356-364 (An Open Accessible, Multidisciplinary, Fully Refereed and Peer Reviewed Journal) ISSN: 0976-7797 Impact Factor: 5.183 Index Copernicus Value (ICV) = 92.57 ©2025, Cognizance Journal, ZAIN Publications, Fridhemsgatan 62, 112 46, Stockholm, Sweden, All Rights Reserved 363 Function Bottleneck Class Description Basic Block LLC Miss Distribution (%) DRKYolo Class 1a DRAM bandwidth-bound 95.3% from single block PLYalu Class 1b DRAM latency-bound 90.9% from 10% of blocks LIGKcrEms Class 1a DRAM bandwidth-bound 95.3% from single block HSJPRH Class 1b DRAM latency-bound 90.9% from 10% of blocks DRKRes Class 1c L1/L2 cache capacity-bound 89.2% from 10% of blocks Table 4: Performance characteristics of different memory bottleneck classes in Processing-in-Memory architectures [10,11] Conclusion Near-data computing emerges as a compelling solution to address the fundamental challenges of dataintensive applications by minimizing costly data transfers between processing units and memory structures. Both storage-level techniques, like Computational Storage Drives and memory-level innovations such as Processing-in-Memory, demonstrate substantial benefits across diverse workloads. The integration flexibility of these technologies enables adoption without disrupting existing system architectures while delivering significant performance gains and energy reductions. Memory-centric computing solutions effectively address the widening gap between processing capabilities and memory performance that constitutes the primary bottleneck in modern data-intensive applications. The transformative nature of technologies like RowClone for DRAM operations and ReRAM-based architectures for neural networks points to a future where computation increasingly occurs where data resides rather than following traditional data movement patterns. Evaluations through frameworks like DAMOV provide critical insights into optimizing processing-in-memory implementations for specific application characteristics. As data volumes continue expanding exponentially, these innovative near-data computing paradigms will become increasingly essential to maintain performance scaling while managing energy consumption constraints. The significant advancements demonstrated across multiple case studies suggest that data-centric computing architectures represent not merely an alternative but a necessary evolution for next-generation computing systems handling massive data processing requirements. cognizancejournal.com Pramod Peethambaran et al, Cognizance Journal of Multidisciplinary Studies, Vol.5, Issue.10, October 2025, pg. 356-364 (An Open Accessible, Multidisciplinary, Fully Refereed and Peer Reviewed Journal) ISSN: 0976-7797 Impact Factor: 5.183 Index Copernicus Value (ICV) = 92.57 ©2025, Cognizance Journal, ZAIN Publications, Fridhemsgatan 62, 112 46, Stockholm, Sweden, All Rights Reserved 364 References 1. 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