Exploring Neuromorphic Paradigms in Softwarized Networks: A Preliminary Study

Exploring Neuromorphic Paradigms in Softwarized Networks: A Preliminary Study Arthur J Simas , Christian Esteve Rothenberg Universidade Estadual de Campinas, Brazil [email protected], cheste[email protected] Abstract—Nature has perfected efficient ways to process information—like how our brains quickly recognize faces or learn new skills using minimal energy. Neuromorphic computing is a biologically inspired computing paradigm that mimics the brain’s neural architecture to achieve high efficiency and adaptive learning. Current research focuses on scaling neuromorphic systems for energy-efficient AI acceleration, robotics, video recognition, alongside advances in Spiking Neural Networks (SNNs), in-memory computing architectures (e.g., memristors), and hardware-software codesign for applications like autonomous systems and healthcare diagnostics. While neuromorphic computing has shown promise in other domains, its role in softwarized networks remains underexplored. This paper presents the early stage of the doctoral research, outlining the required investigations to leverage neuromorphic computing in softwarized networks. We discuss the methodology, involved challenges, limitations, and potential impacts of this novel intersection. Index Terms—Neuromorphic computing, Spiking neural networks, Softwarized networks, Cognitive network management I. INTRODUCTION Modern softwarized networks rely on centralized, GPUheavy Machine Learning (ML) models for tasks like traffic engineering, traffic classification, and attack detection, leading to high energy costs and latency [1]. With data centers consuming 1.5% of global electricity in 2024 and set to more than double by 2030 [2], neuromorphic computing emerges as a disruptive alternative. Neuromorphic computing is a biologically inspired paradigm that mimics the brain’s neural architecture through spiking neuron models, which are mathematical descriptions of how electrical signals are conducted in neurons. Unlike traditional von Neumann systems, this paradigm offers ultra-low-power, adaptive learning by leveraging sparse, asynchronous spikes for event-driven processing and computation [3]. Example use cases span data-intensive AI acceleration in edge [4], and real-time video [5] and voice [6] recognition. While neuromorphic computing has demonstrated remarkable success in these domains, its potential in softwarized networks remains largely underexplored. Current network architectures face fundamental limitations that neuromorphic paradigms could address, yet critical gaps hinder this convergence. Traditional network control mechanisms rely on rigid, pre-programmed policies and energy-intensive ML models, lacking the cognitive adaptability Figure 1: General architecture of a Spiking Neural Network. required for increasingly dynamic environments. For instance, Deep Neural Networks (DNNs) have been applied to tasks like traffic classification, but their computational overhead and inability to process event-driven data efficiently create bottlenecks in real-time decision-making [7]. The potential of neuromorphic computing to transform networking lies in its intrinsic properties: Spiking Neural Networks (SNNs) naturally process asynchronous, eventbased data—aligning perfectly with network telemetry and bursty traffic patterns—while offering orders-of-magnitude improvements in energy efficiency. However, key challenges must be addressed: (i) First, the mapping between network functions and neuromorphic primitives remains unexplored; (ii) Second, it is unclear how to best translate traditional network data into spike-based representations without losing semantic fidelity; (iii) Additionally, existing neuromorphic hardware platforms were not designed with networking workloads in mind, raising questions about high-throughput packet processing scenarios; (iv) Finally, limited access to neuromorphic hardware presents a significant barrier to practical experimentation. This doctoral research takes a first step toward addressing these gaps by initiating an investigation into the feasibility of neuromorphic computing in softwarized networks. Our initial scope focuses on identifying high-impact use cases, developing simulation frameworks and a hardware testbed to evaluate neuromorphic approaches against conventional ones. The remainder of this paper is structured as follows: § II provides background and discusses the state of the art in neuromorphic computing; § III examines the challenges and limitations in the neuromorphic application to networking; § IV then presents the research methodology; § V explores the potential impacts of this work; followed by the closing remarks and future perspectives in § VI. II. BACKGROUND AND STATE OFTHE ART Bioinspiration in computing draws from biological systems to solve complex engineering challenges, with neuromorphic computing representing one promising implementation of this approach. These systems differ fundamentally from traditional von Neumann architectures in five key ways that mirror biological neural systems [3]: 1) Parallelism: Unlike traditional CPUs, all neurons and synapses in a neuromorphic system operate simultaneously, enabling true parallel processing; 2) Unified memory and processing: These systems eliminate the von Neumann bottleneck by colocating computation and memory, with each synaptic connection both processing signals and storing weights; 3) Scalability: The architecture scales seamlessly—adding more neuromorphic chips simply increases available neurons and synapses, allowing networks to grow organically like biological neural systems; 4) Event-driven: Computation occurs only when spikes happen, making these systems exceptionally energyefficient since they remain idle until needed; 5) Stochasticity: Incorporating controlled randomness in neuron firing patterns mimics biological neural variability, enabling noise-tolerant computation and resilient models. By modeling key features of the brain’s neural networks, neuromorphic systems implement biological principles through SNNs—a fundamentally different approach to computation compared to traditional artificial neural networks. Unlike conventional models that process continuous values at fixed intervals (i.e. CPU clock pulses), SNNs communicate through analog, asynchronous spikes (similar to biological neurons), as shown in Fig. 1, where both the timing and frequency of these spikes carry information. This event-driven operation provides (i) energy efficiency, as computations only occur when spikes are present; (ii) eliminates the bottleneck between the memory and computation; and (iii) high parallelism, as all neurons operate simultaneously. The sparse, spike-based communication in SNNs closely resembles how actual neural networks minimize energy use while maintaining computational power [4], making them particularly suitable for edge computing applications where power constraints exist. Recent advances have demonstrated significant progress across four key research directions: algorithmic innovations, hardware developments, enabling toolchains for neuromorphic systems, and domain-specific applications—with networking emerging as a promising but underexplored use case. In the algorithmic direction, authors have worked in foundational methods: Krausse et al. [8] presents a novel implementation of the Hodgkin-Huxley neuron model; learning methods: The continual learning problem in deep neural networks is studied by the authors of Daram et al. [9], and the proposed model, NEO, is able to achieve stateof-the-art performance. Pedersen et al. [10] proposes a novel method using translationand scale-invariance receptive fields to achieve faster convergence. Authors of Rizzo et al. [11] address the problem of training on data from event-based cameras by using downsampling, making it possible for the model to play the Atari Pong game. The impact of noisy input is studied by Patel et al. [12], which proves to produce more robust models when introduced in the training phase; dataset development: Orchard et al. [13] presents a method to convert regular vision datasets to neuromorphic sensors, resulting in the neuromorphic version of the MNIST and Caltech101 datasets. Kriener et al. [14] presents Yin-Yang, a new dataset alternative focused in the early-stage prototyping scenarios of both neural network models and hardware; and implementing algorithms using the neuromorphic computing paradigm: the authors of Snyder et al. [15] proposes a neuromorphic implementation of the Bayesian Optimization methodology, which is open-sourced as part of the Lava Software Framework. Theilman et al. [16] implements on the Loihi platform the Goemans-Williamson approximation algorithm for the NP-hard problem MAXCUT. In the side of hardware innovations, memristor is the electrical component that authors most develop upon: Aklah et al. [17] explores the implementation of memristor devices in FPGA boards, while Tolba et al. [18] further expands this idea by developing a memristor IP core. Han et al. [19] uses memristors to create long-term memory in neuromorphic neural networks. Jiang et al. [20] proposes a read-write crossbar array of memristors to accelerate neural network circuit modules. Xiao et al. [21] studies and proposes a novel method to solve the latent problem of fixed-time synchronization of neural networks between the asynchronous and synchronous domains. The field has developed enabling toolchains to overcome hardware interfacing challenges: Lohoff et al. [22] implements a JAX-like interface in C++ and Python to map a computational graph to memristive crossbar arrays. Knight et al. [23] presents mlGeNN, an interface to define, train, and test SNNs on GPU. Building on the neuromorphic concepts and using neuromorphic systems, domain-specific applications can be realized, such as in vision systems: Stewart et al. [5] shows a method to track quadcopters within the visual field of neuromorphic cameras. Abernot et al. [24] presents a faster implementation of the SIFT state-of-the-art algorithm for image edge detection using oscillatory neural networks. Li et al. [25] introduces a neural network model to address the complexity and large memory usage of existing gesture recognition algorithm models; voice: Stewart et al. [6] showcases speech2spikes, a processing pipeline to encode audio into spikes, suitable for real-time voice recognition in low-power neuromorphic systems; and networking: Bai et al. [4] implements a low-power hybrid deep neural network model alternative for data-intensive deep learning algorithms, allowing them to be run on limited resource edge devices. III. CHALLENGES AND LIMITATIONS The integration of neuromorphic computing into softwarized networks presents several fundamental challenges that must be addressed before widespread adoption becomes feasible. A. Gap between the relationship of network functions to neuromorphic primitives A gap exists in understanding how traditional network functions—such as routing, congestion control, and traffic classification—can be effectively implemented using neuromorphic primitives like spike encoding, synaptic plasticity, and event-driven processing. While SNNs have demonstrated success in data-intensive applications running on edge devices [4], their application to network control logic remains largely unexplored. B. Spike-encoding of network data SNNs excel at processing temporal, event-based data, but translating traditional network telemetry (e.g., flow statistics, packet headers) into spike trains without losing semantic fidelity remains an open problem. Unlike sensory data (e.g., vision, audio), network data is often high-dimensional, discrete, and sparsely correlated over time. Current spike encoding methods (e.g., rate coding, temporal coding) may discard critical network state information. C. Hardware suitability for network-specific application Existing neuromorphic platforms (e.g., Intel Loihi) were not designed high-throughput packet processing. Unlike SmartNICs or GPUs, neuromorphic hardware lacks the I/O bandwidth to handle line-rate traffic in core networks. While neuromorphic architectures are scalable, real-world deployments must integrate with existing network switches and routers, which were not designed for SNN inference. D. Hardware accessibility barriers The niche nature and high prototyping costs of neuromorphic computing create practical obstacles for researchers. Few institutions possess neuromorphic testbeds or have access to neuromorphic hardware, limiting experimentation and validation of novel frontiers. To democratize research, an open neuromorphic system is required, enabling broader innovation without reliance on specialized, proprietary, and high-cost hardware. IV. METHODOLOGY The proposed doctoral research aims to address gaps in the state-of-the-art by exploring the feasibility of neuromorphic softwarized networks. For this end, this research seeks to answer the following core questions: [RQ.1] Can network functions be implemented using SNNs or assisted by SSNs? and [RQ.2] Can neuromorphic hardware match the performance requirements of network-specific applications, or are adaptations required? To attain the research questions, we will use the following methodology, divided into three aspects: Practical experimentation. The methodology begins with GPU-accelerated simulations to explore how to spike-encode network data and the link between network functions and neuromorphic primitives. High-impact use cases, such as adaptive routing, traffic classification, and quality of service management, will be modeled using SNNs in simulation environments like Lava and snnTorch, allowing for rapid prototyping and validation of spike-based network management. Once promising approaches are identified, the study will transition to benchmarking on actual neuromorphic hardware (e.g., Intel Loihi, BrainScaleS) to evaluate realworld performance, energy efficiency, and scalability. This two-phase experimental approach directly addresses RQ.1 by determining whether SNNs can effectively implement or assist network functions, while also providing preliminary insights into RQ.2 by assessing hardware compatibility with networking workloads. Hardware study. Another component of this research involves evaluating existing neuromorphic hardware platforms to determine their suitability for network-specific applications. This entails studying architectures such as Loihi, BrainScaleS, SpiNNaker2, and memristor-based systems for key networking metrics, including throughput, latency, and power consumption under realistic traffic loads. Special attention will be given to identifying hardware limitations—such as I/O bottlenecks or insufficient neuron density—that may hinder deployment in high-speed networks. Additionally, the study will explore potential modifications, such as integrating neuromorphic coprocessors in SmartNICs, to bridge the gap between spikebased computation and packet processing requirements. This analysis directly informs RQ.2, clarifying whether current neuromorphic systems can meet networking demands or if specialized adaptations are necessary. Broaden the access to neuromorphic hardware. To overcome the accessibility barriers of proprietary neuromorphic platforms, this research will investigate the development of an open-source FPGA-based neuromorphic system designed for off-the-shelf deployment. By leveraging FPGA programmability, the project aims to create a modular, scalable SNN implementation that researchers can deploy on commodity hardware, reducing dependency on niche and costly platforms. This initiative not only facilitates practical benchmarking (RQ.2) but also fosters wider experimentation in neuromorphic networking. The resulting framework will be paired with open datasets and toolchains, enabling the community to validate and extend findings while accelerating progress in the field. This step ensures that the benefits of neuromorphic computing—such as ultra-low-power operation and event-driven efficiency—can be realistically assessed and adopted in networking scenarios. V. POTENTIAL IMPACTS The integration of neuromorphic computing into softwarized networks could yield transformative impacts across computational efficiency, network adaptability, and sustainability. Neuromorphic computing’s event-driven operation and colocated memory-processing architecture could drastically reduce the energy footprint of network control systems. By replacing GPU-heavy DNNs with SNNs, data centers might achieve lower power consumption per inference compared to traditional ML models; and dynamic load-dependent energy use, where idle networks consume near-zero power until spikes trigger computation. Such gains could mitigate the projected doubling of data center energy use by 2030 [2]. Impacts in cognitive networks are expected by enabling selflearning and decision-making at the edge. Traditional cognitive architectures rely on centralized ML models that struggle with real-time adaptation and energy constraints. Synaptic plasticity mechanisms could allow networks to autonomously reconfigure routing paths or Quality of Service (QoS) policies based on spike-encoded traffic patterns. By processing only spike-based events, resource-efficient cognition can be achieved in neuromorphic cognitive agents (e.g., in IoT gateways), enabling ubiquitous deployments. SNNs could enable adaptive routing or congestion control that reacts to traffic spikes asynchronously, avoiding the latency of centralized ML inference. The stochasticity of SNNs could improve robustness in noisy edge networks, where packet loss or sensor errors degrade traditional ML performance. Synaptic plasticity mechanisms might allow networks to self-optimize policies in response to evolving traffic patterns, reducing manual reconfiguration. VI. CLOSING REMARKS AND FUTURE PERSPECTIVES This doctoral research investigates the transformative potential of neuromorphic computing in softwarized networks, covering relevant gaps in algorithms and data encoding mapping, hardware suitability, and accessibility. Our preliminary findings suggest that SNNs offer a promising alternative to traditional GPU-heavy ML models, particularly for event-driven, energy-efficient network control tasks. By leveraging the intrinsic properties of neuromorphic systems—such as sparse spike-based communication, synaptic plasticity, and ultra-low-power operation—this work seeks to demonstrate the feasibility in high-impact use cases, resulting in neuromorphic softwarized networks. Key research directions include hybrid neuromorphicvon Neumann architectures for packet processing, optimized spike encoding for network telemetry, and co-designing neuromorphic hardware with networking workloads in mind. Bridging the gap in neuromorphic computing and softwarized networks will require interdisciplinary collaboration—advances in algorithms, hardware, and system integration must converge to realize bioinspired, cognitive networks at scale. ACKNOWLEDGMENT This work was supported by Ericsson Telecomunicac¸ ˜ oes LTDA , and by the S˜ ao Paulo Research Foundation (FAPESP) , grant 2021/00199-8, CPE SMARTNESS . This study was partially funded by CAPES, Brazil - Finance Code 001. REFERENCES [1] R. Boutaba, M. A. Salahuddin, et al., “A comprehensive survey on machine learning for networking: Evolution, applications and research opportunities,” Journal of Internet Services and Applications, 2018. [2] “Energy and AI,” IEA, Paris, Tech. Rep., 2025. [Online]. Available: https://www.iea.org/reports/energy-and-ai. [3] C. D. Schuman, S. R. Kulkarni, et al., “Opportunities for neuromorphic computing algorithms and applications,” Nature Computational Science, 2022. [4] K. Bai, S. Liu, et al., “High speed and energy efficient deep neural network for edge computing,” in ACM/IEEE Symposium on Edge Computing, 2019. [5] T. Stewart, M.-A. Drouin, et al., “Using neuromorphic cameras to track quadcopters,” in International Conference on Neuromorphic Systems, 2023. [6] K. M. Stewart, T. Shea, et al., “Speech2spikes: Efficient audio encoding pipeline for real-time neuromorphic systems,” in NeuroInspired Computational Elements Conference, 2023. [7] K. Kim, J.-H. Lee, et al., “Deep rnn-based network traffic classification scheme in edge computing system,” Computer Science and Information Systems, 2022. [8] J. Krausse, D. Scholz, et al., “Extreme sparsity in hodgkinhuxley spiking neural networks,” in International Conference on Neuromorphic Computing (ICNC), 2023. [9] A. Daram and D. Kudithipudi, “Neo: Neuron state dependent mechanisms for efficient continual learning,” in Neuro-Inspired Computational Elements Conference, 2023. [10] J. E. Pedersen, R. Singhal, et al., “Translation and scale invariance for event-based object tracking,” in Neuro-Inspired Computational Elements Conference, 2023. [11] C. P. Rizzo, C. D. Schuman, et al., “Neuromorphic downsampling of event-based camera output,” in Neuro-Inspired Computational Elements Conference, 2023. [12] K. P. Patel and C. D. Schuman, “Impact of noisy input on evolved spiking neural networks for neuromorphic systems,” in Neuro-Inspired Computational Elements Conference, 2023. [13] G. Orchard, A. Jayawant, et al.,Converting static image datasets to spiking neuromorphic datasets using saccades, 2015. [Online]. Available: https://arxiv.org/abs/1507.07629. [14] L. Kriener, J. G¨ oltz, et al., “The yin-yang dataset,” in Neuro-Inspired Computational Elements Conference, 2022. [15] S. Snyder, S. R. Risbud, et al., “Neuromorphic bayesian optimization in lava,” in International Conference on Neuromorphic Systems, 2023. [16] B. H. Theilman and J. B. Aimone, “Goemans-williamson maxcut approximation algorithm on loihi,” in Neuro-Inspired Computational Elements Conference, 2023. [17] Z. Aklah, A. Al-Safi, et al., “Exploring fpga implementation and emulation of memristor devices,” International Journal of Computational Methods and Experimental Measurements, 2024. [18] M. F. Tolba, M. E. Fouda, et al., “Memristor fpga ip core implementation for analog and digital applications,” IEEE Transactions on Circuits and Systems II: Express Briefs, 2019. [19] J. Han, J. Sun, et al., “Memristor-based neural network circuit of long-term memory,” in International Conference on Neuromorphic Computing (ICNC), 2021. [20] N. Jiang, M. Jiang, et al., “A parallel read-write circuit design for driving memristor crossbar array,” in International Conference on Neuromorphic Computing (ICNC), 2023. [21] J. Xiao, Y. Hu, et al., “A novel method of fixed-time synchronization of neural networks,” in International Conference on Neuromorphic Computing (ICNC), 2023. [22] J. Lohoff, Z. Yu, et al., “Interfacing neuromorphic hardware with machine learning frameworks - a review,” in International Conference on Neuromorphic Systems, 2023. [23] J. C. Knight and T. Nowotny, “Easy and efficient spike-based machine learning with mlgenn,” in Neuro-Inspired Computational Elements Conference, 2023. [24] M. Abernot, S. Gauthier, et al., “Sift-onn: Sift feature detection algorithm employing onns for edge detection,” in Neuro-Inspired Computational Elements Conference, 2023. [25] F. Li, X. Na, et al., “Lightweight yolov5 gesture recognition optimization algorithm,” in International Conference on Neuromorphic Computing (ICNC), 2023.