D2.2. Active gate drivers for high-power, highfrequency WBG devices

1 D2.2. Active gate drivers for high-power, highfrequency WBG devices Reinventing High-performance pOwer converters for heavy-Duty electric trAnSport Grant Agreement Number 101056896 Deliverable name: D2.2 Active gate drivers for high-power, highfrequency WBG devices Deliverable number: D7 Deliverable type: R Work Package: WP2: Design of electric and electronics components Lead beneficiary: UPC Contact person: Alejandro Paredes /[email protected] Dissemination Level: Public Due date for deliverable: December 31, 2023 Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or CINEA. Neither the European Union nor the granting authority can be held responsible for them. Ref. Ares(2024)6273650 - 04/09/2024 D2.2 Active gate drivers for high-power, high-frequency WBG devices Version v.2.3 2 DOCUMENT CONTROL PAGE Author(s): Alejandro Paredes (UPC), Luis Gomez (UPC) Contributor(s): Luis Romeral (UPC) Reviewer(s): Markus Koller (AIT) Version number: v.2.3 Contractual delivery date: 31 – 12 – 2023 Actual delivery date: 04 – 09 – 2024 Status: Submitted REVISION HISTORY Version Date Author/Reviewer Notes v.0 20 – 10 – 2023 Alejandro Paredes (UPC) Creation, First Draft v.0.1 24 – 01 – 2024 Luis Romeral (UPC) Reviewed v.1 29 – 01 – 2024 Alejandro Paredes (UPC) Simulations review and Workbench/Lab tests definition v.2 28 – 07 – 2024 Luis Romeral (UPC) Discussions and improvements v.2.1 05 – 08 – 2024 Markus Koller (AIT) Reviewed v.2.2 04 – 09 – 2024 Luis Romeral (UPC) Final version submitted ACKNOWLEDGEMENTS The work described in this publication was subsidised by Horizon Europe (HORIZON) framework through the Grant Agreement Number 101056896. DISCLAIMER Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or CINEA. Neither the European Union nor the granting authority can be held responsible for them. D2.2 Active gate drivers for high-power, high-frequency WBG devices Version v.2.3 3 TABLE OF CONTENTS DOCUMENT CONTROL PAGE....................................................... 2 REVISION HISTORY ...................................................................... 2 ACKNOWLEDGEMENTS ................................................................ 2 DISCLAIMER .................................................................................. 2 TABLE OF CONTENTS................................................................... 3 LIST OF FIGURES .......................................................................... 5 LIST OF TABLES ............................................................................ 6 LIST OF ACCRONYMS ................................................................... 7 EXECUTIVE SUMMARY ................................................................. 8 1. INTRODUCTION ....................................................................... 9 1.1 DESCRIPTION OF THE DOCUMENT AND PURSUE .......................... 9 1.2 WPS AND TASKS RELATED WITH THE DELIVERABLE .................... 9 2. GATE DRIVERS OVERVIEW .................................................. 10 2.1 GATE DRIVERS’ ISSUES AND REQUIREMENTS ............................. 10 2.2 GATE DRIVING TECHNIQUES FOR WBG DEVICES ........................ 13 3. GATE DRIVING APPROACH BASED ON HIGH-FREQUENCY PWM ............................................................................................. 15 3.1 GATE DRIVING CONCEPT ................................................................ 15 3.2 GATE DRIVING PROCESS ................................................................ 16 3.3 GATE DRIVING CRUCIAL PARAMETERS DEFINITION ................... 17 3.4 TRANSITION TIMES ........................................................................... 17 D2.2 Active gate drivers for high-power, high-frequency WBG devices Version v.2.3 4 4. GATE DRIVING EVALUATION AT OPEN LOOP CONTROL .. 18 4.1 TIME STAGE EVALUATIONS ............................................................. 19 4.2 GATE-DRIVING EVALUATION BY MEANS SIMULATIONS .............. 21 5. GATE DRIVING EXPERIMENTAL EVALUATION ................... 23 5.1 GATE DRIVING PROTOTYPING AND SETUP .................................. 23 5.2 GATE-DRIVING ON FPGA IMPLEMENTATION ................................. 23 5.3 EXPERIMENTAL RESULTS AND CIRCUIT’S CHALLENGES ........... 24 5.4 CHALLENGES AND LIMITATIONS OF GATE DRIVING APPROACH 26 6. GATE DRIVING FOR RHODAS WBG CONVERTER ............. 28 7. CONCLUSION AND NEXT STEPS ......................................... 30 7.1 CONCLUSIONS .................................................................................. 30 7.2 NEXT STEPS ...................................................................................... 30 REFERENCES .............................................................................. 31 D2.2 Active gate drivers for high-power, high-frequency WBG devices Version v.2.3 5 LIST OF FIGURES Figure 3.1. The gate-driving concept and waveforms representation .......................... 15 Figure 3.2. Power circuit for active gate driving design and validation ......................... 16 Figure 4.1. LTspice model for gate-driving evaluation ................................................. 18 Figure 4.2. Representation of time transitions of GaN by simulations ......................... 20 Figure 4.3. Currents and voltages of GaN under gate-driving method at turn-on. ........ 21 Figure 4.4. Currents and voltages of GaN under gate-driving method at turn-off ......... 22 Figure 5.1. Gate driver experimental set-up ................................................................ 23 Figure 5.2 Artix 7-FPGA architecture and concept for gate driving pulses generation . 24 Figure 5.3. FPGA and totem pole driver outputs; High frequency PWMs and expected Vg profile .................................................................................................................... 24 Figure 5.4. Gate driving comparison on one operating cycle. Vds=200V, Id 4 A maximum and fs=100kHz. ........................................................................................................... 25 Figure 5.5. Gate driver comparison at turn-on transition. Vds = 200 V, Id =4 A and fs=100kHz ................................................................................................................... 25 Figure 5.6. Gate driver comparison at turn-off transition. Vds=200 V, Id = 4 A and fs=100kHz. .................................................................................................................. 26 Figure 6.1. The overall structure of the high-power inverters of RHODAS ................... 28 Figure 6.2. A gate-driving adaptation approach ........................................................... 29 D2.2 Active gate drivers for high-power, high-frequency WBG devices Version v.2.3 6 LIST OF TABLES Table 2.1 Commercial GDs compatible with GaN Transistors ..................................... 12 Table 3.1. Equations to determine the time transitions of GaN transistor .................... 17 Table 4.1. GaN Transistor and totem-pole main specifications ................................... 18 Table 4.2. GaN transistor parameters and parasitic elements used for calculations and simulations .................................................................................................................. 19 Table 4.3. GD Simulation Assessment Specifications ................................................. 19 Table 4.4. Transition times results comparison ........................................................... 19 Table 4.5. Power losses comparison .......................................................................... 22 Table 4.6. Overshoots comparisons ............................................................................ 22 Table 6.1. RHODAS converter specifications .............................................................. 28 Table 6.2. ADuM4121ARIZ gate driver specifications ................................................. 29 D2.2 Active gate drivers for high-power, high-frequency WBG devices Version v.2.3 7 LIST OF ACCRONYMS AGD Active gate drivers ASIC Application-specific integrated circuit CPLD Complex programmable logic device DESAT Desaturation EMI Electromagnetic interference ESD Electrostatic discharge FPGA Field programmable gate array GD Gate driver GDC Gate driver circuit GaN Gallium nitride IC Integrated circuit LUT Lookup table OC Over current OVLO Over-voltage lockout PLL Phase-locked loop MCU Microcontroller unit MMCM Mixed-mode clock manager SiC Silicon Carbide UVLO Under-voltage lockout WBG Wide bandgap D2.2 Active gate drivers for high-power, high-frequency WBG devices Version v.2.3 8 EXECUTIVE SUMMARY Active gate driving has been shown to provide reduced circuit losses and improved switching waveform quality in power electronic circuits. Featuring higher switching speed and lower losses, the silicon carbide MOSFETs and GaN devices are widely used in higher power density and higher efficiency power electronic applications as a new solution. However, the increase of the switching speed induces oscillations, overshoots, electromagnetic interference (EMI) and even additional losses. High – voltage, high – power T-Type RHODaS SiC/GaN inverter uses power devices working at 1000VDC in DC bus, while intermediate GaN leg has to support 500VDC as a rated voltage. Reducing voltage and current overshoots becomes crucial to allow the use of 650V GaN, which represent the current available technology. This deliverable studies, develops and tests a novel active gate driver (AGD) for highpower GaN switches, that allows to fully using its potential of high-speed characteristic under different operation temperatures and load currents. The principle of the AGD is based on drive voltage decrement during the voltage and current slopes since high dV/dt and dI/dt are the source of the overshoots, oscillations and EMI problems. This voltage control is achieved by a duty-adjustable high frequency pulse train generated by a FPGA that modifies the input and output sides of the PWM pulses applied to the gate of the transistor, thus generating a variable drive voltage that change according the switching conditions. Compared to conventional gate driver (CGD) with fixed drive voltage, the proposed AGD has the capability of suppressing the overshoots, oscillations and reducing losses without compromising the EMI. Analytical developments, simulations and experimental results are showed in the deliverable, which are the basis for the future utilization of these advanced gated drivers in RHODaS power converters. D2.2 Active gate drivers for high-power, high-frequency WBG devices Version v.2.3 9 1. INTRODUCTION 1.1 DESCRIPTION OF THE DOCUMENT AND PURSUE Gate driving methods for GaN transistors based on gate current control, gate resistance change, or gate-source voltage (Vgs) modifications are essential issues for improving GaN devices, enhancing existing GD circuits, and allowing advanced new GD systems, especially for high-voltage and high-power applications. Therefore, this deliverable presents the analysis and development of advanced gate drivers for SiC MOSFETs and GaN devices, which could be used as Active Gate Drivers (AGD) in commercial power converters. The document also describes the usual, commercial gate drivers, their functions, advantages, and disadvantages. In addition, the issues and challenges of using commercial gate drivers (GDC) and encounters when designing with new gate driver circuit approaches are discussed, particularly for GaN transistors. The document includes a gate-driving approach for GaN power devices and the proposal's modelling, design, and parameter definitions. The gate-driving is fully evaluated using LTspice for simulations and validated with laboratory tests. Finally, an AGD based on gate driving is delineated to be applied to WBG semiconductors like those used in RHODAS converters. 1.2 WPS AND TASKS RELATED WITH THE DELIVERABLE This deliverable refers to Task 2.3 included in WP2: Design of electric and electronics components. D2.2 Active gate drivers for high-power, high-frequency WBG devices Version v.2.3 16 The high-frequency PWMs are generated by an FPGA connected to a simple commercial totem pole circuit to supply the required current for the GaN power devices, as shown in Figure 3.2. This circuit includes the parasitic DUT GaN model, inductive load, and critical inductances as Lloop. Figure 3.2. Power circuit for active gate driving design and validation 3.2 GATE DRIVING PROCESS Considering Figure 3.1 in the first half of the PWM period, the Vg profile starts just as the conventional PWM for regular charging the input capacitances up to the Miller plateau at t2. At this point, Vg falls to Miller Voltage (VMiller) to limit the gate current (Ig); from this point, the Vg increases until the gate-source voltage (Vgs) reaches the nominal Vcc at t4, then shapes a slope signal. From this time, Vg remains at Vcc until the first half of the PWM period ends. It is important to note that the VMiller of the Vgs with standard PWM (Figure 3.1 d, orange waveform line) defines the inflexion point for shaping the Vg profile. When the Vg profile is applied, the new Vgs (Figure 3.1 d, doted waveform in Figure 3.1) will cause a lower level of VMiller due to the drop voltage of Rg. As the VMiller with new Vgs is lower than conventional Vgs, the gate driving would warranty the expected results. Considering again Figure 3.1, in the second half of the PWM period, the Vg profile (Figure 3.1 d orange line) remains just as the conventional PWM for regular discharging of the output capacitances until the Miller plateau ends (t8). At this point, Vg rises to VMiller to restrict the Ig; from this point, the Vg goes until the Vgs reaches the nominal lower voltage (GND) using a slope as a reference. From this time, Vg remains at GND until the second half of the PWM period ends. With the defined Vgg profile, the drain current (Id) and drain-source voltage (Vds) should behave better, with lower turn-on and turn-off transition oscillations, as shown in Figure 3.1 e). D2.2 Active gate drivers for high-power, high-frequency WBG devices Version v.2.3 17 3.3 GATE DRIVING CRUCIAL PARAMETERS DEFINITION Figure 3.1 shows that the 𝑉𝑉𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚 and transition stages are essential for the gate-driving definition. Therefore, these parameters must be known or calculated to achieve the expected Vg profile. The Miller voltage (VMiller) is a voltage reference for the star of the high-frequency PWM, which should be calculated or defined. Manufacturers always provide the Vth, and often, they proportionate the 𝑉𝑉𝑉𝑉𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖 as constant and the same value for turn-on and turn-off. In practice, Vmiller can change due to system dynamics and could be different for turn-on and turn-off transitions. Nevertheless, Vmiller has been defined in the literature [19] and can be approximated by (1) and (2). 𝑉𝑉𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚−𝑜𝑜𝑜𝑜 =�𝑉𝑉𝑉𝑉ℎ 𝐺𝐺𝑚𝑚𝑅𝑅𝑔𝑔𝐶𝐶𝐺𝐺𝐺𝐺+𝐼𝐼𝐿𝐿𝑅𝑅𝑔𝑔𝐶𝐶𝐺𝐺𝐺𝐺+𝑉𝑉𝑔𝑔(𝐶𝐶𝐺𝐺𝐺𝐺+𝐶𝐶𝐺𝐺𝐷𝐷) �1+𝐺𝐺𝑓𝑓𝑓𝑓𝑅𝑅𝑔𝑔�𝐶𝐶𝐺𝐺𝐺𝐺+𝐶𝐶𝐺𝐺𝐷𝐷 � (1) 𝑉𝑉𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚−𝑜𝑜𝑜𝑜𝑜𝑜 =�𝑉𝑉𝑡𝑡ℎ𝐺𝐺𝑚𝑚𝑅𝑅𝑔𝑔𝐶𝐶𝐺𝐺𝐺𝐺+𝐼𝐼𝐿𝐿𝑅𝑅𝑔𝑔𝐶𝐶𝐺𝐺𝐺𝐺 �1+𝐺𝐺𝑚𝑚𝑅𝑅𝑔𝑔�𝐶𝐶𝐺𝐺𝐺𝐺+𝐶𝐶𝐺𝐺𝐷𝐷 � (2) Where the capacitances CGD and CDS can be obtained by 𝐶𝐶𝑚𝑚𝑖𝑖𝑖𝑖 =𝐶𝐶𝑔𝑔𝑖𝑖 +𝐶𝐶𝑔𝑔𝑔𝑔, 𝐶𝐶𝑜𝑜𝑖𝑖𝑖𝑖 =𝐶𝐶𝑔𝑔𝑖𝑖 + 𝐶𝐶𝑔𝑔𝑔𝑔 and 𝐶𝐶𝑚𝑚𝑖𝑖𝑖𝑖 =𝐶𝐶𝑔𝑔𝑔𝑔. The capacitances 𝐶𝐶𝑚𝑚𝑖𝑖𝑖𝑖,𝐶𝐶𝑜𝑜𝑖𝑖𝑖𝑖, 𝐶𝐶𝑚𝑚𝑖𝑖𝑖𝑖 can be found in the datasheets by the manufactures. 3.4 TRANSITION TIMES There are various methods to obtain the transition times. The manufacturer in the datasheets provides approximate turn-on and turn-on transition times; however, they are defined as an ideal case study without considering circuit parasitic elements. This simple model differs from the final application, where various parasitic elements are present, such as the transistor loop inductances, power loop inductances and the printed circuit parasitic elements. In the literature, models often fit equations and models to determine the energy and losses of transistors, seeking values closer to real behavior [19], [20], [21]. Table 3.1 shows the summary of the equations to approximate the time stages. Table 3.1. Equations to determine the time transitions of GaN transistor Stage Times by calculations 𝑡𝑡don 𝑡𝑡𝑔𝑔−on = (𝑅𝑅𝑔𝑔Ciss)ln( 𝑉𝑉 gs (𝑉𝑉 gs −𝑉𝑉 miller )−𝑉𝑉 TH ) 𝑡𝑡ir 𝑡𝑡ir = ( 5 ∗(𝑅𝑅𝑔𝑔 (𝐶𝐶gd1 +𝐶𝐶gs)) ) −𝑡𝑡𝑔𝑔_on 𝑡𝑡vf 𝑡𝑡vf =𝑅𝑅𝑔𝑔 ∗( 𝑄𝑄 gd 𝑉𝑉 DS )∗( 𝑉𝑉 DS 𝑉𝑉 gs −𝑉𝑉 miller ) 𝑡𝑡𝑚𝑚𝑜𝑜𝑔𝑔−𝑜𝑜𝑜𝑜 𝑡𝑡_𝜏𝜏2= 5 ∗(𝑅𝑅𝑔𝑔 (𝐶𝐶gd2 +𝐶𝐶gs)) 𝑡𝑡on−total Ton_total =𝑡𝑡𝑔𝑔−on +𝑡𝑡ir +𝑡𝑡vf +𝑡𝑡_𝜏𝜏2 𝑡𝑡doff 𝑡𝑡𝑔𝑔−off = 𝜏𝜏2= 5 ∗(𝑅𝑅𝑔𝑔 (𝐶𝐶gd2 +𝐶𝐶gs)) 𝑡𝑡vr 𝑡𝑡vr =𝑅𝑅𝑔𝑔 ∗( 𝑄𝑄 gd 𝑉𝑉DS )∗( 𝑉𝑉 DS 𝑉𝑉miller−off ) 𝑡𝑡if 𝑡𝑡if =�( 𝑔𝑔𝑚𝑚∗𝐿𝐿𝑔𝑔)∗(𝑅𝑅𝑔𝑔∗𝐶𝐶gd)(𝑉𝑉miller−𝑉𝑉th 𝑉𝑉miller ) 𝑡𝑡𝑚𝑚𝑜𝑜𝑔𝑔−𝑜𝑜𝑜𝑜𝑜𝑜 𝑡𝑡_𝜏𝜏1=𝑅𝑅𝑔𝑔𝐶𝐶issln( 𝑉𝑉 th 0.01∗𝑉𝑉th ) 𝑡𝑡off−total Toff_total =𝑡𝑡𝑔𝑔−off +𝑡𝑡vr +𝑡𝑡if +𝑡𝑡_𝜏𝜏1 D2.2 Active gate drivers for high-power, high-frequency WBG devices Version v.2.3 18 4. GATE DRIVING EVALUATION AT OPEN LOOP CONTROL The gate-driving concept presented in Section 3 has been developed and validated by simulation in the LTspice framework using the circuit shown in Figure 4.1, based on the circuit defined in Figure 3.2. The used LTspice simulation model comprises commercial models of GaN transistors and totem pole driver components provided by manufacturers. Figure 4.1. LTspice model for gate-driving evaluation The GaN transistor model GS-065-011-1-L by GaN System was used for all analyses. Meanwhile, the totem pole driver LTspice model used was the IC MAX5048C from Analog Devices manufacturer. Table 4.1 shows GaN transistor and totem pole driver parameters taken from the datasheet. Table 4.1. GaN Transistor and totem-pole main specifications Component Characteristics Symbol Value Units GaN Transistor GS-065-011-L Drain to source voltage VDS 650 [V] Continuous drain current IDS 7.2 [A] Gate-to-source voltage VGS -10 to 7 [V] Drain-to-source Resistance RDS(on) 150 [mΩ] Turn-On Delay TD(on) 5 [ns] Rise Time tR 5 [ns] Turn-Off Delay TD(off) 8 [ns] Fall Time tF 10 [ns] Totem-pole Driver MAX5048C Voltage operating range V+ + 4 to 14 [V] Maximum Output current Iout 7 [A] Propagation delay TD-ON/TD-OFF 8 [s] Rise time tR 5 [ns] Fall time tF 4 [ns] The LTspice GaN model considers critical parasitic capacitances and inductances obtained from papers, datasheets, and application notes. In addition, it includes other parameters such as VMiller, Vth, and Vgs, which are crucial for calculating the time transition and voltage set points for gate drive applications. Table 4.2 shows the main parasitic elements, key voltages, and resistances for time transition determination. D2.2 Active gate drivers for high-power, high-frequency WBG devices Version v.2.3 19 Table 4.2. GaN transistor parameters and parasitic elements used for calculations and simulations Parameters Value Parameters Value C ds 19.6 pF L d 5 nH Cgd 0.4 pF Lg 5 nH Cgs 69.6 pF Ls 10 nH C iss 70 pF L loop 5 nH Coss 20 pF Lload 350 uH Crss 0.4 pF Rload 47 Ω QGD 0.7 nC Rg 10 Ω C ds 19.6 pF V gs 6 V Vmiller 3 V Vmiller-on 2 V Vth 1.7 V Vmiller-off 1.6 V The parameters Vmiller-on and Vmiller-off in Table 4.2 have been obtained by using Equations 1 and 2. As previously commented, these voltages define the start points of variable PWMs at GaN transitions. On the other hand, Table 4.3 shows the electrical specifications to perform the simulations. Table 4.3. GD Simulation Assessment Specifications Parameter Value Vdc bus [V] 200 Maximum Load current [A] 4 Switching frequency [kHz] 100 duty cycle of primary PWM [%] 50 4.1 TIME STAGE EVALUATIONS Calculations were performed to obtain the time steps required for the gate control definition considering Figure 3.1, which are t2, t4, t8 and t10. The time steps were calculated using Table 3.1 and the specifications shown in Table 4.1, Table 4.2 and Table 4.3. Furthermore, simulations were developed to measure these same times. Table 4.4 compares the equivalent time steps obtained by analysis and simulations. On the other hand, Figure 4.2 shows the time transitions. The color codes are those defined in Figure 3.1 Table 4.4. Transition times results comparison Stage Times by calculations Times by simulations Turn -on 𝒕𝒕 𝟐𝟐 = 𝑡𝑡 don + 𝑡𝑡 ir 3.77 ns 3.61 ns 𝒕𝒕𝟒𝟒= 𝑡𝑡2+𝑡𝑡vf + 𝑡𝑡𝑚𝑚𝑜𝑜𝑔𝑔−𝑜𝑜𝑜𝑜 14.58 ns 34.01 ns Turn -off 𝒕𝒕 𝟖𝟖 = 𝑡𝑡 doff + 𝑡𝑡 vr 13.14 ns 25.42 ns 𝒕𝒕𝟏𝟏𝟏𝟏 = 𝑡𝑡8+𝑡𝑡if + 𝑡𝑡𝑚𝑚𝑜𝑜𝑔𝑔−𝑜𝑜𝑜𝑜𝑜𝑜 21.14 ns 50.43 ns D2.2 Active gate drivers for high-power, high-frequency WBG devices Version v.2.3 20 As shown in Table 4.4, the time steps have the same order of magnitude, although there are some differences in the values that define the new shape of the PWM pulse, which are 52% in the case of (tdon + tir) and 3% for the time (tvf + (t3-t4). Figure 4.2. Representation of time transitions of GaN by simulations As expected, the time transitions of the GaN devices is very short, which limits the operating range to actuate on the PWM gate signal, to generate the adjustable duty cycle trend. However, However, using a high frequency PWM pulses conformer it is still possible to modify the voltage profile of the applied PWM gate signal. By using LTspice to simulate the gate driving it is possible determining the pulse quantities and the periods of each pulse (see Figure 3.1 b). The obtained results are analyzed in the next section. D2.2 Active gate drivers for high-power, high-frequency WBG devices Version v.2.3 21 4.2 GATE-DRIVING EVALUATION BY MEANS SIMULATIONS The expected profile was defined in LTspice, and the gate-driving concept was evaluated based on the conditions defined in Table 4.3 and the transition times obtained in Table 4.4. Simulations were performed and results of advanced gate driving was compared with conventional gate driving based on a single Rg to analyze the performance advantages. The gate driving was evaluated in open loop and at different operating points in both turn-on and turn-off transitions. Figure 4.3 and Figure 4.4 show the results obtained. Ideal Vg profile and duty-adjust pulses were simulated for observing the effect of the gate driving. The ideal Vg profile was generated by using the PWL LTspice tool. On the other hand, to generate and adjust the duty of the high-frequency pulse sequence and achieve the expected profile, the standard PWM was considered a reference at the switching frequency of the GaN transistors, 100 kHz, in these simulations. Then, to generate the high-frequency PWM, a triangular signal (carrier signal at 200 MHz) was compared with the desired profile (reference signal) to obtain the desired duty-adjusted pulse sequence. The color codes in Figure 4.3 and Figure 4.4 are as follows: Green color, original waves without modifying the PWM gate driver pattern; Blue color, theoretical waves when applying a modified PWM gate drive pattern; Red color, resulting waves after applying the developed PWM concept to the PWM gate drive pattern. Figure 4.3. Currents and voltages of GaN under gate-driving method at turn-on. D2.2 Active gate drivers for high-power, high-frequency WBG devices Version v.2.3 22 Figure 4.4. Currents and voltages of GaN under gate-driving method at turn-off From Figure 4.3 and Figure 4.4, both for turn-on and turn-off, it can be concluded that advanced gate driving can reduce the overshoots and amplitude of the oscillations without a significant increase in delays at the transitions. To verify the performance, a quantitative comparison of the GaN power losses and overshoots between the gatedriving approach and conventional gate driver was performed. Table 4.5 shows the power losses. Meanwhile, Table 4.6 shows the overshoot percentages. Table 4.5. Power losses comparison Type Ptotal (W) Psw-on (W) Psw-off (W) Pcond (W) Conventional GD 0.7419 0.2359 0.1390 0.3569 Proposed GD 0.8272 0.3082 0.1532 0.3565 Table 4.6. Overshoots comparisons Turn-on overshoot reduction (%) Turn-off overshoot reduction (%) 𝑉𝑉 𝐷𝐷𝐷𝐷 15 2,8 𝐼𝐼𝐷𝐷 40,29 13 The comparison shows that the proposed gate control technique has slightly higher switching losses than the conventional method. For instance, if we consider Pconduction = 0.3569 W, with the conventional gate driver the losses are PCLosses = 0.2359 W + 0.1390 W = 0.7419 W. On the other hand, losses resulting of applying the proposed gate driver method are PPLosses = 0.3082 W + 0.1532 W + 0.3565 W. Based on this calculation, the estimated losses are 11.49%, indicating the effectiveness of this method. Considering the total device losses, these increase by 11.49%. However, the reduction of the peak current Id and voltage Vds is 15% and 40.29%, respectively, which reduces the risk of overcurrent and overvoltage stress and breakdown of the circuit in high-power industrial applications. This conclusion is particularly important for the use of GaN devices in high-voltage-high-power applications, as is the case of the RHODaS project, due to the limited maximum ranges in voltages and currents available in the current generation of GaN transistors. D2.2 Active gate drivers for high-power, high-frequency WBG devices Version v.2.3 23 5. GATE DRIVING EXPERIMENTAL EVALUATION 5.1 GATE DRIVING PROTOTYPING AND SETUP The developed gate driver is evaluated in the laboratory to investigate its feasibility in real conditions. As shown in Figure 5.1, a setup based on the circuit presented in Figure 3.2 was mounted. This setup uses GaN devices GS-065-011-1-L, Totem-pole Driver MAX5048C, and an FPGA Artix 7 on a board by Digilent to generate the duty-adjustable high-frequency pulses to conform the PWM gate drive pulses. Figure 5.1. Gate driver experimental set-up The electrical parameters shown in Table 4.3 were used for the laboratory analysis of the gate driving. The tests were performed in two stages. In the first stage, the dutyadjustable high-frequency pulses was generated in the FPGA to analyze the correct generation of pulses. After that, the gate drive PWM pulses were modified to obtain the expected profiles. In the second part, the power stage was installed, and the advanced gate driving was applied to the transistor for voltage and current behavior evaluation. 5.2 GATE-DRIVING ON FPGA IMPLEMENTATION As is shown in Figure 5.2, the duty adjust pulse sequences in the FPGA were created by using a frequency divider (MMCM or PLL), which is generated by using a phase shift stage with six clocks synchronized at the same sampling frequency. The output signal of the phase shifter enters the duty generator stage, which is based on programmable logic blocks to generate different duty cycles. In parallel, a custom profile is at the lookup table (LUT) connected to the desired profile (referenced to the PWM standard) enters the programmable logic blocks stage. Finally, D2.2 Active gate drivers for high-power, high-frequency WBG devices Version v.2.3 24 with a MUX and an additional programable logic block called a pulse generator, the dutyadjust pulse sequence is achieved for turn-on and turn-off of the GaN transitions. Figure 5.2 Artix 7-FPGA architecture and concept for gate driving pulses generation Figure 5.3. FPGA and totem pole driver outputs; High frequency PWMs and expected Vg profile As is shown in Figure 5.3, it was possible to generate the duty-adjustable high-frequency pulses; however, the FPGA Digilent Basic board has limitations concerning the physical clock, which has a frequency of 100 MHz, which limits the period of the duty-adjustable pulses. Applying the frequency divider shown in Figure 5.2, it was possible to achieve a resolution with a minimum step of 2.5 ns. With this step time, it was possible to prove the gate-driving method. 5.3 EXPERIMENTAL RESULTS AND CIRCUIT’S CHALLENGES To compare the behavior of the transistors', conventional gate drivers based on a single resistance were applied, like the simulation previously presented. conventional gate driver (a) and the new gate driving method (b). The developed gate was applied to a GaN transistor mounted in an experimental circuit with a scheme as shown in Figure 3.2. The loading and control parameters are presented in Table 4.2 and Table 4.3. The Id and the Vds were measured on the resulting circuit. D2.2 Active gate drivers for high-power, high-frequency WBG devices Version v.2.3 25 To compare the behavior of the transistors, conventional gate drivers based on a single resistor were applied, as was done also in the simulation presented above. Figure 5.4 shows the Vds and Id with the conventional gate driver (a) and the new gate control method (b). An impressive reduction in Id peak can be seen at the turn-on switching, without significantly affecting the rest of the on/off parameters. Figure 5.4. Gate driving comparison on one operating cycle. Vds=200V, Id 4 A maximum and fs=100kHz. As shown in Figure 5.4, experimental measurements demonstrate that the new gate drive technique can reduce the overshoot current Id. Figure 5.5 and Figure 5.6 show details of the on-off transitions of the conventional (main) gate drivers and the (modified) gate drive technique. Figure 5.5. Gate driver comparison at turn-on transition. Vds = 200 V, Id =4 A and fs=100kHz Figure 5.5 shows that the gate control technique results in a better turn-on transition. The overshoot can be reduced to just 50% and the ringing can also be significantly reduced without a significant increase in transition delay. Figure 5.6 shows the voltage overshoot limitation that is achieved with the proposed method at the turn-off transition, which is reduced by 12.5% while also reducing the voltage ringing. D2.2 Active gate drivers for high-power, high-frequency WBG devices Version v.2.3 32 [13] M. Lamine Beye et al., “Active Gate Driver and Management of the Switching Speed of GaN Transistors dur-ing Turn-On and Turn-Off,” vol. 10, no. 2, 2021, doi: 10.3390/electronics10020106ï. [14] W. J. Zhang et al., “A Smart Gate Driver IC for GaN Power HEMTs with Dynamic Ringing Suppression,” IEEE Trans Power Electron, vol. 36, no. 12, pp. 14119– 14132, Dec. 2021, doi: 10.1109/TPEL.2021.3089679. [15] H. C. P. Dymond et al., “A 6.7-GHz Active Gate Driver for GaN FETs to Combat Overshoot, Ringing, and EMI,” IEEE Trans Power Electron, vol. 33, no. 1, pp. 581–594, Jan. 2018, doi: 10.1109/TPEL.2017.2669879. [16] S. Yu et al., “A 400-V Half Bridge Gate Driver for Normally-off GaN HEMTs with Effective dv/dt Control and High dv/dt Immunity,” IEEE Transactions on Industrial Electronics, 2022, doi: 10.1109/TIE.2022.3153808. [17] R. Katada et al., “5 V, 300 MSa/s, 6-bit Digital Gate Driver IC for GaN Achieving 69 % Reduction of Switching Loss and 60 % Reduction of Current Overshoot,” in Proceedings of the International Symposium on Power Semiconductor Devices and ICs, Institute of Electrical and Electronics Engineers Inc., May 2021, pp. 55– 58. doi: 10.23919/ISPSD50666.2021.9452225. [18] D. Liu et al., “Full Custom Design of an Arbitrary Waveform Gate Driver with 10GHz Waypoint Rates for GaN FETs,” IEEE Trans Power Electron, vol. 36, no. 7, pp. 8267–8279, Jul. 2021, doi: 10.1109/TPEL.2020.3044874. [19] S. Liu, S. Song, N. Xie, H. Chen, X. Wu, and M. Zhao, “Miller plateau corrected with displacement currents and its use in analyzing the switching process and switching loss,” Electronics (Switzerland), vol. 10, no. 16, Aug. 2021, doi: 10.3390/electronics10162013. [20] B. Lasek, P. Trochimiuk, R. Kopacz, and J. Rąbkowski, “Parasitic-based active gate driver improving the turn-on process of 1.7 kv sic power mosfet,” Applied Sciences (Switzerland), vol. 11, no. 5, pp. 1–16, Mar. 2021, doi: 10.3390/app11052210. [21] Y. Sukhatme, V. K. Miryala, P. Ganesan, and K. Hatua, “Digitally Controlled Gate Current Source-Based Active Gate Driver for Silicon Carbide MOSFETs,” IEEE Transactions on Industrial Electronics, vol. 67, no. 12, pp. 10121–10133, Dec. 2020, doi: 10.1109/TIE.2019.2958301.