Application of Clock Enable Technique in Power Optimization of a 32-Bit Adder on FPGA

Available online at www.rajournals.in RA JOURNAL OF APPLIED RESEARCH ISSN: 2394-6709 DOI:10.47191/rajar/v11i11.02 Volume: 11 Issue: 11 November 2025 International Open Access Impact Factor8.553 Page no.- 973-977 973 Hang Thuy Vu1, RAJAR Volume 11 Issue 11 November 2025 Application of Clock Enable Technique in Power Optimization of a 32-Bit Adder on FPGA Hang Thuy Vu1, Khoi Huy Do2 1,2Faculty of Engineering and Technology, University of Information and Communication Technology, Thai Nguyen University, Vietnam ARTICLE INFO ABSTRACT Published Online: 04 November 2025 Corresponding Author: Hang Thuy Vu The adder is a fundamental logic block in most digital processing systems, but it is also a significant source of power consumption due to its high switching frequency. This paper presents the application of the Clock Enable (CE) technique to reduce dynamic power in a 32bit adder implemented on FPGA. Instead of directly gating the clock signal, the input and output registers of the adder are controlled by the CE signal, maintaining their values when the adder is inactive. Experimental results on a Spartan-3E FPGA show that dynamic power is reduced by approximately 58.6%, total power decreases by 36.6%, and junction temperature drops by 2°C compared to the conventional design. This technique is simple, easy to integrate, and provides significant benefits for low-power digital design. KEYWORDS: Low-power design, Clock Enable (CE), FPGA implementation, 32-bit adder optimization, Dynamic power reduction. I. INTRODUCTION In digital circuit design, particularly on FPGA platforms, power consumption has increasingly become a critical challenge alongside performance and area considerations [1], [2]. Adders frequently appear in Arithmetic Logic Units (ALUs), Digital Signal Processors (DSPs), and embedded AI systems [4]. Therefore, optimizing power consumption in adders has a direct impact on the overall system efficiency [4], [5]. Common techniques such as Dynamic Voltage and Frequency Scaling (DVFS), Multi-Threshold Voltage (MultiVt) design, and operand isolation have been widely studied; however, they require specific levels of hardware/EDA support. In contrast, the Clock Enable (CE) technique is readily available on most FPGAs, allowing flip-flops (FFs) to freeze their states without interfering with the global clock network [2], [3]. This paper focuses on investigating and evaluating the effectiveness of CE when applied to the design of a 32-bit adder on FPGA [3]-[5], focusing on its ability to suppress unnecessary switching activity while maintaining correct timing behavior. II. THEORETICAL BACKGROUND In today’s semiconductor market, high performance and low power consumption are two key factors that greatly contribute to the commercial viability of an integrated circuit (IC) [6], [7]. The low-power criterion has become increasingly important and is now widely used as a benchmark to compare chips within the same market segment. In particular, for battery-powered applications, mobile devices, and systems relying on wireless energy sources, achieving ultra-low power consumption is a critical requirement [8]. When two chip families are equivalent in terms of functionality and performance, the one that consumes less power is considered to have better energy efficiency [6], [8]. The power consumption of a chip is primarily associated with the operation of CMOS circuits [7], [9]. In essence, the total power consumption consists of the following components: total dynamic static P P P=+ Here, dynamic P represents the dynamic power (switching power), which is the energy required to charge or discharge the capacitance at the output load. static P also denotes the static power (leakage power), which is the energy lost due to leakage currents when the logic remains in a steady state without any switching activity [9]. “Application of Clock Enable Technique in Power Optimization of a 32-Bit Adder on FPGA” 974 Hang Thuy Vu1, RAJAR Volume 11 Issue 11 November 2025 The dynamic power consumption of a chip is the sum of transient power consumption and capacitive load power consumption. dynamic T L P P P=+ The transient power consumption is calculated using the following formula: 2 w ddT s pd i P N C V f= Here, ws N denotes the number of switching bits. pd C is the capacitance associated with dynamic energy dissipation. It represents the intrinsic capacitance calculated when there is no load and the output does not switch. dd V is the supply voltage, and i f is the input signal frequency [6]. The capacitive load power consumption is calculated as follows: 2 w ddL s L o P N C V f= where: ws N is the number of switching outputs , L C is the load capacitance at the output, dd V is the supply voltage, o f is the output signal frequency. The above formulas indicate that power consumption can be reduced by lowering ws N , which is achieved by decreasing the number of switching bits in the signals. In ASIC design, the clock gating technique is widely employed to disable the clock for either the entire circuit or specific sections when they are not required to operate. However, on FPGAs, implementing clock gating manually with logic gates is prone to glitches, which may compromise timing safety and the reliability of the clock tree[7]. Each flip-flop in an FPGA is equipped with an additional Clock Enable (CE) input. When CE = 1, the flip-flop operates normally, latching new input data to the output at every clock edge. Conversely, when CE = 0, the flip-flop ignores both the clock and the input data, retaining its current output value. This mechanism allows the circuit to “freeze its state” without turning off the physical global clock signal [8], [9]. This capability forms the basis for reducing unnecessary switching activities in FPGA designs, thereby lowering dynamic power consumption. It can be affirmed that CE provides a simple yet highly effective mechanism to suppress redundant switching inside FPGA logic, ultimately reducing dynamic power without compromising circuit stability[9], [10]. III. METHODOLOGY AND DESIGN DESCRIPTION A. Baseline 32-Bit Adder Design Without Using CE Figure 1: Block diagram of the 32-bit adder without using the Clock-Enable (CE) technique Figure 2: Architecture of the 32-bit adder without using the Clock-Enable (CE) technique Figure 2 illustrates the basic architecture of a conventional 32-bit adder without using the Clock Enable (CE) signal. Input flip-flops (FFs): The signals ,, in in in A B C are directly latched into flip-flops by the clock. Since CE is not used, the flip-flops always update their data at every clock edge, regardless of whether the adder block is required to operate. 32-bit adder core (Adder 32-bit): Immediately after the input FFs, the data is fed into the 32-bit adder. Because the input data continuously changes with every clock cycle, the adder is forced to perform computations at all times. As a result, internal switching activities are generated, even during cycles when the computation results are not actually needed. Output flip-flops (FFs): The results Sum and Cout from the adder are also latched into output flip-flops at every clock edge. Since CE is not used, the output FFs continuously update with new results, which then propagate through subsequent logic blocks. The RTL schematic of the 32-bit adder without using CE is shown in Figure 3. “Application of Clock Enable Technique in Power Optimization of a 32-Bit Adder on FPGA” 975 Hang Thuy Vu1, RAJAR Volume 11 Issue 11 November 2025 Figure 3: RTL schematic of the 32-bit adder without using the Clock-Enable (CE) technique B. Design of a 32-Bit Adder Using the Clock-Enable (CE) Technique Figure 4 shows the block diagram of the 32-bit adder with CE. Figure 5 illustrates the operation of the 32-bit adder when applying the Clock-Enable (CE) technique in two different states: Figure 4: Block diagram of the 32-bit adder using the Clock-Enable (CE) technique Figure 5: Architecture of the 32-bit adder using the Clock-Enable (CE) technique (a) CE = 0 - Hold state / No switching: When the CE signal is set to 0, the input flip-flops ( ,, in in in A B C ) do not latch new data but retain their current values. Since the inputs of the 32-bit adder remain unchanged, the adder does not generate internal switching activity, and the outputs (Sum/Cout) stored in the output flip-flops also remain unchanged. This state effectively eliminates all unnecessary switching activities, thereby significantly reducing dynamic power consumption. (b) CE = 1 - Normal operation / Switching active: When the CE signal is set to 1, the input flip-flops allow new data to be latched at the next clock edge. These values are then fed into the 32-bit adder, which performs the computation and generates the results (Sum/Cout). The output flip-flops are also updated accordingly, reflecting the correct addition results at each clock cycle. In this state, the adder operates normally and consumes dynamic power proportional to the switching activity. The technology schematic of the 32-bit adder with CE is illustrated in Figure 6. Figure 6: Technology schematic of the 32-bit adder using the Clock-Enable (CE) technique In this study, the 32-bit adder was designed and implemented on FPGA in two versions to compare power consumption efficiency: (i) a baseline adder without the Clock-Enable (CE) signal, and (ii) an enhanced adder with CE functionality to disable unnecessary operations. “Application of Clock Enable Technique in Power Optimization of a 32-Bit Adder on FPGA” 976 Hang Thuy Vu1, RAJAR Volume 11 Issue 11 November 2025 In the design without CE, both the input and output flipflops continuously update new data at every clock edge. This forces the 32-bit adder to remain active, generating internal switching activities even when the addition results are not required. In contrast, in the CE-enabled design, the flip-flops only latch data when CE = 1, and retain their previous values when CE = 0. As a result, the adder can remain “idle” during inactive cycles, eliminating unnecessary switching activities and thereby significantly reducing dynamic power consumption. To evaluate the effectiveness of the CE technique, the design process was described in VHDL and synthesized and simulated using Xilinx ISE Design Suite 14.7. Power analysis was performed with XPower Analyzer, based on switching activity data obtained from ISim simulation (VCD file). The experiments were carried out on an FPGA Spartan-3E (XC3S500E, package FG320), with a core supply voltage of 1.2 V, a clock frequency of 50 MHz, and an ambient temperature of 25 °C. The two adder versions were directly compared in terms of total power consumption, dynamic power, static power, and junction temperature. V. RESULTS The experimental results demonstrate a clear difference in power consumption between the two versions of the 32-bit adder. Table 1 presents a comparison of total power, dynamic power, static power, and junction temperature between the design without Clock Enable (CE) and the design with CE. Table 1: Comparison of Power Consumption of the 32bit Adder With and Without Clock Enable (CE) Design Total Power (W) Dynamic Power (W) Static Power (W) Junction Temperature (°C) Without CE 0.216 0.133 0.083 30.6 With CE 0.137 0.055 0.082 28.6 The results show that the dynamic power consumption of the adder decreases from 0.133 W to 0.055 W, corresponding to a power saving of 58.6%. The total power consumption is also reduced from 0.216 W to 0.137 W, equivalent to a 36.6% reduction. In addition, the FPGA junction temperature decreases from 30.6 °C to 28.6 °C, representing a reduction of approximately 2 °C. Meanwhile, the static power remains almost unchanged (0.083 W compared to 0.082 W), which is consistent with the theoretical expectation that the Clock Enable (CE) technique only affects the dynamic switching activity within the digital circuit. Figure 7 illustrates the comparison of dynamic and total power consumption between the two designs. It is evident that the design employing the Clock Enable (CE) technique demonstrates superior energy efficiency, particularly in reducing unnecessary switching activity. Figure 7: Comparison of Power Consumption of the 32bit Adder These results indicate that the Clock Enable (CE) technique is a simple yet highly effective mechanism for reducing dynamic power consumption. In applications with a high idle ratio, the benefits become even more pronounced. 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