Bridging Simulation and Silicon: A Study of RISC-V Hardware and FireSim Simulation
Barai, Atanu; Kamalakkannan, Kamalavasan; Diehl, Patrick; Moraru, Maxim; Dominguez-Trujillo, Jered; Pritchard, Howard; Santhi, Nandakishore; Fatollahi-Fard, Farzad; Shipman, Galen
- Publisher
- Zenodo
- Language
- en
Abstract
RISC-V ISA-based processors have recently emerged as both powerful and energy-efficient computing platforms. The release of the MILK-V Pioneer marked a significant milestone as the first desktop-grade RISC-V system. With increasing engagement from both academia and industry, such platforms exhibit strong potential for adoption in high-performance computing (HPC) environments. The open-source, FPGA-accelerated FireSim framework has emerged as a flexible and scalable tool for architectural exploration, enabling simulation of various system configurations using RISC-V cores. Despite its capabilities, there remains a lack of systematic evaluation regarding the feasibility and performance prediction accuracy of FireSim when compared to physical hardware. In this study, we address this gap by modeling a commercially available single-board computer and a desktop-grade RISC-V CPU within FireSim. To ensure fidelity between simulation and real hardware, we first measure the performance of a series of benchmarks to compare runtime behavior under single-core and four-core configurations. Based on the closest matching simulation parameters, we subsequently evaluate performance using a representative mini-application and the LAMMPS molecular dynamics code. Our findings indicate that while FireSim provides valuable insights into architectural performance trends, discrepancies remain between simulated and measured runtimes. These deviations stem from both inherent limitations of the simulation environment and the restricted availability of detailed performance specifications from CPU manufacturers, which hinder precise configuration matching. Preprint: https://arxiv.org/abs/2509.18472
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UNCLASSIFIED Bridging Simulation and Silicon: A Study of RISC-V Hardware and FireSim Simulation Atanu Barai, Kamalavasan Kamalakkannan, Patrick Diehl, Maxim Moraru, Jered Dominguez-Trujillo, Howard Pritchard, Nandakishore Santhi, Farzad Fatollahi-Fard, and Galen Shipman LA-UR-25-30862 (https://doi.org/10.5281/zenodo.17603153) Managed by Triad National Security, LLC,for the U.S. Department of Energy’s NNSA.UNCLASSIFIED November 13, 2025
UNCLASSIFIED Motivation Need for representative open source hardware design and evaluation technologies for co-design. Adoption in HPC environments •RISC-V ISA-based processors have recently emerged as both powerful and energy-efficient computing platforms. •Increasing engagement from both academia and industry, such platforms exhibit strong potential in high-performance computing (HPC) environments Challenges •No HPC-grade RISC-V available for experimentation •Little details available on hardware design / features for available RISC-V processors UNCLASSIFIED November 13, 2025 | 2
UNCLASSIFIED In this study we assess the gap between simulated architecture and real hardware The following questions are addressed: 1. Can we evaluate the capability of FireSim to closely model and to predict the performance on single core and multi-core systems. * 2. Can we evaluate the performance of HPC representative workloads on simulated and actual systems and analyze the correlations in performance. * Obligated AI-Generated Image UNCLASSIFIED November 13, 2025 | 3
UNCLASSIFIED Outline Applications Configuration Results Conclusion and Outlook UNCLASSIFIED November 13, 2025 | 4
UNCLASSIFIED Applications •The MicroBench suite, provides 40 lightweight microbenchmarks specifically targeted at evaluating microarchitectural features of processor cores and memory subsystems. •The NAS Parallel Benchmarks (NPB) are a set of standardized tests designed to evaluate the performance of massively parallel supercomputers. •Unstructured Mesh Explorations (UME) proxy application, developed at Los Alamos National Laboratory (LANL), models salient features of a much larger code. •The Large-scale Atomic/Molecular Massively Parallel Simulator (LAMMPS) is a parallel molecular dynamics simulation package specifically engineered to run efficiently on high-performance computing platforms. UNCLASSIFIED November 13, 2025 | 5
UNCLASSIFIED FireSim and hardware configuration UNCLASSIFIED November 13, 2025 | 6
UNCLASSIFIED Microbenchmark performance on FireSim and Banana PI •Difference in DDR4 vs DDR 3 and unknown parameters let to 35-37% of the performance of the baseline hardware in benchmarks stress the DDR bandwidth. UNCLASSIFIED November 13, 2025 | 7
UNCLASSIFIED Microbenchmark performance on FireSim and MILK-V •Difference in memory model and unknown parameters let to 8%-43% of the performance of the baseline hardware in benchmarks stress the DDR bandwidth. UNCLASSIFIED November 13, 2025 | 8
UNCLASSIFIED LAMMPS performance on FireSim compared with Banana PI and MILK-V 124 # of MPI processes 0 1 Relative speedup to real hardware FireSim simulation vs real hardware Hardware Milk-V Sim Model Banana Pi Sim Model LAMMPS Lennard-Jones (JL) benchmark 124 # of MPI processes 0 1 Relative speedup to real hardware FireSim simulation vs real hardware Hardware Milk-V Sim Model Banana Pi Sim Model LAMMPS Polymer Chain benchmark •Similar to UME, we also observe speedup with the number of MPI processes. •Once again, there is a large performance gap between MILK-V hardware and FireSim simulation although good MPI performance scaling can be observed in all hardware configurations. UNCLASSIFIED November 13, 2025 | 9
