Post-Placement Timing Optimisations on Asynchronous Designs

Post-Placement Timing Optimisations on Asynchronous Designs Dimitrios Tsalapatas , Nikolaos Chatzivangelis , Christos P. Sotiriou , and Nikolaos Sketopoulos Department of Electrical and Computer Engineering University of Thessaly Volos, Greece {dtsalapatas, chnikolaos, chsotiriou, sketopou}@e-ce.uth.gr Abstract— In this paper, we present the Asynchronous In-Place Optimisation (AIPO) algorithm, designed to enhance post-placementand-routing (post-P&R) timing for asynchronous control and Bundled-Data circuits. AIPO operates in a closed-loop system with ASTA (Asynchronous Static Timing Analysis), focusing on achieving timing closure for the circuit. The algorithm performs gate resizing and buffer insertion by making tentative optimisation moves and evaluating their impact using ASTA. It leverages advanced timing models, such as CCS, and wellestablished wire RC representation formats, such as Pi-models. Additionally, AIPO works in tandem with a placement legaliser to resolve cell overlaps introduced by its optimisation actions. We present post-P&R results for the AIPO algorithm across 17 benchmark designs and three technology libraries: IHP 250nm, IHP 130nm, and GF 22nm. The results demonstrate that AIPO effectively improves circuit timing by mitigating the adverse effects of cell placement and wire RC interconnect delays. Timing improvements of 33% and 30% were observed for the IHP and GF libraries, respectively. The observed area overhead correlates with the achieved delay reductions, highlighting AIPO’s ability to navigate the Area-Delay Pareto trade-off effectively. Index Terms—Optimisation, Asynchronous, Timing, EDA I. INTRODUCTION Asynchronous circuits have now been around for a long while [1]. A solid body of research exists today both for asynchronous control circuit synthesis and datapath implementation, using Bundled-Data (BD) or QDI, timing models. Applications that benefit from the use of asynchronous design include NOCs [2] and switches [3], resilient circuits [4], digital controllers for analog circuits [5], Near Threshold Computing [6], arithmetic circuits [7], [8], CPUs [9]–[11], Neural Networks [12], [13] and Machine Learning [14]. Asynchronous synthesis using Petrify [15] and Workcraft [16] is capable of both synthesis and formal verification of control circuit specifications. In particular, the Workcraft framework is now sufficiently mature, providing numerous design examples and tutorials, visualisation and modelling capabilities and multiple synthesis back-end options [17]–[19], rendering asynchronous circuit design a viable option. Post-synthesis, asynchronous circuits may possess timing assumptions, including isochronic forks, zero delay inverters, Relative Timing (RT) paths. The longest, or critical, cycle(s) typically determines performance. However, physical design for asynchronous circuits is less mature to synthesis. During physical design, cells placement often introduces long wires that increase delays in unexpected places. In clocked circuits, this is resolved through incremental synthesis [20], [21] and the In-Place Optimisation (IPO) phase. The latter includes closed-loop gate resizing and buffer insertion, based on incremental STA [21]. However, STA, the cornerstone of physical design timing optimisation cannot handle cycles. STA cuts loop arbitrarily, producing inaccurate slew, delay, and power results. Flows such as [22], [23] create virtual clocks to indirectly enforce BD and RT constraints. FFbased templates without internal cycles are easier to handle in STA, however, microarchitectural cycles are still an issue which affects post-P&R performance. Asynchronous control circuits are thus hard to timing optimise during physical design. Typically, “don’t touch” or “size-only” constraints are used, to ensure no changes during physical optimisation, which may impact their timing assumptions. In conclusion, asynchronous control sections may suffer from suboptimal gate sizing and buffer insertion, post-P&R. In this paper, we present a post-placement ASTA-based, closed-loop, gate resizing and buffer insertion Asynchronous IPO (AIPO) algorithm. The latter iteratively optimises the ASTA computed critical cycle(s), during physical design, working in tandem with a placement legaliser [24]. AIPO may be implemented as a side flow to back-end methodologies. The optimised circuit is fed back to the back-end tool, and timing optimisations may be validated using STA tools such as Synopsys PrimeTime or Cadence Tempus, albeit with cycles cut. ASTA generated cycles are used to steer the STA process. Our contributions include the following: •we demonstrate significant asynchronous control critical cycle performance gains, using our AIPO algorithm, •we demonstrate an industry-proven STA engine compatible flow (Section IV) to time asynchronous circuit cycles, utilising Synopsys PrimeTime flow, at the highest level of timing accuracy, with full parasitics extracted (SPEF in), and evaluate the AIPO results, •we validate that critical cycle(s) ranking order, pre and post-AIPO, is identical between custom ASTA tool and industry-proven STA engines, •we illustrate that the AIPO algorithm produces a welldistributed (Area, Delay) Pareto during optimisation. II. BACKGROUND A. Asynchronous STA STA engines for asynchronous circuits (ASTA) [25]–[27] are now available. ASTA [25] is Graph-Based Analysis (GBA) performed on the circuit graph and its environment, if defined. The ASTA circuit graph, also known as RETG (Reduced Event Timing Graph), i.e. a Marked Graph (MG) or simplified PTnet, or an RER (Repetitive Event Rule System), is constructed by composing individual circuit component PTnets [26], the edges of which correspond to the technology library (Liberty, .lib) specification timing arcs between component pins. The RETG may be marked by the user, if needed. However, in the fully-automated ASTA flow it is automatically marked as live and 1-bounded [26], so that the critical cycle, composed of maximum timing arc delays, directly corresponds to the worst-case events occurrence. ASTA overcomes the STA cycle breaking issues. It takes into account combinational loops in the timing calculation, propagates slews iteratively through circuits with loops, therefore avoiding slew optimism resulting to delay optimism [28]. In the case of multiple cycles in the circuit, ASTA identifies the longest cycle, but without explicitly enumerating all unique cycles, which is exponential in complexity. ASTA may be used both pre and post-P&R, allowing for the modelling of interconnect parasitics both post placement and post routing. Post placement, where physical routes are not yet available, yet cell and pin physical locations are known, interconnect delay may be modelled using the wellestablished Elmore delay or full waveform propagation [29]. The latter is less pessimistic, and well correlated to stateof-the-art back-end tools post placement interconnect delay estimations, involving also more accurate interconnect representation compared to Lumped model such as Pi-model or RC-trees. Post routing, parasitic extraction may take place to generate all R, C parasitics per net in a SPEF file. This is the most accurate ASTA (or STA) analysis. where the most sophisticated timing models may be used, e.g. CCS waveform propagation with full parasitics, in both ASTA and state-ofthe-art tools. B. Bundled-Data Circuits ASTA engine [25] also supports Bundled-Data (BD) Circuits. A BD circuit is divided into control and BD datapath Verilog modules, with the datapath and control sections user-specified. ASTA traces asynchronous control to datapath connections, and creates asynchronously generated, worst-case local clocks. The local clocks timings depend on the derived, worst-case critical cycle, and combine worst-case active clock edge timing, with best-case timing for the opposite, nonactive edge. Pulse widths are also checked for the control to datapath asynchronously generated clocks, by the ASTA engine to check clock pulse width timing violations at the circuits BD elements, be FFs or Latches. Based on the ASTA asynchronously generated clock waveforms, the generated datapath clocks are then used to perform STA for the BD datapath section, and validate the BD timing constraints for both setup and hold. C. IPO and AIPO In-Place Optimisation (IPO) is the process of performing post-P&R, local physical circuit changes to improve circuit timing. IPO is always performed in closed-loop with STA, iteratively making local circuit changes while timing is improving for the circuit portion in focus. In clocked circuits, IPO typically focuses on the top critical path, or a set of critical paths, performing incremental synthesis, which includes resizing optimisations and buffer insertion [30]. In addition to these techniques, further optimisation strategies in IPO [31] include netlist restructuring, which involves gate composition and decomposition to preserve the logical functionality of the design while utilising alternative gate configurations to enhance performance. Fan-out decomposition helps manage high fanout nets by splitting them into smaller loads, reducing delay and improving signal integrity. Pin re-assignment improves timing by reassigning signals, balancing loads across critical paths without increasing the design’s area. Cell movement reduces wirelength, leading to better timing characteristics and potentially lower power consumption [32]. In this paper we focus on the highest impact IPO operations, i.e. gate resizing and buffer insertion. Both gate resizing and buffer insertion, at a gate output across its fanouts, are hazardnon-increasing transformations [33], [34]. This is key to ensure that IPO does not create new hazards or timing models issues. Similar to clocked IPO, Asynchronous IPO (AIPO) may be performed iteratively, on the ASTA computed critical cycle or a set of critical cycles, performing tentative gate resizing or buffer insertion on the critical cycle gates, wires, and classifying the tentative move as good or bad, based on the local timing delta. Resizing replaces a cell with a higher drive strength equivalent, to reduce propagation delay on critical paths by increasing the W/L ratio of the device, thereby reducing the on-resistance of the cell transistors [35]. Buffer insertion addresses timing issues by dividing long interconnects into shorter segments, reducing RC slews and delays [36]. Both of these operations trade-off performance improvement with area and power increments, and such factors must also be taken into account, e.g. placing a buffer or resizing a cell may not be physically possible, due to placement congestion. D. Timing Model Constraints When it comes to timing constraints related to the circuit timing model, such as isochronic forks, zero delay inverters and RT paths, these are typically considered as higher priority violations. These must typically, be fixed, post an AIPO step, when closing all circuit Design Rule Violations. Fixing those, additional timing or physical area penalties may incur, thus extra floorplan area may be needed. III. ASYNCHRONOUS IN-PLACE OPTIMISATION ALGORITHM In this section, we present a greedy AIPO (Asynchronous In-Place Optimisation) flow that aims to reduce the delay on the critical cycle of the design. The AIPO algorithm pseudocode is illustrated in Algorithm 1. AIPO operates iteratively, performing tentative moves, which are accepted or rejected, based on the local stage delay outcome, i.e. local delay reduction or increase. Moves include: (i) gate resizing and (ii) buffer insertion. The latter is used if and only if (i) is not available. AIPO focuses on reducing the critical cycle delay below a user-specified critical cycle delay/period constraint, the Target Period (TP). As the top critical cycle delay improves, another cycle may become timing dominant and take its place. If the new cycle still violates the TP constraint, the algorithm will now focus on the latter. Both delays and slews are updated locally for every tentative and accepted move, to ensure ASTA results are consistent and accurate. Algorithm 1: Critical Cycle(s) Optimisation Input: Initial Netlist (.v), .lib, .lef, .def, .captables, Target Period (TP), Max Utilisation (Umax), Don’t Touch cells, Max Iterations (Imax) Output: Optimised Netlist (.v) and .def 1i←0; 2while i<Imax do 3Ccrit, DC old ←get critical cycle(); 4sort gates by criticality(Ccrit); 5G←get most crit available gate(Ccrit); 6while G=NONE do 7DG old ←G.delay; 8upsize result ←eco upsize gate(G); 9if upsize result =SUCCESS then 10 eco insert buffer(G); 11 incremental legalisation(); 12 DG new ←get local timing cost(G); 13 if DG new > DG old then 14 revert move(); 15 mark gate as blocked(G); 16 else 17 unblock predecessor gates(G); 18 sort gates by criticality(Ccrit); 19 G←get most crit available gate(Ccrit); 20 incremental ASTA(); 21 DC new ←Ccrit.delay; 22 i←i+ 1; 23 if DC new == DC old then 24 break; 25 else if DC new < TP then 26 revert move(); 27 break; 28 else if Design.Utilisation > Umax then 29 revert move(); 30 break; A. Critical Cells Delay Metric To improve the critical cycle timing, critical cycle cells must be prioritised, in terms of their timing improvement potential. A good metric for this, which we refer to as cell criticality, is their ratio of total output capacitance, including wire RC delays, to their input capacitance, Cout/Cin [37]. What is key to this metric is that it correlates to the cells total fanout load, including both fanout cells input capacitances and wire RC loads, as well as to the specific driver cell size. When the Cout/Cin ratio is large, it reflects an imbalance between cell fanout load and own drive strength, thus identifying an optimisation candidate. In more detail, fanout input capacitances and Cin are determined by technology library Liberty (.lib) file data. Wire RC delays are estimated, post-placement, using the Elmore or Pi-model stage full waveform propagation [29], or postrouting, post parasitic extractions using SPEF data. In postplacement, the Pi-model stage full waveform propagation is less pessimistic than Elmore delay with small overhead in complexity. The SPEF data, which includes all layout R, C parasitics per net, including coupling, is produced by an extractor. Post-routing SPEF STA/ASTA analysis, has highest accuracy and highest computational cost, so AIPO is typically used with post-routing estimation model, i.e. the Pi-model RC representation, to reduce the execution time. B. Optimisation Loop The AIPO process takes as inputs the circuit netlist (.v), the standard cell technology library (.lib) files, layout files (.lef and .def), capacitance tables (.captables), the user constraint Target Period (TP ), a maximum allowable utilisation (Umax), to ensure the design is routable post changes, a list of don’t touch cells, e.g. for delay elements, and optionally a maximum given number of AIPO iterations to limit runtime. The AIPO outputs include the optimised netlist (.v) and the updated layout (.def). Both reflect all cell size changes, cell location changes, and include any inserted buffers. In this way, the AIPO input may come from any back-end tool, and its output may be fed back to it. AIPO optimisation begins by identifying the circuit critical cycle, which represents the most timing sensitive sequence of cells in the asynchronous control circuit (line 3). The critical cycle (Ccrit) and its delay (DC old) are determined by ASTA engine [38]. Critical cycle cells are then sorted by their Cout/Cin criticality metric (line 4), and the most critical available cell (G) is selected for optimisation (line 5). Cell Gis tentatively upsized by selecting the next available equivalent Boolean function gate with higher drive strength, achieved by choosing a cell with larger max_capacitance, from the library. This attempts to reduce the local cell stage delay in the critical cycle (lines 6-19). If a larger gate is not available, the algorithm attempts to insert a buffer instead. This redistributes and balances the fanout load between the Gand the inserted buffer, and thus again improves local cell stage delay (lines 9-10). During these two tentative moves, incremental legalisation [24] is performed to ensure that the larger gate, or the inserted buffer, may be accommodated in valid physical locations within the layout floorplan (line 11). The resultant modified cell stage delay, DG new, is next evaluated to classify the tentative move as good or bad (line 12). If the new delay is greater than the previous delay (line 13), the tentative move is rejected, and any changes to the circuit, including cell layout relocations or buffer placements by the legaliser are reverted (line 14). In addition, the cell failing optimisation is marked as “blocked”, to prevent further redundant optimisation attempts on it (line 15). On the other hand, if the new cell stage delay, DG new, is less than the previous one, the tentative move is accepted. The algorithm then continues by updating the Cout/Cin metric for all cells, the Cout or Cin values of which has changed due to the last cell optimisation moves (line 18). In addition, the “blocked” flag for such cells is reset (line 17), to be able to reconsider them, should they become critical again. The AIPO algorithm then reiterates, selecting again the new most critical ratio cell for optimisation (line 19). This process repeats until no further available cells exist in the current critical cycle (line 6). To reduce the AIPO execution time, it is beneficial for the modified cell stage delay, DG new, to be computed quickly. This is the reason why only local, stage timing analysis is performed. Local delay analysis performs delay computation in the new cell local vicinity, considering delay changes one level back and one level forward from the cell in question. The local stage delay delta directly impacts the critical cycle. In the case where, the upsizing or buffer insertion increases Cin for its previous stage, and the move is accepted, so local delay is improved, the new increased Cin value will be reflected in the previous stage Cout/Cin ratio, and will modify its criticality metric for a next AIPO iteration. After completing all possible cell stage optimisations for the current critical cycle, an incremental ASTA step is performed (line 20), to update the critical cycle(s) timing for the entire design. This will obtain a new critical cycle and its delay (DC new). At this point, the algorithm will check overall progress and exit if necessary. The following criteria are used as optimisation loop exit conditions between iterations: (i) critical cycle delay remains unchanged (DC new == DC old) (lines 23-24), (ii) critical cycle delay falls below the specified target (DC new < TP ) (lines 25-27), (iii) the design’s layout area utilisation exceeds the maximum allowable limit (Umax) (lines 28-30), i.e. sufficient changes have been made that the design is too dense to be routable, so floorplan changes are needed if optimisation is to be performed, and (iv) a maximum number of iterations (Imax) is reached (line 2). If any of these conditions are met, the optimisation process terminates. It is important to note that for exit conditions (i) and (ii), the last moves that led to a violation of these limits are reverted. In case of (i), this is because the last moves had no impact on the timing of the critical cycle, causing only unnecessary area overhead. For (ii), the last moves are reverted, as they violated the user-defined target period constraint, which could disrupt the relative timing constraints of cyclic paths in the design. Finally, by leveraging condition (iii), the user can impose a predefined limit on the design area, ensuring that the algorithm does not exceed a specified utilisation threshold, thereby controlling the trade-off between performance and area overhead. IV. AIPO EVALUATION FLOW This section describes a complete, back-end EDA evaluation flow, using state-of-the-art tools, such as Cadence Innovus and Synopsys PrimeTime, to use and evaluate the proposed AIPO methodology. By providing baseline STA data, using established back-end flows and STA tools, we address the well-founded scepticism for the use of custom EDA tools such as ASTA or AIPO. The goal of the flow is to thus measure critical cycle delay improvements from AIPO using industryproven STA tools. For these purposes we chose the Synopsys PrimeTime. A. Standard STA Results Evaluation Flow The AIPO flow is illustrated in Fig. 1. The red (dashed) arrows correspond to the pre AIPO STA-based, industry-proven circuit critical cycle delay measurement flow, whereas the black arrows correspond to the post AIPO respective measurements. The pre AIPO flow essentially performs placement and routing of the design within Cadence Innovus. It is checked that the design is DRC clean and parasitics are extracted at the highest level of detail. Using the ASTA generated cycles, uses Synopsys PrimeTime to measure critical cycle delays, in Signoff quality, i.e. with SPEF in. Instead of allowing PrimeTime to arbitrarily cut cycles, the ASTA cycles are handled as paths, by breaking them, one point at a time, and overriding the slew at the cut point. This is detailed in Section IV-B. The AIPO flow begins with the current placement and routing layout data, in def form. The design is loaded in the AIPO side flow (blue box). ASTA is performed on the layout data and AIPO optimisation takes place. When AIPO completes, optimised netlist and the updated critical cycle information are exported. Placement changes are not required as the AIPO legaliser ensures placement is legal to begin with. The design is rerouted in Cadence Innovus and it is checked that the layout is DRC clean. A new, post AIPO SPEF is now extracted, to feed into PrimeTime and compare the pre and post AIPO results, using the process of Section IV-B. Thus, the pre and post-AIPO timing data do not rely on ASTA delay measurements, but on industry-proven STA. B. Iterative Slew Override Cycle Delay Calculation Flow As mentioned in Section IV-A, industry-proven STA tools were not developed to handle circuits with cycles, as they use an internal DAG representation. Consequently, they break cycle timing arcs to break cycles into paths. However, as cycles are cut, their delay and slew values are optimistic. To address this, we use a custom Slew Override flow using Synopsys PrimeTime iteratively. Delay calculation is performed per run, and slews are set at the cut point input timing arc. Next, this slew result is applied to the cut timing arc, and the cut point is also moved forward, within the critical cycle. This sets up the Fig. 1: AIPO Flow including STA Baseline Data Generation next run. Slews are thus propagated across the critical cycle, and eventually settle, across script runs. The resultant delays thus take into account slew values propagated across the cycle, and both slew and delay optimism is significantly reduced. The steps of our Slew Override STA Flow is detailed below. A total of three to four iterations are required across the cycle for slews to settle. 1) A design with Ncells on critical cycle is loaded into Synopsys PrimeTime, which breaks the cycle by cutting (disabling) an arbitrary timing arc. 2) Delay calculation for each arc of the cycle is performed. 3) Once the cut arc is reached, the previous arc is disabled to enable the current one and continue the delay calculation to the following stages. 4) Upon completing delay calculations on all cycle arcs, delay is reevaluated but the initial 0.0 slew is replaced by the last computed predecessor arc transition, to propagate the slews throughout the cycle and obtain more accurate delays. 5) This process is repeated until the output slews stabilise (values do not change), typically requiring three to four iterations. An illustration of the iterative slew override flow is shown in Fig. 2, showing snapshots 2(a)-2(f) of the process. A mock cyclic design is used, comprised only by an inverter (INV) and a nand (NAND) gate. The cut timing arc is marked with an “x”, the current delay, slew calculation is highlighted with a red slew symbol and highlighted in the snapshot table. Cycle delay computation includes the following timing arcs: INV/A to INV/Z (rise), INV/Z to NAND/B (rise), NAND/B to NAND/Z (fall), and NAND/Z to INV/A (fall). Initially, PrimeTime detects and breaks the cycle by disabling timing arc INV/A to INV/Z (Fig. 2a). The initial delay of NAND/B to NAND/Z arc is computed using the output capacitance the NAND gate drives, and an ideal input slew of 0.0 ps, due to the currently cut arc. Next, the interconnect wire delay between NAND and INV is calculated based on the computed slew at NAND/Z (Fig. 2b). When disabled arc, INV/A to INV/Z, is reached, previous arc, NAND/B to NAND/Z is disabled, and the former is now enabled. Delay and slew is updated from INV/A to INV/Z (Fig. 2c). Next, arc INV/Z to NAND/B is computed, based on the previously derived slew (Fig. 2d). The process continues, i.e. arc NAND/B to NAND/Z delay is recomputed, using the updated slew from INV/Z (Fig. 2e). The procedure converges when no further changes occur in slews (Fig. 2f). This iterative approach ensures a realistic and precise assessment of the cycle delay. C. Critical Cycles ASTA, STA Correlation During this process of iterative slew override within PrimeTime, we compared the critical cycles ranking order between ASTA and PrimeTime, to see if the relative delays between critical cycles change. It is possible that the ranking order of critical cycles may differ when they are treated as paths in Synopsys PrimeTime. For instance, the ASTA top critical cycle may not be the longest PrimeTime delay path. We evaluated all cycles and can confirm that for all designs in the experimental section, the ASTA reported critical cycle ranking order was identical to that of the PrimeTime slew override flow. There were delay and slew differences, but not enough to change the relative order of critical cycles. This is a very interesting key result demonstrating the potential of the AIPO approach in practical EDA post-P&R flows. V. EXPERIMENTAL RESULTS To evaluate the QoR of our AIPO methodology, a total of 17 benchmark designs were used. More specifically, 13 of the 17 benchmarks are from the asynchronous community, representing a range of asynchronous control circuits used in various projects and applications, with varying levels of complexity while designs multiplier_pipe, alu_pipe, cla_adder, and divider_pipe are Bundled-Data (BD). Thus, they include both asynchronous control and BD datapath sections, including delay elements. Delay elements are “don’t touched” during the AIPO flow, as the flow focuses only on improving the performance of the control circuit. Designs have been synthesised using Petrify tool [15]. A total of 3 technology nodes, have been tested, i.e. IHP 130nm, IHP 250nm, and GlobalFoundries (GF) 22nm FinFET. Remapping between technologies has been performed using Synopsys Design Compiler, and gates have been checked to be 1-1 across libraries to avoid timing issues caused by logic decomposition of complex CMOS gates. The benchmarks design characteristics are presented in Table I. The AIPO algorithm implementation is in C, C++. The interface between the ASTA, AIPO and industry-standard EDA tools is implemented through TCL scripts and standard EDA file formats, including lef, lib, def, Verilog and SPEF, as shown in Fig. 1. The machine used for experiments is a 10-core, 20-thread CPU Linux workstation machine at 3.0 GHz with 128GB of RAM. (a) Report Delay from NAND/B to NAND/Z (b) Report Delay from NAND/Z to INV/A (c) Report Delay from INV/A to INV/Z (d) Report Delay from INV/Z to NAND/B (e) Report Delay from NAND/B to NAND/Z (f) Final Calculation with Converged Slews Fig. 2: Critical Cycle Slew Override Flow example in Synopsys PrimeTime. TABLE I: Benchmarks Characteristics Max Cout Cin Benchmark #Pins #Nets #Cycles #Cells in Crit. Cycle IHP GF 22 ring_oscillator 7 5 1 3 3.1 1.1 ebergen 30 11 4 2 2.0 2.8 half 36 13 9 7 3.4 3.0 c3dec2 36 14 6 8 1.2 4.1 nowick 38 17 2 2 3.9 4.1 chu133 46 22 6 8 2.2 2.0 converta 59 21 10 5 5.7 5.3 latchcontroller 72 22 8 8 9.6 3.2 trimos 95 36 30 24 7.6 6.7 click_2stage 97 24 8 10 6.7 7.0 three_controllers 156 38 7 21 5.0 5.6 Master_Read_0 194 70 47 32 5.2 5.9 pausibleck 244 62 6 9 22.4 15.9 alu_pipe* 380 104 3 18 14.1 23.0 cla_adder* 1599 569 3 15 57.3 93.5 multiplier_pipe* 6007 1972 15 16 43.2 70.5 divider_pipe* 11516 3914 19 24 44.9 73.4 *Synthesised with IHP 130nm PDK A. Experimental Setup This section outlines AIPO algorithm setup used to generate the results presented in the following sub-section. Physical design was performed on the benchmarks using Cadence Innovus, including placement, routing, and SPEF extraction. During the placement and routing phase, the timing-driven option was disabled to prevent the tool from considering timing information from cut combinational cycles, which could lead to erroneous results. AIPO was performed in post-placement and pre-routing design state, using the Pi-model representation to model wire RC interconnects. Floorplan utilisation was set to 70% for IHP and 50% for GF 22nm respectively. The latter was used to provide for more floorplan area to be utilised and thus potential for improvement. It should be noted that some benchmarks contain a relatively moderate number of standard cells, meaning that area increases from upsizing or buffer insertion could significantly impact utilisation. The utilisation upper bound, Umax, was capped at 90% across all PDKs to ensure a resultant legal, no cell overlaps and routable placement. As an example, the smallest benchmark, ring_oscillator, exited the optimisation loop after only a few moves, by reaching the utilisation limit. Across all designs, the Target Period (TP) is set to 0.0, to test the algorithm optimisation potential by pushing delay to be as small as possible. The maximum number of iterations was left unconstrained for the same reason. It is worth noting that the maximum number of AIPO iterations reached 360 across all cycles, for the largest design examined, i.e. divider_pipe. As for the performance of the AIPO algorithm optimisation step is fast, at least for the 17 tested benchmarks. In more detail, the total runtime of the slowest benchmark, i.e., divider_pipe, is less than 80 seconds, while the average runtime for all designs is about 20 seconds. B. Experiments Analysis In this section the delay and area results of the proposed AIPO methodology, based on the AIPO evaluation flow, are analysed. As explained in the previous section, Section IV, pre and post-AIPO timing results are obtained using PrimeTime STA, using the iterative slew override flow on all ASTA reported cycles. Table II presents the results, highlighting the impact on each circuit’s timing and area after post-P&R, as determined by the critical (i.e., longest delay) cycle for the three technology libraries: IHP 250nm, 130nm, and GF 22nm. Results demonstrate that AIPO consistently managed to improve performance for all 17 benchmarks, at varying levels of incurred area overhead. Specifically, for the IHP PDKs, the average cyclic circuit period improvement achieved by AIPO is 32.63%, with an average footprint area increase of 5.54%. For the GF 22nm FinFET process, the corresponding average period improvement is 29.7%, with an average area overhead of 39.55%. While the GF 22nm technology appears to have a significantly higher percentage area overhead, it is essential to take note that percentage area overhead is a relative metric. In absolute terms, area increases are often negligible, particularly for smaller designs. For example, for benchmarks chu133 and ring_oscillator the area overhead is reported as 90.71% and 85.62%, but the absolute increase is only 2.59um2 and 0.85um2respectively. Across both PDKs, design netlists with higher Cout/Cin cell metric ratios, as presented on Table I, usually exhibit greater performance improvements. For instance, in the IHP TABLE II: AIPO Results for IHP 130nm / 250nm and GlobalFoundries GF22nm Libraries IHP 250nm / 130nm* Global Foundries 22nm Benchmark Period (ns) Area (um2) Period Impr. (%) Area Overhead (%) Period (ns) Area (um2) Period Impr. (%) Area Overhead (%) ring_oscilator 0.38 56.44 29.93% 12.50% 0.09 0.46 16.85% 85.62% ebergen 0.32 190.51 45.08% 7.41% 0.07 2.33 7.21% 65.71% half 1.32 211.68 17.90% 13.33% 0.34 1.93 28.73% 31.04% c3dec2 0.75 218.73 0.00% 0.00% 0.18 2.06 12.76% 64.57% nowick 0.31 268.12 50.32% 2.63% 0.06 2.39 32.31% 72.25% chu133 0.66 310.46 9.74% 4.55% 0.18 2.86 24.68% 90.71% converta 1.60 409.24 30.06% 3.45% 0.41 3.59 32.17% 74.10% latchcontroller 1.42 395.13 33.97% 3.57% 0.49 3.39 21.85% 41.15% trimos 4.13 649.15 37.04% 14.13% 0.74 5.92 19.70% 52.80% click_2stage 2.20 1079.56 46.96% 7.84% 0.49 12.31 21.85% 10.81% three_controllers 5.59 1622.88 38.29% 10.87% 0.91 17.83 21.43% 19.40% Master_Read_0 7.24 1333.58 39.21% 10.05% 1.43 12.04 13.13% 38.12% pausibleck 4.46 4148.92 58.91% 1.53% 0.81 39.80 58.22% 12.88% alu_pipe* 4.52 1219.27 26.60% 1.69% 0.94 53.78 27.55% 6.93% cla_adder* 9.23 6469.47 45.78% 0.17% 1.95 289.74 59.01% 2.14% multiplier_pipe* 14.04 25490.51 29.65% 0.16% 1.71 1153.08 51.83% 2.57% divider_pipe* 32.32 42857.26 15.24% 0.23% 2.13 1651.15 55.57% 1.52% Average - - 32.63% 5.54% - - 29.70% 39.55% *Synthesised with IHP 130nm PDK library, latchcontroller achieves a 33.97% period improvement, with a modest area overhead of 3.57%, while pausibleck demonstrates an impressive 58.91% improvement, at only a 1.53% area overhead. This argument is further enhanced by c3dec2, where no improvement in performance or area is observed due to its initially balanced Cout/Cin ratio (Cout/Cin ≈1) across all cells. This issue prevented AIPO from performing upsizing or buffer insertion, leaving its period and area unchanged. An exception to this is observed in the ring_oscillator design, which also exhibits a Cout/Cin ≈1. However, the library includes an inverter gate with a drive strength of 1.5 between x1 and x2, which this design utilises to reduce delay, thereby taking advantage of the configuration as two out of its three cells are of type INV. For the GF 22nm library, designs like cla_adder, with 59.01% improvement at 2.14% area overhead, and multiplier_pipe, with 51.83% improvement at 2.57% area overhead, further showcase the AIPO capability to optimise bundled-data designs with minimal standard-cell percentage area and layout floorplan impact. The flexibility and effectiveness of the AIPO algorithm depend heavily on (i) synthesised netlist original sizes and presence of buffers, (ii) the physical timing to post-synthesis timing gap, and (iii) PDK characteristics, in particular, the availability of multiple gate sizes for upsizing and various buffer sizes for buffer insertion. For instance, the benchmark ebergen demonstrates a period improvement of 45.08% in the IHP 250nm, but only 7.21% in GF 22nm. This significant difference occurs due to the Umax, maximum utilisation constraint, which limits the number of AIPO moves, thereby limiting the overall achievable performance improvement. Overall, the experimental results validate the effectiveness of AIPO across all technologies. While IHP demonstrates consistent improvements, at minimal area impact, GF 22nm exhibits greater sensitivity to the initial netlist Cout/Cin ratios, at acceptable absolute area increases. These findings emphasise AIPO’s adaptability to varying library characteristics and its potential to optimise both small and BD asynchronous circuits effectively. C. Delay-Area Pareto Curves In this section, we illustrate the Area-Delay Pareto curves exposed by the AIPO flow. Fig. 3 illustrates the Area-Delay Pareto curves for two designs synthesised using different PDKs. These Pareto curves represent the area, delay trade-off performed during the AIPO flow iterations, with critical cycle delay reducing at the cost of standard cell area increasing. As delay is reduced more and more, it reaches a minimum value, and it’s at this point that standard-cell area peaks. This is a well known trait of logic synthesis and clocked IPO. What may also be observed from Fig. 3 is that at some points in the curve, area does not change much, while at other places it rapidly shoots upwards. This behaviour is influenced by the AIPO selected optimisation moves (Cout/Cin) and the delay and area characteristics of the PDK cells. As explained in the previous section V-B, it is the availability of multiple gate sizes for upsizing and various buffer sizes for buffer insertion that cause local jumps on the area, delay curve. To conclude, similar to clocked circuits, we see that asynchronous and BD circuits are capable to enjoy a post-P&R area, delay trade-off during timing optimisation. VI. CONCLUSIONS AND FUTURE WORK We presented an Asynchronous In-Place Optimisation (AIPO) algorithm, optimising circuit timing in post-P&R design state. AIPO works in closed-loop with ASTA, optimising the circuit critical cycle, to close the timing within a user-specified delay constraint. Two optimisation steps are performed by AIPO, gate upsizing and buffer insertion. AIPO works by performing tentative moves, evaluating their impact 4.40 7.24 1,333.58 Area (um^2) 1,460.59 Critical Cycle Delay (ns) (a) Master_Read_0 at IHP 250nm 1.24 1.43 Critical Cycle Delay (ns) 12.05 Area (um^2) 16.11 (b) Master_Read_0 at GF 22nm 3.32 4.52 Critical Cycle Delay (ns) 1,219.28 Area (um^2) 1,260.55 (c) alu_pipe at IHP 130nm 0.68 0.94 Critical Cycle Delay (ns) 53.78 Area (um^2) 57.51 (d) alu_pipe at GF 22nm Fig. 3: Master_Read_0 and alu_pipe Pareto Curves using ASTA, to account for non-linear cell and wire RC delay timing. AIPO and ASTA support the NLDM and CCS timing libraries for cell delays, and the Elmore and Pi-Model stage full waveform propagation for approximating wire RC delays, post-placement, when metal routes are not present. SPEF in is supported post-routing. As the AIPO gate upsizing and buffer insertion steps perturb the physical layout, AIPO uses a placement legaliser, whenever cell overlaps are caused by upsizing, or to physically identify a legal location to place a newly inserted buffer. Based, on layout space availability, one or more cells may be perturbed from their original locations, during legalisation. AIPO results were obtained not by ASTA, but by using an iterative slew override flow, compatible with industry-proven STA tools, to account for cycle cuts. This flow iteratively runs STA on the critical cycles reported from ASTA, propagating slews and moving the cycle cut point forward, until slews settle. In this way, Synopsys PrimeTime was used to compare and contrast pre-AIPO and post-AIPO results. The placement, routing and SPEF extraction steps were performed using Cadence Innovus. Our AIPO timing results demonstrate significant post-P&R improvements of 30% for all three technology libraries. AIPO manages to improve circuit timing, recovering from the impact of both cell placement and wire RC interconnect delays. The area overhead is proportional to the delay improvement, and for GF 22nm, it is more pronounced as the library cells have significantly smaller sizes. The illustrated AIPO Area-Delay Pareto curves, highlight its effectiveness at handling area-delay trade-offs. We believe that this work represents a solid step forward, towards maturing EDA tools for asynchronous design, particularly for their post-P&R implementation and STA analysis, which is key to ease their use by the semiconductor industry. The AIPO algorithm capabilities may be further improved in the future, by supporting a richer set of timing optimisations, as fan-out decomposition, pin re-assignment, netlist restructuring, etc. In addition, instead of focusing solely on closing the timing of the critical cycle, another AIPO process could focus on satisfying asynchronous timing constraints, including isochronic forks, and Relative Timing (RT) Paths. Moreover, since optimisation actions impact multiple metrics, we aim to extend our methodology to evaluate not only performance, but also the trade-offs between area and power. Lastly, as the quality of the optimisation step depends on the accuracy of the analysis tool (whether for timing or power), we plan to enhance the capabilities of the ASTA engine by incorporating more advanced timing models and supporting library formats such as LVF. VII. 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