Benefits of On-wafer Calibration for RF Characterization of InP DHBT Technology Devices

1 Benefits of On-wafer Calibration for RF Characterization of InP DHBT Technology Devices Moussa Ciss´ e1, Nil Davy2, Virginie Nodjiadjim2, Bertrand Ardouin2, Colin Mismer2, Cristell Maneux1, Franc¸ois Marc1, Marina Deng1 1IMS Laboratory, University of Bordeaux, CNRS UMR 5218, Bordeaux INP, Talence, France. 2III-V Lab, joint lab between Nokia Bell Labs, Thales and CEA Leti, Palaiseau, France. Abstract—In this study, calibration methods are performed on passive structures up to 110 GHz using off-wafer standards and on-wafer standards. The open and short transistor interconnect measurements are analyzed through a comparison with the electromagnetic (EM) predictive simulation. The results clearly demonstrate the benefits of utilizing on-wafer calibration methods to improve measurement accuracy by significantly reducing the parasitic effects due to the transistor’s interconnects. Keywords—RF on-wafer characterization, calibration, openshort de-embedding, EM simulation, bipolar transistors, indium phosphide (InP). I. INTRODUCTION The electromagnetic radiation spectrum reveals a gap between the electronic and photonic domains (from 300 GHz to 3 THz in vacuum). Indium Phosphide (InP) Double Heterojunction Bipolar Transistors (DHBTs) have emerged as an attractive solution for this THz gap due to their superior frequency performance and high breakdown voltage, which enhance their power handling capabilities [1]. To fully exploit the potential of InP DHBTs, accurate onwafer RF characterization is essential. In fact, it enables compact modelling by providing the necessary high-frequency measurements for the extraction of specific parameters, as well as the validation of the model at high frequency [2] to allow integrated circuit design at sub-millimeter wave frequencies. Previous studies have demonstrated the application of conventional on-wafer RF measurement methods, such as off-wafer Short-Open-Load-Thru (SOLT) calibration followed by OpenShort deembedding [3], with a precision of up to 110 GHz using pads optimized for industrial process fabrication [4]. However, limitations have been observed in extending these measurements up to 220 GHz. As it was foreseen by the electrical model simulation of the interconnects in [5], the reduction of the parasitics of the de-embedding test structures is crucial to improve the accuracy of the transistor’s onwafer RF measurements beyond 110 GHz. As a consequence, this study provides a comparison between off-wafer SOLT and on-wafer Thru-Reflect-Line (TRL) calibrations through measurements up to 110 GHz of identical test structures as in [4]. Section II shows the design of the RF test structures and the methodology for EM simulation; section III presents the results obtained by measurement and EM simulation up to 110 GHz of Open and Short de-embedding structures. II. METHODOLOGY A. RF Test Structure Design Several samples on which passive devices were fabricated using the InP DHBT baseline technology were designed by III-V Lab. Different de-embedding structures, such as Open and Short, were available, together with transmission lines. Fig. 1 shows a picture of one of these test structures. Fig. 1. Picture of a Pad-Open structure used for on-wafer TRL calibration These passive devices are intended to be measured in order to benchmark calibration methods, and possibly propose any further improvements in the RF test structure design. The preliminary measurement results carried out up to 110 GHz will be shown in Section III. B. EM Simulation In order to verify the accuracy of the off-wafer SOLT calibration and the Open and Short measurements, the electromagnetic (EM) simulation was done by using the corresponding layout of these test structures. The model of the stack was simply based on a single metal layer on top of the dielectric deposited on the indium-phosphide layer, as depicted in Fig. 2. The EM simulation will be used as the physical reference for the validation of the high frequency on-wafer measurements. (a) (b) Fig. 2. Material stack used for EM simulation of Open and Short structures: a) stack cross section, b) 3D view of the simulated Open structure 2 C. Measurement Setup RF measurements were performed using a probe station equipped with a Keysight E5270 Vector Network Analyzer (VNA), covering frequencies up to 67 GHz. To extend the measurement range, the N5260A mm-wave head controller, in conjunction with frequency extenders (N5260-60003), was used for frequencies beyond 67 GHz. 100-µm pitch Picoprobe RF probes, compatible with the RF pads of on-wafer standards, were utilized for measurements in the 1 to 110 GHz range. For calibration, a CS-5 calibration kit paired with the RF probes provider was employed for off-wafer SOLT calibration, while on-wafer TRL calibration was conducted using on-wafer standards, fabricated on the same wafer as the devices under test. III. RESULTS AND DISCUSSION The available Open and Short structures intended for the de-embedding of the transistor’s interconnects were measured from 1 to 110 GHz after performing the off-wafer SOLT calibration. As a result, an excellent agreement between offwafer SOLT calibrated measurements and EM simulation of the Open and Short structures was achieved until 110 GHz, as it can be observed in Fig. 3. The extracted values of open capacitances and short inductances for off-wafer SOLT calibration are: C1=C2= 15 fF, and C12 = 1 fF, while L1=L2 = 36 pH and L0= 6 pH. 0 20 40 60 80 100 0 5 10 15 20 Open capacitances (fF) frequency (GHz) C1_meas C1_sim C2_meas C2_sim C12_meas C12_sim Off-wafer SOLT measurements (a) 0 20 40 60 80 100 0 10 20 30 40 50 Short inductances (pH) frequency (GHz) L1_meas L1_sim L2_meas L2_sim L0_meas L0_sim Off-wafer SOLT measurements (b) P ort 1P ort 2 C1C2 C12 (c) L1L2 L0 P ort 1P ort 2 (d) Fig. 3. Comparison between off-wafer SOLT calibrated measurements and EM simulation of de-embedding test structures up to 110 GHz: a) Open structure, b) Short structure, c) Open equivalent circuit, d) Short equivalent circuit The same comparison was made when the Thru-ReflectLine calibration was performed using standards that were available on the wafer. Instead of placing the reference plane of the calibration at the probe tips, such as the off-wafer SOLT calibration, the on-wafer TRL calibration allows to push the reference plane after calibration along the Thru standard as indicated in Fig. 1. This way, the parasitic effects caused by the contact pads are removed by the calibration. The extracted values for on-wafer TRL calibration are: C1=C2= 3 fF and C12 = 1 fF, while L1=L2= 10 pH and L0= 6 pH. Consequently, the measurements of the Open and Short test structures show less parasitics (capacitive effects reduced by 80%and inductive effects by 72%), as shown in Fig. 4, which was confirmed again by EM simulation. 0 20 40 60 80 100 0 5 10 15 20 Open capacitances (fF) frequency (GHz) C1_meas C1_sim C2_meas C2_sim C12_meas C12_sim On-wafer TRL measurements (a) 0 20 40 60 80 100 0 10 20 30 40 50 Short inductances (pH) frequency (GHz) L1_meas L1_sim L2_meas L2_sim L0_meas L0_sim On-wafer TRL measurements (b) Fig. 4. Comparison between on-wafer TRL calibrated measurements and EM simulation of de-embedding test structures up to 110 GHz: a) Open structure, b) Short structure CONCLUSION We demonstrated that on-wafer calibration techniques offer significant advantages over traditional off-wafer methods. The reduction in parasitic effects by calibration leads to more reliable measurements at high frequencies, particularly for sub-millimeter range applications. Future work will focus on extending this study about benchmarking off-wafer and onwafer calibration techniques to higher frequencies up to 220 GHz and possibly explore other calibration techniques than SOLT and TRL. ACKNOWLEDGMENT This work is supported by the Chips Joint Undertaking and its members through Move2THz project, including the top-up funding by National Authorities under Grant Agreement n° 101139842. REFERENCES [1] A. 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