Capacitive Power Transfer as Scalable Low-Cost Multi-Load Auxiliary Power Supply for Gate Drivers

Received 9 September 2025; revised 8 October 2025; accepted 21 October 2025. Date of publication 31 October 2025; date of current version 12 November 2025. The review of this article was arranged by Associate Editor Lei Gu. Digital Object Identifier 10.1109/OJPEL.2025.3626899 Capacitive Power Transfer as Scalable Low-Cost Multi-Load Auxiliary Power Supply for Gate Drivers ADRIAN AMLER 1(Graduate Student Member, IEEE), LUKAS BEST1, AND MARTIN MÄRZ 1,2 1Institute of Power Electronics at Friedrich-Alexander-Universität Erlangen-Nürnberg, 91058 Nürnberg, Germany 2Fraunhofer Institute for Integrated Systems and Device Technology IISB, 91058 Erlangen, Germany CORRESPONDING AUTHOR: ADRIAN AMLER (e-mail: [email protected]) This work was supported by the Project ECS4DRES through Chips Joint Undertaking under Grant Agreement 101139790 and its members, including the top-up funding by Germany, Italy, Slovakia, Spain and The Netherlands. ABSTRACT Using operating frequencies in the RF range around the 13.56 MHz ISM band, Capacitive Power Transfer (CPT) can provide sufficient power for a wide range of applications even across coupling capacitances of only a few pF. A low power, multi-load power supply can be realized with simple inductorless capacitive links and rectifiers. Multiple loads connect in parallel to a common primary transmission line, driven by a resonant inverter. This scalable low-cost isolating converter can be used in power electronic converters and inverters to simultaneously supply multiple gate drivers with auxiliary power. However, this application presents some unique challenges – in particular, the extremely low coupling capacitances required to limit common-mode interference – which are investigated in this article. It is shown that gate drivers for GaN eHEMTs can be supplied with 35 mW at 5 V using an effective capacitance of only 0.7 pF, and SiCMOSFETs and even Si-IGBTs can be driven at frequencies in the 10–100’s kHz range. Burst tests confirm common-mode immunity even under voltage slopes exceeding 400 V/ns between loads and to ground. INDEX TERMS Auxiliary power, capacitive power transfer, gate driver, low-power, low-cost, multi-load, multi-output, multi-level inverter, radio frequency power conversion, wireless power transfer. I. INTRODUCTION Recent advances in Wide Band Gap (WBG) semiconductors enable new topologies and applications for Radio Frequency (RF) power conversion in the frequency range from 3 to 30 MHz. RF operation can benefit Wireless Power Transfer (WPT) and dc-dc converters using magnetic fields (Inductive Power Transfer, IPT), and especially electric fields (Capacitive Power Transfer, CPT). For CPT, it enables a reasonable power output and power density even with coupling capacitances in the low pF range. Compared to IPT, CPT avoids the use of complex transmission coils, whose losses limit the efficiency and which might require expensive HF litz windings and magnetic cores. Thus, a capacitive power transmission is lighter, more versatile, and cost-effective [1]. CPT has been demonstrated for various applications including wireless charging of consumer electronics and portable devices [2], [3],[4], drones [5], and even vehicles [6], as well as energy transfer in fixed [7] and rotating assemblies [8],[9]. A further advantage of CPT is the easily scalable link in terms of power and number of loads. A multi-load CPT system promises low cost and high convenience [2], which makes it ideal for supplying multiple low-power loads across a short transfer distance while avoiding galvanic contacts with the purpose of galvanic isolation, easier handling, avoidance of corrosion, access to hermetically sealed environments or avoidance of sparks [10]. Possible applications range from charging and supplying sensor networks [11] to gate drivers in complex power electronic systems, as pursued in this article. While multi-load CPT systems have been investigated elsewhere [2],[3],[4],[10],[12],[13],[14],[15],[16],[17],gate driver supplies pose unique challenges to be addressed: rRapid changes of the load-side potential due to switching transitions impose steep voltage slopes across the coupling capacitance – can CPT maintain robust © 2025 The Authors. This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ 1910 VOLUME 6, 2025 FIGURE 1. System concept: (a) Example of a 3-phase, 3-level ANPC inverter requiring auxiliary power to supply 18 gate drivers. (b) Conventional solution with 18 individual dc-dc converters in parallel, driving cost and build volume. (c) Cost-effective and scalable simultaneous supply of all gate drivers using (d) a single HF inverter and transmission line forming a multi-load CPT power supply. common-mode immunity with slopes exceeding 100 V/ns? rA gate driver supply must be low-cost, occupy minimal PCB area, and ideally power all gate drivers simultaneously – how should a CPT system with its inverter, transmission line, and capacitive link be designed to satisfy these constraints and outperform today’s alternatives? The fundamental concept under investigation is illustrated in Fig. 1(c) and (d). The proposed CPT-based supply replaces multiple individual isolated dc-dc converters with a single transmission line, driven by a resonant zero voltage switching (ZVS) inverter. The line acts as a large-scale primary side for multiple CPT links to simultaneously supply various distributed loads and their rectifiers only comprise inductor-less diode bridges. Taking a 3-phase ANPC inverter as an example, as shown in Fig. 1(a) and (c), a single CPT supply replaces up to 18 individual isolating dc-dc converters. This article presents a demonstrator showing the supply of 35 mW across an effective coupling capacitance of 0.7pF, suitable for the gate driver of GaN devices. It is used to prove CM immunity by means of burst testing with up to 470 V/ns. Additionally, the CPT supply is implemented in a 30 kW hybrid switch inverter to supply roughly 200 mW for each of the 6 SiC-MOSFETs and 6 Si-IGBTs. Stable operation at up to 150 kHz and 30 kHz, respectively, could be achieved. This verifies the usefulness and applicability of the presented simple and cost-effective approach. The article is structured as follows: Section II summarizes the state-of-the-art of multi-load capacitive power transfer systems and explains the advantages of a CPT supply over current alternatives for powering gate drivers. Section III covers the components of the novel CPT auxiliary power supply and outlines a design procedure. Practical questions are TABLE 1. Independent Potentials With the Need of Powering Gate Drivers in Different 3-Phase Inverter Topologies discussed and design examples are presented and experimentally verified in Section IV followed by a conclusion in Section V. II. STATE-OF-THE-ART MULTI-LOAD POWER SUPPLIES The following discussion first highlights the constraints and disadvantages of conventional auxiliary power supplies for gate drivers. Secondly, literature on the state-of-the-art of multi-load capacitive power transfer is reviewed and the differences to the presented concept are described. A. CONVENTIONAL AUXILIARY POWER SUPPLY SOLUTIONS Most converter topologies feature multiple switches on various floating potentials. The challenge of cost-effectively supplying gate drivers is illustrated by Table 1. It gives an overview on various topologies and the respective number of separate floating potentials requiring a power supply. Taking a 3-phase ANPC inverter topology again as an example, as VOLUME 6, 2025 1911 AMLER ET AL.: CAPACITIVE POWER TRANSFER AS SCALABLE LOW-COST MULTI-LOAD AUXILIARY POWER SUPPLY FOR GATE DRIVERS depicted in Fig. 1, it has 18 switches, each with a dedicated gate driver, on 9 different floating and 2 fixed potentials. It thus requires at least 11 isolating power supplies, but even multiple switches on a common potential can benefit from a separate supply to prevent oscillations and cross-talk, and to simplify circuit design. Non-isolating supplies (e.g., bootstrap circuits) often require regular switching of the system to sustain the quiescent current draw of the gate driver. More common are isolated dc-dc converters, such as integrated converters, power supply ICs, and inductive singleand multi-output transformer circuits. Also, optical power transfer is used occasionally [18]. As the following examples illustrate, each gate driver often is supplied individually by a dc-dc converter and multiple independent converters are placed side-by-side, driving cost, volume, and complexity. For example, 30 discrete transformers are used in [19] to supply the 30 switches of a 3-phase 7-level flying capacitor/ANPC hybrid inverter. For the single phase 13-level flying capacitor inverter in [20],an ADUM5210 isolator IC with an integrated dc-dc converter is combined with an LM5113 half-bridge driver containing a bootstrap circuit for two neighboring switches, amounting to 12 driverand 12 isolator-ICs for a single phase. Recent work targets inverter optimization [21] and PCB-integrated transformers to reduce cost and parasitic capacitances. However, these integrated transformers suffer from a lower efficiency and occupy a large PCB area [22],[23]. Multi-output designs still can only be achieved if the position of every load is considered in the transformer design as in [24]. Thus, integration efforts have only come as far as integrating a low number of loads in a single, more complex transformer [24],[25] or driving multiple transformers from a single inverter [21]. All mentioned state-of-the-art solutions lack scalability and flexibility concerning the number of loads and their location, especially when multiple loads are spatially distributed, as is often the case in multi-level multi-phase inverters. Multi-load capacitive power transfer overcomes these issues: a single high-frequency transmission line serves as the inverter-side primary coupler. Only one inverter is required, the transmission line can be freely routed throughout the application, and the loads can be realized at an extremely low cost, comprising only the capacitive coupling plates, a rectifier, and a voltage limiter. However, switching events of the supplied gate drivers can cause rapid changes in potential. Any capacitance across a coupler thus triggers common mode (CM) current spikes and should be kept as low as possible. In existing solutions, a good design can achieve capacitances in the range of 1−2pF [25]. For dc-dc converters, only specially optimized integrated devices like Murata’s MGJ1 series and transformers like WE’s AGDT series reach similar values while lower-cost components exhibit capacitances in the 10−20 pF range. The highest CM immunity can be achieved with optical solutions, e.g., using a high-power laser on a fiber-optical cable. They promise extremely high isolation ratings and a negligible coupling capacitance but remain expensive and inefficient [18] and are generally not viable for more complex topologies since a fiber is necessary for each switch. For a comparable performance of the proposed CPT supply with regard to its CM immunity, its effective CM capacitances should be in a similar range as in the abovementioned dc-dc converters. B. MULTI-LOAD CAPACITIVE POWER TRANSFER Multi-load capacitive power transfer systems, i.e., where a single inverter connects to multiple outputs (SIMO), have already been investigated in literature: Although a series connection of loads has been mentioned in [15],[16],[17], multi-load CPT systems predominantly employ a parallel connection of multiple capacitive links to their corresponding loads as the more flexible solution [2],[3],[4],[10],[12],[13], [14]. Among those, a method to obtain an efficiency optimized operating point of an abstracted capacitive link is covered in [10].Ref.[2] proposes a unified model of multiple loads to simplify the inverter design. An LCCL matching network tolerating a varying number of loads and a corresponding inverter are implemented in [4], while [3] and [13] cover CLCL-CL and CLC-CLC matching networks adapted for a multi-load power transfer. Ref. [14] parallels multiple capacitive links for improved power transfer to a single load and [12] uses frequency bifurcation aiming at a reduced interference between loads. Tolerance in regard to position and angle of the load is also an important issue in multi-load CPT systems for WPT applications. It can be realized using methods that have been reported previously, like [26],[27],[28]. However, most existing work covers higher power applications, whose specifications and constraints differ significantly from a gate driver supply. As previously mentioned, a CPT gate driver supply requires ultra-low common-mode capacitances at or below those of the beforementioned alternative technologies (single digit pF) to limit common-mode currents during switching transitions. In most CPT concepts, similarly low coupling capacitance are compensated using matching networks to achieve a sufficient power level – a strategy also used by most previously mentioned literature regarding multi-load CPT. However, secondary-side matching networks are unsuitable for compact, low-cost loads. Alternatively, asymmetric matching networks, limited to the primary side, can be used [11], [29],[30] or – for better scalability – a non-resonant link. Then, the coupling capacitance can be connected directly to the inverter output, thus avoiding a precisely tuned resonant link, but an inverter with a sinusoidal output waveform is required. Most suitable are derivatives of the resonant pushpull inverter adapted for CPT, as mentioned in [31],[32], [33]. Such a non-resonant topology is chosen – contrary to the approaches in existing work – for the scalable CPT-based multi-load low-power auxiliary supply for gate drivers with ultra-low coupling capacitances. III. CONCEPT AND FUNDAMENTALS The system concept of Fig. 1translates to the circuit diagram in Fig. 2. It is defined by four major elements, which are the 1912 VOLUME 6, 2025 FIGURE 2. Multi-load CPT supply consisting of (a) an RF inverter feeding the (b) transmission line with multiple loads connected at x1...xN. (c) Each load comprises the capacitive link, a bridge rectifier, and the actual load modelled by a variable resistance Rl. Equivalent circuits of the connected load for (d) calculating the ac to dc transfer ratio and for (e) modeling the loading of the transmission line at each coupling node. (f) Typical waveforms for the inverter switch voltages usw,1/2, differential line input voltage utl,0, and non-resonant and FHA-simplified rectifier input voltage ul,ac and current il,ac. inverter (a) feeding the high frequency transmission line (b). It connects to multiple differential capacitive coupling nodes and their rectifiers and loads (c). In the following chapters, the fundamentals for each are briefly described and the implications for system operation are explained. A. CAPACITIVE POWER TRANSFER In a fundamental harmonic approximation (FHA), the power transfer across the coupling capacitors and into the rectifier can be described by a capacitive/resistive voltage divider formed between the effective coupling capacitance Ccpl,eand the effective load resistance Rl,ac (Fig. 2(d)). This equals a high-pass and its impedance and voltage transfer characteristics are a function of the cut-off frequency ωc: ωc=Rl,ac Ccpl,e (1) Maximum power is reached when the impedance of the link and the load match, and thus, the operating frequency of the capacitive transmission ωtl equals the cut-off frequency (ωtl =ωc). If the link impedance dominates (ωtl ωc), the capacitive link shows current source behavior with a maximum current of ˆ il,ac,max =ˆutl ·ωtl ·Ccpl,e.(2) To the contrary, if the load resistance dominates (ωtl ωc), the voltage transfer function approaches one. In Fig. 3, these relations are graphically represented. Fig. 4gives an overview on the required capacitance and voltage levels to achieve a certain amount of output power. For a symmetrical link and to minimize CM interference emissions and maximize CM noise immunity, the values of the two differential coupling capacitances should be chosen FIGURE 3. Normalized characteristics of CPT link for (a) output voltage, (b) current, and (c) power, with maximum power at ωtl =ωc, current source behavior at ωtl <ω c, and voltage source behavior at ωtl >ω c. FIGURE 4. (a) Available output power at maximum power point and (b) available current at current source behavior for a CPT link at ftl =13.56 MHz. equal with a value of Ccpl =2·Ccpl,e. In a system with multiple loads as discussed here, the loads cannot be actively controlled individually from a primary side. Therefore, a defined behavior of the link is useful, either similar to a voltage VOLUME 6, 2025 1913 AMLER ET AL.: CAPACITIVE POWER TRANSFER AS SCALABLE LOW-COST MULTI-LOAD AUXILIARY POWER SUPPLY FOR GATE DRIVERS source or a current source to perform a secondary-side power regulation. In literature, either voltage source [4] or current source behavior [2],[13],[16] has been forced using matching networks. While a voltage source behavior seems more practical, a current source behavior allows higher power levels because of higher usable line voltages ˆutl at the same Ccpl,eand output voltage Uout. Also, secondary-side matching networks are avoided and the secondary-side voltage can be stabilized using a Zener diode to dissipate excess power and to eliminate a primary-side power regulation. B. HIGH FREQUENCY TRANSMISSION LINE AsshowninFig.2(b), all loads capacitively couple to a common transmission line at separate positions x1...xN,fed by a single RF inverter. Due to the high operating frequency, the line can only be assumed as a lumped structure and the line voltage sufficiently homogenous, if the system dimensions are well below the effective wavelength of the loaded transmission line. Otherwise, wave propagation along the line and the associated resonance effects must be considered as they cause a standing wave pattern with voltage maxima and minima along the line. This of course has a direct impact on the power transmission to the individual load. For data and analog signal transmission, it is common to terminate the line with a resistor corresponding to the characteristic impedance Z0,eof the line to avoid standing waves. However, losses in the termination are proportional to ˆu2 tl,0and by far surpass the output power at the intended output voltage ratio and the small coupling capacitance values. A terminated line should therefore be avoided to achieve an acceptable efficiency for the application in mind. In case of an open line without termination, line resonance occurs at line length l=(2n+1)·λ 4(3) with n∈N0. A standing-wave pattern emerges with line voltage maxima at the end and along the line at distances of λ/2 that can far exceed the input voltage. Using the telegrapher’s equation, the voltage and current along the line can be calculated by u(x,t)=ˆutl,0·exp (jωtlt)· cosh γe(l−x) cosh γel,(4) i(x,t)=ˆutl,0 Z0,e·exp (jωtlt)· sinh γe(l−x) cosh γel,(5) using the effective complex wave propagation constant γeand the effective complex line impedance Z0,eobtained by γe=(R+jωtlL)·(G+jωtlCe),(6) Z0,e=R+jωtlL G+jωtlCe .(7) In certain applications, it may be useful and possible to distribute the load coupling points along the line in such a way FIGURE 5. (a)–(d) Transmission line geometries (conductor width wand distance d, substrate thickness h, substrate permittivity εr). that the voltage minima are avoided. In general, however, one will try to keep the line length short compared to the effective wavelength calculated by λ=2π mγe.(8) To limit the voltage rise to approximately max( ˆutl(x))<1.5· ˆutl,0, it is necessary to keep the line length below l<λ/8. Twice the system dimensions could be reached without violating the length constraint by using a centrally fed transmission line, thus effectively paralleling two shorter lines. For an auxiliary power supply system, it is thus recommendable to use a tree-like routing of the transmission line instead of a longer winding line to reduce line effects. As the line parasitics affect the system operation, the line geometry should be chosen correctly. Basically, all waveguides suitable for the chosen frequency range are also suitable as CPT transmission lines, including cables as well as striplines, as long as the capacitive link can be integrated. Fig. 5shows some practically useful stripline arrangements that can be easily realized in rigid and flexible printed circuit board technologies. The basic design parameters are the width w, spacing d, and thickness of the conductors and the permittivity rof the substrate material, which together define the characteristic impedance of the waveguide. The losses of FR4 in the frequency range used for the CPT supply are negligible. Shielded arrangements with the shield layer(s) connected to the primary-side inverter’s ground or system ground can be advantageous in applications with very high common mode interference by providing a well-defined ground path for CM currents. However, they increase the parasitic capacitances of the line and thus the reactive power in the system, reducing efficiency. In general, the inductance per unit length Lincreases while the capacitance per unit length Cdecreases with a greater conductor distance dor smaller width wresulting in an increased characteristic line impedance Z0,i. Higher Z0,iare favorable to limit reactive power for increased efficiency. For 1914 VOLUME 6, 2025 common geometries, the wavelength λis above 12 m at an operating frequency of ftl =13.56 MHz. This means that for an unloaded line, the criterion of an electrically short line is met up to a length of l<1.5 m. Thus far, the impact of the capacitive loading caused by the coupling nodes is neglected. Loading shortens the effective wavelength and should be considered in the design process (see Section III-E). C. INVERTER For feeding the line, an inverter capable of creating a sinusoidal output voltage at MHz frequencies and amplitudes of up to hundreds of volts is required. While bridge-type inverters have been widely adopted [2],[4],[5],[6],[7],[8],[9], [11],[13],[16], resonant push-pull inverters, as previously covered in e.g., [31],[32],[33], offer an inherent sinusoidal output voltage, can drive a capacitive load (e.g., a CPT link) directly without any matching networks, and provide a gain of ˆutl,0≥π·Uin.(9) at its output over the input voltage Uin. This characteristic is beneficial for driving the transmission line as it allows for a higher line voltage without requiring an external step-up converter. The derivate of the resonant push-pull inverter in use is shown in Fig. 2(a). Its operating principle has been extensively covered in [32] and is therefore only briefly described here. The inverter consists of two low-side switches S1/2, two resonant inductors Lσand a dc choke Lh.Thetwo switches are turned ON complementarily with a duty cycle of 50 % at a fixed switching frequency of ftl. This results in a resonant oscillation with a frequency fres between the series connection of both resonant inductors Lσand the effective capacitance Ctot across the currently turned-OFF switch. The effective total capacitance comprises the parasitic capacitance of the switch and the PCB layout, summarized to Cinv,aswell as the effective capacitance value of the transmission line at its input terminal Ce. Usually, no discrete capacitor is added. The fact that basically all parasitic elements of the circuit can be meaningfully integrated into its operating principle, its symmetrical structure, and the simple gate control thanks to the two low-side switches are outstanding advantages of the topology. When operated at or slightly below the effective resonant frequency fres, the voltages at the switches have the characteristic of a sinusoidal half-wave with the voltage returning to zero before the switch turns ON, thus achieving Zero Voltage Switching (ZVS). Its typical waveforms are shown in Fig. 2(f). Within the limits described in [32] the inverter can drive a variable load without losing ZVS. Varying capacitive loads result in a change of the resonant frequency with lower loads causing a higher resonant frequency. The inverter can handle this despite the fixed operating frequency by naturally introducing a free-wheeling state in which both switch voltages are zero and one switch conducts current in the reverse direction. D. RECTIFIER AND LOAD The rectifier proposed for this application is a conventional full-bridge rectifier (see Fig. 2(b)) since its simple and costeffective design allows for a lightweight and low volume secondary side. Its ideal pulsed waveforms are explained in detail in [32] and are shown in Fig. 2(f). In practice, the changing of the rectifier state will cause ringing due to parasitic inductances. However, it does not negatively influence the power transfer and it can be damped for EMI purposes using inline chip inductors. To simplify the design process and under the assumption of Uout ˆutl,0,the impedance of the coupling capacitances is dominant in the series connection with the rectifier. Then, current source behavior can be assumed. This simplifies the rectifier model since otherwise the conduction states and the current flow angle must be taken into account, like in [29],[32]. By means of a fundamental harmonic analysis (FHA) an ideal rectifier can be simplified to an equivalent resistance Rl,ac [34], which can be calculated from the dc load resistance Rlby Rl,ac =8 π2Rl.(10) The relationships between line and output voltages and currents are then as follows: ˆul,ac =4 πUout,(11) ˆ il,ac =π 2Iout.(12) An important parasitic element of the rectifier is its equivalent input capacitance during the non-conducting state Crec. A major, unavoidable contribution to Crec are the parasitic capacitances of the rectifier diodes. If Crec is not significantly smaller than the coupling capacitances Ccpl,e, its effect has to be considered, as mentioned in [4],[29],[32]. In the present case, the rectifier capacitance absorbs a part of the available link current, which consequently is not available for power transfer. In the equivalent circuit (Fig. 2(d)), the rectifier capacitance Crec appears in parallel to the ac-equivalent load resistance Rl,ac. A detailed analysis can be performed based on the explanations given in [32]. In the following, a design guidance based on an FHA is sufficiently accurate. Should the available power be too low, slightly adjusting the input voltage of the RF inverter can compensate minor inaccuracies. E. DESIGN PROCEDURE The general design procedure bases on the applicational loadside requirements, which typically specify the number of loads N, the output power per load Pout,n, and the output voltage Uout. Also, in most applications the coupling capacitance Ccpl,eis limited by isolation requirements (e.g., common-mode currents in a gate driver power supply) or size requirements (e.g., max. copper area on a PCB). Based on the FHA, the necessary line voltage can be calculated by ˆutl = 1+jωtlRl,ac Crec +Ccpl,e jωtlCcpl,eRl,ac ·ˆul,ac.(13) VOLUME 6, 2025 1915 AMLER ET AL.: CAPACITIVE POWER TRANSFER AS SCALABLE LOW-COST MULTI-LOAD AUXILIARY POWER SUPPLY FOR GATE DRIVERS FIGURE 6. Required line voltage ˆutl according to (14) with respect to the a given output voltage Uout and coupling capacitance Ccpl,eto achieve a certain output power Pout,nat ftl =13.56 MHz. With (10) and (11), this extends to ˆutl = π 2 1 jωtlCcpl,e·Pout Uout +4 π1+Crec Ccpl,e·Uout (14) and shows the main trade-off options. The first term corresponds to the current source behavior of the capacitive link for which the operating frequency ftl, the coupling capacitance Ccpl,e, and the (inverse) output current 1/Iout are interchangeable. The second term of (14) models the behavior of the rectifier, including the effects of its input capacitance Crec. Evaluating the second term for Crec yields that to compensate its effects ˆutl should be increased by ˆutl =4 π Crec Ccpl,e·Uout (15) As a rule of thumb, one should keep the relative increase below 10 %. Fig. 6gives an overview for some common specifications for the gate driver supply and the required ˆutl. In general, higher ˆutl are necessary when a higher Pout,n,lowerCcpl,e,or lower Uout are specified. In the opposite direction, the system approaches voltage source behavior and ˆutl only slightly above Uout are necessary. The modelling of the transmission line should consider its loading by each of the coupling nodes. The equivalent capacitance Cn,eand conductance Gn,ecaused by each node (see Fig. 2(e)) is given by Cn,e=1 ωtl mjωtlCcpl,e1+jωtlCrecRl,ac 1+jωtl Crec +Ccpl,eRl,ac ,(16) Gn,e=ejωtlCcpl,e1+jωtlCrecRl,ac 1+jωtl Crec +Ccpl,eRl,ac .(17) Assuming Crec Ccpl,eand an operation in the current source regime of the capacitive link, i.e., ωtl ωc(see (1)), these expressions can be simplified to Cn,e∼ =Ccpl,e,(18) Gn,e∼ =ωcCcpl,e 1+ωc ωtl 2=Rl,ac Rl,ac2+1 (ωtlCcpl,e)2 .(19) The line parameters depend on its geometry. In case of an electrically short line, resonance effects can be neglected during the design process and all coupling nodes are combined into a lumped equivalent capacitance. This results in Ce=Ci·l+Cn, =Ci·l+Cn,e·N.(20) Note that if the transmission line is shielded as in Fig. 5(c) and (d) and the shield is connected to the ground of the pushpull inverter stage, the corresponding ground capacitances need to be added. As described in Section III-B, the criterion of an electrically short line below its first resonance is met by l<λ/8. When calculating the wavelength λusing the effective wave propagation constant γe, the loading of the line must be considered because a capacitive load reduces the effective wavelength. This can be done by using an effective line capacitance and conductance per unit length Ce=Ce l=Ci+Cn,e·N l,(21) G=Gn,e·N l(22) Below the first resonance, the voltage along the line is always higher than the input voltage. With l<λ/8, it never rises more than 50%. For the capacitively coupled loads, this means that for some nodes more power is available than designed, which should be considered when stabilizing the output voltage. The inverter is designed for a total effective capacitance Ctot including the inverter capacitance Cinv and the effective line input capacitance Ce: Ctot =Ce+Cinv.(23) As Cinv depends on the inverter switches and cannot be selected freely, the selected ftl determines the inverter resonant inductor values Lσbased on the design premise of the inverter: to maintain ZVS, the resonant frequency fres should be designed to fres =1 2π√2CtotLσ≥ftl.(24) Using the characteristic inverter impedance Z0,inv =2Lσ Ctot ,(25) and at ftl =fres, the resonance causes reactive power of Qinv =1 2 ˆu2 tl Z0,inv =1 2ˆu2 tl ·ωtlCtot.(26) The line geometry should be selected so that its parasitic capacitance Ciis not significantly lower than the loading to not significantly reduce the wavelength λ, but also not too high because of the increased total capacitance Ctot and thus reactive power Qinv. Similarly, the inverter capacitance Cinv should not be too small for a robust resonance but not too 1916 VOLUME 6, 2025 TABLE 2. Different Power Semiconductors and the Required Gate Power as Building Blocks for an Inverter With Inom ≈200 A large to greatly increase Qinv. Thus, a good recommendation is Cinv ≈Ce≈Cn,.(27) to navigate the trade-off between efficiency and robustness. When deciding on the operating frequency ftl, the usage of the ISM bands is recommended for their increased EMI limits, e.g., ftl ={6.78,13.56,27.12,...}MHz. In the current source regime, a higher ftl allows for lower coupling capacitances Ccpl,e. Alternatively, the line voltage ˆutl can be reduced, and thus, Qinv. This helps lowering conduction losses in the inverter inductors and switches, which are the major loss contributors. However, there is a top limit for ftl. Increasing ftl decreases λ, reducing the allowed line length l. Also, driving losses of the RF inverter increase and Cinv can only be reduced if suitable switches are available. In fact, in many cases the parasitic switch capacitances may already be larger than all others. Then, Qinv starts to increase near the end of the current source regime, i.e., if ˆutl cannot be further reduced. The efficiency optimum lies in between. Also note that while the inverter is relatively robust to load and resonance variations, it is recommended to keep free-wheeling short by fres ≈ftl,as discussed in [32], because of the additional losses caused by the reverse conduction behavior of turned-OFF GaN switches. IV. PRACTICAL CONSIDERATIONS AND VERIFICATION In the following, first, practical design considerations are discussed before two designs are built and experimentally tested to verify the principle of operation, CM immunity, and the integration into an actual inverter. A. PRACTICAL CONSIDERATIONS The required power Pgfor a gate driver depends strongly on the system power level, the semiconductor technology, and the intended switching frequency of the supplied power switches. It can be approximated by Pg=Ug·Qg·fsys,(28) with Ugbeing the ON-state gate voltage (assuming 0 V turn-OFF), Qgbeing the gate charge, and fsys the switching frequency of the supplied gate driver of the main power system. Table 2gives examples on the auxiliary power requirements for inverter systems based on GaN-eHEMTs, SiC-MOSFETs, and Si-IGBTs. In all cases, a topological switch with a current rating of roughly 200 A is assumed, made up of paralleled discrete devices, as well as a switching frequency typical for the respective device technology. The required auxiliary power is then calculated by (28), based on the recommended operating conditions in the datasheet. For the auxiliary supply, some headroom should be added for the quiescent current of the gate driver and for a negative turnOFF voltage for SiCand Si-devices. The following design examples of the CPT supply thus specify Pout,n=35 mW at 5 V for GaN and 200 mW at 20 V for Si and SiC. Beside the power transfer itself, a gate driver supply must provide a galvanic isolation and be able to tolerate high voltage gradients between the loads and from the loads to ground. To limit the common mode current, the capacitance Ccm between the gate driver and a common potential, in the present case, the transmission line, respectively the system ground, should be as small as possible. For example, to limit the average CM current ¯ icm to 250 mA during a slope of 100 V/ns, the CM capacitance must not exceed Ccm ≈2.5 pF. However, the coupling capacitances act as in parallel for the common mode path but as in series for the power transfer. For a given Ccm, the effective coupling capacitance Ccpl,emust therefore not exceed Ccpl,e=Ccm 4,(29) which results in Ccpl,e≈0.7 pF. Because of this very small coupling capacitance, minimizing the rectifier input capacitance Crec is of utmost importance to maximize the output power at a given line voltage. Suitable rectifier diodes should be as small as possible as long as a blocking voltage of Uout,a current rating exceeding ˆ il,ac,max and no or negligible reverse recovery are met. For example, Infineon BAT62 Schottky diodes are among the smallest discrete devices available and offer an effective Crec ≤0.3 pF, but have a high forward voltage exceeding 1 V at 3 mA. Rohm’s RB706UM-40 Schottky diode offers better conduction characteristics with a forward voltage below 0.6 V at 20 mA at the cost of an effective Crec ≤1.1 pF. According to (15), the higher the ratio of ˆutl/Uout, the less critical Crec becomes. The influence of the forward voltage on the power transfer is also reduced. To maintain a constant output voltage and avoid voltage overshoots, a Zener diode can be used to dissipate power exceeding the load requirement. Even though less efficient, it is the easiest method for a low-power auxiliary supply to achieve a uniform output voltage as a primary-side control is impossible and a load-side regulation is less cost-effective. In a no-load condition, each Zener diode must dissipate the full transferred power, which in a worst case increases beyond the designed Pout,nproportional to the line voltage if resonance effects begin to emerge. When limiting the line length as previously described, the excess power is at maximum 50 %of the designed power. VOLUME 6, 2025 1917 AMLER ET AL.: CAPACITIVE POWER TRANSFER AS SCALABLE LOW-COST MULTI-LOAD AUXILIARY POWER SUPPLY FOR GATE DRIVERS TABLE 3. Example Designs B. GAN SUPPLY PROTOTYPE In the following, a demonstrator with Ccpl,e=0.7 pF is designed, suitable for the gate driver supply of fast switching GaN devices. For a given output power of Pout,n=35 mW at Uout =5 V, according to (14), a line voltage of ˆutl = 185 V is necessary. N=16 loads are assumed resulting in a total capacitive load Cn, of about 12 pF and a total output power of Pout, =0.56 W. From Cn, alone, a reactive power of Qinv =17.5 var is required to achieve resonance at the selected operating frequency ftl =13.56 MHz. This corresponds to a characteristic impedance of Z0,e=978  and a maximum inductor current ˆ iσ=95 mA. However, the line capacitance and inverter also contribute. Especially, the parasitic capacitance of the inverter switches significantly increases the total capacitance. Using the smallest available 200 V GaN eHEMTs from EPC (EPC2012C), a total effective capacitance of Ctot =100 pF is achievable, resulting in Z0,e=120 ,Qinv =146 var, and ˆ iσ=1.58 A. Assuming a high quality factor of q=100, losses of 1.46 W are still threefold over the output power. Alternatively, very small Si MOSFETs (Ron ≈1) could be used but require higher driving power. While this means a poor conversion efficiency for the auxiliary power supply, its losses are still miniscule for the supplied multi-kW inverter. However, the previous discussion highlights the importance of minimizing all parasitic capacitances in low-power CPT systems operating at RF frequencies. For the prototype, a biplanar line with a conductor width of 1 mm and a distance of 1.2 mm is selected, resulting in Ci=43 pF/m, based on FEM calculations. The final design parameters are listed in Table 3. This geometry can be easily integrated into the inner layers of a 4-layer PCB. Due to the high breakdown strength of FR4, even a single prepreg is usually enough to fulfil the isolation requirements. The loadside capacitive plates are placed symmetrically on the outer layers. For the demonstrator, a single coupling capacitance Ccpl =1.4 pF is realized with an area of 5.5mm 2. TABLE 4. Required Line Voltage in Measurement for an Output of 5 V Across Ccpl,e=0.7pF for the GaN Supply Prototype The purpose of this demonstrator is to verify power transfer over very small capacitance values and to prove commonmode robustness. Table 4shows power measurements taken for different line voltages ˆutl,0and the load resistors were adjusted for the output to reach the design voltage of Uout =5V. The required line voltages are slightly smaller than the theoretical estimate, which might be due to a larger than designed coupling capacitance, resonance effects and higher harmonics along the line or interference from the measurement. C. BURST TESTING To investigate the CM immunity, burst tests have been performed on the gate driver supply demonstrator. A burst signal is injected between the inverter ground and one load-side potential. The current caused by the burst is expected to propagate along the transmission line and affect the push-pull inverter the most because of its resonant capacitors and inductors being in the CM current path, which may influence its resonance. The inverter waveforms have been recorded for different burst signals, see Fig. 7. The burst generator (Schlöder SFT1420) applies a voltage gradient of approximately duburst/dt≈90 V/ns at a burst amplitude ˆuburst of 800 V, respectively, duburst/dt≈470 V/ns at 4.2 kV. A subharmonic oscillation can be seen in the amplitude of the RF inverter voltages for the duration of a few switching cycles. In case of the 90 V/ns burst, the amplitude of the oscillation is almost negligible. In case of the 470 V/ns burst, which by far exceeds voltage gradients commonly found in power electronic converters, the inverter might lose ZVS for a single switching cycle, as marked in Fig. 7(d), but no malfunction is observed. Also, no cross-influence of a burst on one load on the generated supply voltages of neighboring loads can be detected. This is expected, as the capacitive link and the rectifier form a passive uncontrolled system with the link behaving like a current source. The rectifier does not discriminate between intentional signals and disturbances. Any interference either slightly increases the transmitted power, similar to a bootstrap circuit, or cancels itself out through superposition of its positive and negative components. On the rectified side, the dc buffer and clamping circuit smooth out and dissipate potential disturbances. Moreover, switching events are rare compared to the normal polarity reversal of the rectifier and thus bring significantly less energy into the output. The tests thus verify the suitability of the multi-load capacitive power transfer system for the application as auxiliary power supply with a high CM immunity. D. INVERTER INTEGRATION Based on the promising results from the prototype, a CPT gate driver supply is integrated into an actual 3-phase 30 kW 1918 VOLUME 6, 2025