High Current Multi-Stage Gate Drive Unit to Control the Maximum dv/dt

High Current Multi-Stage Gate Drive Unit to Control the Maximum dv/dt Tristan Eberle Chair of Power Electronics TU Dresden Dresden, Germany [email protected] Dirk Rudolph Chair of Power Electronics TU Dresden Dresden, Germany [email protected] Veli-Matti Leppanen LV System Drives ABB Oy Helsinki, Finland Steffen Bernet Chair of Power Electronics TU Dresden Dresden, Germany stef[email protected] Abstract—This paper addresses the fast voltage changes in a hard-switching IGBT based two-level voltage-source inverter. It is well known that fast-switching devices generate high dv/dt values at the inverter output. This paper presents a solution to control the voltage slopes of IGBTs in a flexible manner. The proposed method utilizes a multi-stage architecture to control both the dynamic and static behavior of the IGBT. The control stage of the proposed method is simulated and verified in a test chamber. The measurement results underline the capability to control effectively the di/dtand dv/dtfor IGBTs. Index Terms—Igbt, gate drive unit, dv/dt control, di/dt control, variable gate voltage, switching transients I. INTRODUCTION From July 1st 2021, efficiency class of IE2 is required by the Regulation (EU) 2019/1781 for drives up to 1000 kW, up to 1000 V, and up to 599 Hz. Active front end, low harmonic front end, single phase, and multi-drives are exempted. On the motor side, only induction motors are affected so far, but the regulation for drives covers all types of motors [1], [2]. The efficiency of the inverter could be increased by increasing the switching speed, thus lowering the switching losses, or bluntly by reducing the current densities and flux densities in various parts of the circuit. The first approach usually leads to more expensive semiconductors, while the other leads to increased weight and size, again increasing the cost. In addition, the impulse voltage insulation classes (IVIC) set worth in IEC 60034-18-41 practically eliminate the sole use of faster switching semiconductors [3]. The switching speeds have been steadily increasing from the advent of the IGBT in mid-80’s to the present. Currently the introduction of wide band gap silicon carbide and gallium nitride semiconductors continue this trend. Short rise and fall Funded by the European Union with the grant agreement number 101096387 and by the German Federal Ministry of Education and Research under grant number 16MEE0227. The views and opinions expressed herein are solely those of the author(s) and do not necessarily reflect those of the European Union or the German Federal Ministry of Education and Research. Neither the European Union nor the German Federal Ministry of Education and Research can be held responsible for them. times of the currents and voltages during switching cause high frequency radiated electromagnetic emission, which must be kept below the allowed limits. The dv/dtitself stresses the first turns of the motor winding. Moreover, the voltage wave is reflected at the motor terminals depending on the cable length. The propagation speed of the wave is approximately 100 m/µs. The reflection increases the peak voltage at the motor end from the initial peak voltage at the inverter source. The increase is due to the mismatch of the wave impedance of the cable (few tens of ohms) and the motor (a few hundred ohms). High dv/dtleads to the full reflection of the voltage even with relatively short motor cables (a few tens of meters). Reducing the dv/dtwould be a straightforward way to reduce the insulation stress and emission levels. However, this will typically lead to higher switching losses in the power switches. This paper considers a multi-stage gate drive unit to control the dv/dtof IGBTs to acceptable levels without extensively increasing the switching losses to improve the overall system performance. II. TURN-ON SWITCHING BEHAVIOR OF IGBTS The turn-on switching behavior in a half-bridge configuration with an inductive load is shown in Fig. 1. The turn-on characteristic is divided into four distinct sections, as described in [4]. These sections are represented in Fig. 2 using different colors: cyan, green, gray and yellow. •Before the IGBT T2is turned on: The diode of T1carries the current of ILand IGBT T2remains turned off. •Section 0 (S0, cyan): The gate-emitter voltage vGE,2rises until it reaches the threshold voltage VGE,th. During this phase, the collector current remains zero because the IGBT is not yet in conduction mode. Consequently, there is no voltage drop across the stray inductance, and thus no voltage drop across the collector-emitter terminals of the IGBT T2. •Section 1 (S1, green): The gate voltage continues to rise, and the current starts to commutate. Consequently, a voltage drop occurs across the stray inductance, causing the collector-emitter voltage to decrease. •Section 2 (S2, gray): The Miller plateau is reached, and the gate-emitter voltage ceases to rise as the gate CDC,link iDC+ LσiC,1 T1 T2 iC,2 RShunt LLoad iL GDU vDC,link vGE,2vCE,2 vCE,1 IGBT Module Fig. 1. Schematic of a half-bridge with an inductive load and the stray inductance current flows through the Miller capacitance. The reverserecovery current of the diode of T1decreases until iC,2 equals the output load current iL. The voltage commutes from the diode to the IGBT. •Section 3 (S3, yellow): The Miller capacitance becomes fully charged, and the gate voltage rises to the driving voltage. The collector-emitter voltage continues to decrease until reaching saturation at vCE,sat. Only the first part of section 1 and the section 2 are important for controlling the maximum dv/dt. a) Section 1: dv/dtcaused by d2iC2/dt2 Change of di/dt, which causes a dv/dtS1 across the stray inductance Lσ, as given by the following equation: VDC,link =Lσ diDC+ dt+vCE,1+vCE,2(1) iDC+ =iC,1+iL(2) Differentiating of (2) under assumption of a constant iL gives diDC+ dt=diC,1 dt(3) Assuming that vCE,1= 0 because the diode still conducts and substituting (3) into (1) results in VDC,link =Lσ diC,1 dt+vCE,2(4) Under the assumption of a constant VDC,link, differentiating (4) with respect to time gives dvCE,2 dt=−Lσ d2iC,1 dt2.(5) b) Section 2: dv/dtS2 caused by voltage commutation from diode to IGBT This section can be controlled by adjusting the duration of the Miller plateau. The proposed method can adjust both di/dtand dv/dtS2 of the IGBT, making it possible to control the maximum dv/dt. 0 vGE,Miller vGE,max vGE,2 vGE,th 0 imax iL iC,2 t0t1t2t3t4t5 vDC vDC vDC,σ vDS,sat vCE,2 vDS,on | {z } sec1 |{z} sec2 Fig. 2. Idealized turn-on behavior of the IGBT vGS,iCand vCE divided into four main sections according to [4] III. PROPOSED METHOD A. Motivation and Requirements For this application, the IGBT half-bridge module IFF750B12ME7 B11 in the EconoDUAL™ 3 package is used [11]. It consists of TrenchStopTM IGBT7 chips with an integrated shunt resistor. The internal gate resistance is 0.5 Ω. This control method is also suitable for di/dtcontrol and, therefore, for current balancing in IGBT modules connected in parallel. Due to the high importance of an IGBT parallel connection this feature is considered in the gate drive unit design. In addition, the gate drive unit should fulfill the following requirements: •Balancing the current in a parallel connection of modules. •Controlling the maximum dv/dtwithin a range of 1 kV/µs. Thus, the gate drive unit should be able to: •Deliver a peak current of IPeak = 30 A. •Operate at a maximum DC-link voltage of vDC,link = 800 V. •Generate different gate voltages during the switching period, which lasts a few 100 ns. •Accurately adjust the on-state voltage during the on-state period. This paper presents the results of controlling the maximum dv/dt. The other features of the gate unit will be elaborated at a later time. According to [5], active gate drive units can be divided into different types, primarily the 1-step-, 2-stepand 4step-control. The approach of using multiple voltage steps to drive the gate of an IGBT is shown in [6]. The authors modify the positive and negative supply voltage of the driving circuit to alter the behavior of the IGBT. Another technique to control the IGBT behavior is switching parallel resistors to increase the gate current [7]. In [8], a method with a 10 bit-DAC and a Class-B current amplifier stage is presented. The output current of the proposed method is realized with bipolar junction transistors (BJTs). Each transistor can drive a maximum current of 3 A, which is why a parallel configuration of transistors was used. The technique presented in [9] controls the gate current by setting the VGS of a MOSFET operating in saturation mode. A high precision DAC is connected to the gate and source terminals to control the saturation voltage, thereby adjusting the drain current used to drive the IGBT. In [10], an operational amplifier circuit composed of an adder and an amplifier is used to control the gate voltage. The output voltage is determined by control signals that modify the voltage divider ratio within the adder circuit, thereby adjusting the input to the voltage amplifier and hence the voltage applied to the IGBT gate. The proposed method in this paper proposes a low-cost approach for varying the gate voltage using a flexible architecture with a low-voltage, low-cost, high dynamic range DAC and a powerful Class-B current amplifier to supply the required high gate current. As this method controls the gate voltage and, consequently, also the gate current, the external gate resistor is no longer needed, reducing the component count. B. Description of the Overall System The schematic structure of the proposed gate drive unit, including feedback of the output current iLand the maximum dv/dt, is depicted in Fig. 3. An FPGA controls the gate drive unit by switching the low-voltage MOSFETs (RE1C001UN [12]) in the DAC block. The THS3491 voltage amplifier from TI [13] amplifies the resulting DAC voltage to the driving voltage level for the IGBT. The Class-B amplifier functions as a current amplifier, consisting of one n-channel MOSFET (RD3H200S [14]) and one p-channel MOSFET (RD3H160SPTL1 [15]) from ROHM Semiconductor. This amplifier supplies the necessary gate current of at least 30 A to drive the IGBT. The output current of the half-bridge IGBT module is sensed using an integrated shunt resistor. A ∆Σ-ADC measures the voltage drop across this resistor and transmits the data back to the FPGA. The maximum dv/dtis determined using a peak detector [16], and its maximum voltage is measured by another ∆Σ-ADC, whose bit stream is then fed back to the FPGA. IV. SIMULATION OF THE CONTROL STAGE An LTspice simulation of the control stage for IGBT turn-on is shown in Fig. 4. The simulation demonstrates how the dv/dtduring the IGBT turn-on can be actively adjusted by varying the gate voltage. However, the effect of di/dt, which induces dv/dt across the stray inductance, is not considered in this simulation. The figure presents two different scenarios, represented in blue and red, corresponding to pulse patterns P1 and P2. The upper figure shows the output voltage of the ClassB amplifier vout (dotted line) and the internal gate-emitter voltage vGE,int (solid line) behind the internal Gate resistor Rint at the gate connection, along with the corresponding Miller plateau duration. The lower Figure depicts the gate currents iG. FPGA RShunt iL DAC AmplrClss-B IGBT Moul GtDrvUnt ∆Σ-ADC ∆Σ-ADC du dt -Msurmnt iL-Msurmnt 1 Fig. 3. Schematic structure of the gate unit with DAC, voltage amplifier, Class-B current amplifier, and feedback measurement of output current and maximum dv/dt TABLE I EQUIPMENT USED FOR TESTING THE PROTOTYPE Device Description Power supply EA-PS 91500-30 imax = 30 A,vmax = 1.5 kV, pmax = 15 kW Oscilloscope Tektronix MSO46 fBW = 500 MHz, fs= 5 GS/s Rogowski Coil CWT15B imax = 3 kA High voltage differential probe BumbleBee fmax = 400 MHz, vmax = 1 kV Low voltage differential probe Saker vmax =±25 V The gate voltage level is varied using the DAC. The red curve represents the case where 17 V is applied earlier. As soon as the 17 V is applied to the gate, the voltage at the output of the Class-B amplifier rises, and the current iGstarts to increase according to iG=vout −vGE,int Rext +Rint (6) where Rext is the external resistor, and Rint is the internal resistance of the IGBT module. A higher gate current results in a faster switching transition, as the switching time is correlated with the gate charge QG according to QG=ZiG·dt. (7) V. VERIFICATION OF THE METHOD A. Test Setup The prototype for the proposed method is tested in a doublepulse testbench. The measurement equipment and voltage source are listed in table I. The IGBT module equipped with its gate drive unit is shown in Fig. 5. The proposed prototyped gate drive unit is positioned on top of the Infineon IGBT module. The output of the IGBT half-bridge is connected to an inductance of LLoad = 100 µH −10 −5 0 5 10 15 20 v/V Δ𝑡Mil.,P1 Δ𝑡Mil.,P2 𝑣OUT 𝑣GE,int 0.0 0.5 1.0 1.5 2.0 2.5 3.0 t/µs −2.5 2.5 7.5 12.5 iG/A P1 P2 Fig. 4. Simulation results of the control stage using LTspice, where one of the small-signal MOSFETs in the DAC is switched at two different times to alter the duration of the Miller plateau Fig. 5. Realized gate drive unit mounted on top of the IGBT and to the positive rail of the DC-link, as can be seen in Fig. 1. To test the gate drive unit, a double-pulse test is conducted, characterizing the low-side switch. The following results are conducted with an external resistor of Rext = 0 Ω, which results in a gate voltage vGE =vvout and a maximum gate voltage of 17 V. Since the gate drive unit can precisely control the gate voltage, the need for an external gate resistor is eliminated. To achieve higher gate currents and to adjust the on-statevoltage in later test, a slightly increased gate voltage is used. B. Measurement Results of the Proposed Method with Time Control In Fig. 6, a pulse pattern with four voltage steps is shown. The gate-emitter voltage vGE transitions from the negative voltage to 6 V,12.5 V and finally 17 V. The duration of the 12.5 V-level gate voltage level is varied systematically. The resulting maximum dv/dtand the maximum di/dtare shown in Fig. 7. If the driving voltage remains at 12.5 V for an extended period, the dv/dtis reduced, as the rise to the 0 500 𝑉CE / V −3.8kV/µs −5.4kV/µs −5.7kV/µs −10.4kV/µs 𝑉CE1 𝑉CE2 0 500 1000 𝐼C,2/ A 5.2kA/µs 6.0kA/µs 6.3kA/µs 8.0kA/µs 50.6 50.8 51.0 51.2 51.4 51.6 t / µs 0 10 𝑉GE,2/ V 12.5V 6V 17V Fig. 6. Turn-on waveforms of the collector-emitter voltage, gate-emitter voltage, and collector current of transistor T2 for an example gate voltage pattern. threshold voltage VGE,th and the Miller plateau VGE,Miller is reduced. The time interval between VGE,th and VGE,Miller determines the di/dt, while the duration of the Miller plateau determines the dv/dt, as illustrated in Fig. 2. In contrast, directly stepping the driving voltage from 6 V to 17 V, both the resulting di/dtand dv/dtreach higher values, as the VGE,th and VGE,Miller are attained in shorter time intervals. In Fig. 7, the mean di/dtof IGBT T2 and the maximum dv/dtare plotted against the duration of the 12.5 V level applied to the gate of the IGBT. As the gate drive voltage remains at 12.5 V for a longer duration, the gate current is decreased, leading to a reduction in both di/dtand dv/dt. The di/dtof IGBT T2 is shown in gray, while the maximum dv/dtvalues for the two sections of IGBT T2 are shown in blue and orange. The |dv/dt|of the first section is significantly higher than that of the second section. Therefore the primary objective is to reduce the dv/dtof the first section. •S1 (blue): The dv/dtof section 1 can be controlled within a range of approximately −10.5 kV/µsto −3.5 kV/µs. •S2 (orange): The dv/dtof the second section remains relatively constant at around −3 kV/µs. However, the results indicate that dv/dtin this section can also be controlled, with values dropping below −2 kV/µs. The dv/dtvalues for IGBT T1 are divided into two parts: •First part: The period until the current reaches Imax. The corresponding rising dvCE,1/dtr,max is positive (green). It is initially high but can be effectively controlled by reducing di/dt. The dv/dtdecreases from approximately −16 kV/µsto −8 kV/µs. −18 −12 −6 0 d𝑣CE,1 d𝑡/kV µs −d𝑣CE1 d𝑡r,max d𝑣CE1 d𝑡f,max −12 −8 −4 0 d𝑣CE,2 d𝑡/kV µs d𝑣CE2 d𝑡sec1,max d𝑣CE2 d𝑡sec2,max 0.0 0.1 0.2 0.3 𝑡(12.5V)/µs −10 −8 −6 −4 d𝑖 d𝑡/kA µs −d𝑖C2 d𝑡mean Fig. 7. Results of di/dtand dv/dtof the measurement over the length of the 12.5 V pulse •Second part: The period in which the current iC,2 falls from Imax to IL. The corresponding falling dvCE,1/dtf,max is negative (red) and can be controlled within a range of approximately −5 kV/µsto −1 kV/µs. The result in Fig. 7 confirm the primary goal of controlling the global maximum dv/dtover a wide range. The resulting losses for this pulse pattern are presented in Fig. 8. The solid lines represent the resulting energy losses of this configuration, while the dotted lines show the datasheet values at room temperature and an external gate resistor of Rext = 0.5 Ω and a gate voltage of VGate = 15 V. The datasheet losses are higher when the duration of the 12.5 V voltage level is either zero or minimal, as the external gate resistor is zero and the driving voltage reaches fast 17 V. However, as the duration of the of 12.5 V voltage level increases, the turn-on energy loss Eon and the total energy loss Etotal increase, whereas the reverse recovery loss Erec decreases. C. Measurement Results of the Proposed Method with Time and Voltage Level Control To optimize the maximum dv/dtin a more loss-efficient manner, a more sophisticated puls pattern, as depicted in Fig. 9, is tested. The new pulse pattern consist of flexible voltage levels to precisely control dv/dtin both sections. Different gate voltages are applied in each section with the objective to optimize •the delay time by applying a high voltage in section zero. •the maximum dv/dtby reducing the di/dtin section 1. •the losses. As the dv/dtin section 1 is low after the current rises and becomes linear, a higher voltage to 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 𝑡(12.5V)/µs 0 20 40 60 80 𝐸/ mJ 𝐸on / mJ 𝐸rec / mJ 𝐸total / mJ Datasheet reference Fig. 8. Losses over the length of the 12.5 V pulse −500 0 500 𝐼/ A 𝐼C,1 𝐼C,2 0 500 𝑉CE / V 𝑉CE,1 𝑉CE,2 82.0 82.5 83.0 83.5 84.0 84.5 85.0 t / µs 0 20 𝑉GE / V 𝑉Class−B 𝑉GE,2 𝑉objective Fig. 9. IGBT turn-on transition with five voltage steps to control the dv/dt and its losses the gate is applied to accelerate the commutation of the current which leads to a steeper current slope and a higher dv/dt. •the maximum dv/dtby lowering the voltage commutation and thus the di/dtin section 2. •the losses, by applying a higher gate driving voltage to increase the dynamic gate drive unit performance regarding changes of the gate current and to accelerate the drop of the drain-source voltage. After the collector-emitter voltage drops to a low level, a gate voltage of 15 V is applied to limit the maximum current in the event of a short circuit. The graphs in Fig. 10 show the maximum dv/dtand the corresponding losses compared to reference measurements using a state-of-the-art control with different gate resistors at a 0 4 8 12 d𝑣 d𝑡max /kV µs d𝑣 d𝑡sec1 d𝑣 d𝑡sec2 d𝑣 𝑑𝑡 GDU,sec1 d𝑣 𝑑𝑡 GDU,sec2 0.00 0.47 1.00 1.50 2.20 3.30 4.70 𝑅ext /Ω 0 40 80 120 𝐸/mJ 𝐸on 𝐸GDU,on 𝐸rec 𝐸GDU,rec Fig. 10. Results of the optimized gate voltage applied to the gate and its maximum dv/dtand its losses compared to reference measurements with different gate resistors and a gate voltage of 15 V fixed gate drive voltage of 15 V. The x-axis indicates the gate resistor values, while the y-axis represents the measured maximum dv/dtand switching losses. The results obtained using the optimized pulse pattern are marked with triangles in both plots. The dv/dtvalues in both sections are nearly identical, demonstrating the goal of reducing dv/dtwhile maintaining low losses. The resulting losses correspond approximately to those observed with a gate resistor of about 0.5 Ω. The loss of EGDU,rec is lower than in the reference measurement as the current commutation is accelerated by the increased gate voltage. This also induces a stronger reverse recovery current spike which leads to a higher voltage drop across the stray inductance Lσ. In this test setup, the IGBT’s maximum voltage rating is not exceeded and therefore, the losses associated with the commutation can be reduced. VI. CONCLUSION This paper presents the realization of a gate drive unit capable of flexibly adjusting the gate voltage to control the maximum dv/dtduring the turn-on switching transition. The primary objective of controlling and reducing the maximum dv/dtis to reduce the dv/dtat the converter output and the insulation stress on the motor windings. The proposed method achieves this by controlling •the di/dtin the first section and •the dv/dtin the second section of an IGBT switching transient. The effectiveness of this approach is demonstrated through both LTspice simulations and experimental results. The dv/dtand di/dtplots validate the proposed method, showing that adjusting intermediate gate voltage levels significantly impacts the switching transients. Additionally, the energy loss analysis reveals a trade-off between dv/dtand efficiency. The experimental results confirm that the maximum dv/dtcan be controlled within a wide range. ACKNOWLEDGMENT The authors acknowledge Infineon for providing the IGBT module and ABB for supplying the inverter. REFERENCES [1] Capiel and CEMEP, ”Information about the Ecodesign Regulation (EU) 2019/1781 for Motors and Drives,” [Online]. Available: https://www.capiel.eu/img/ Information-Ecodesign-Regulation-2019-1781-CEMEP-CAPIEL-1st-Edition-1. pdf. [Accessed: Jun. 18, 2025]. [2] IEC 61800-9-2:2017, ”Adjustable speed electrical power drive systems - Part 9-2: Ecodesign for power drive systems, motor starters, power electronics and their driven applications - Energy efficiency indicators for power drive systems and motor starters,” 2017. [3] IEC 60034-18-41:2014+AMD1:2019 CSV, ”Rotating electrical machines - Part 18-41: Partial discharge free electrical insulation systems (Type I) used in rotating electrical machines fed from voltage converters – Qualification and quality control tests,” 2019. [4] SEMIKRON, ”Application Manual 2015,” [Online]. Available: https://shop.semikron-danfoss.com/out/media/ds/SEMIKRON DataSheet APPLICATION MANUAL 2015 Application Manual 2015 11288080.pdf. [Accessed: Feb. 11, 2025]. [5] Zhang, R., Li, X., Ding, J., Chen, S., Yang, H., & Guo, H. (2024). Review of IGBT Intelligent Gate Drive and Protection Strategies. IEEE Transactions on Power Electronics, 39(6), 7392-7403. https://doi.org/10.1109/TPEL.2024.3372254 [6] Li, C., Tan, K., Ji, B., Wang, Z., Ding, S., and Lefley, P., ”A fourstep control for IGBT switching improvement using an active voltage gate driver,” IET Power Electronics, vol. 15, Feb. 2022, doi: 10.1049/pel2.12248. [7] Nayak, P., & Hatua, K. (2018). Active Gate Driving Technique for a 1200 V SiC MOSFET to Minimize Detrimental Effects of Parasitic Inductance in the Converter Layout. IEEE Transactions on Industry Applications, 54(2), 1622-1633. https://doi.org/10.1109/TIA.2017.2780175 [8] Y. Ling, Z. Zhao, and Y. Zhu, ”A Self-Regulating Gate Driver for HighPower IGBTs,” IEEE Transactions on Power Electronics, vol. 36, no. 3, pp. 3450-3461, 2021, doi: 10.1109/TPEL.2020.3015924. [9] C. Liu, D. Zhang, S. Yang, Y. Wang, Q. Zhou, S. Zhang, R. Min, and Q. Tong, ”An Adaptive Current Source IGBT Gate Driver Based on Current and Voltage Slope Feedback to Reduce EMI,” 2023 IEEE 15th International Conference on ASIC (ASICON), pp. 1–4, 2023, doi: 10.1109/ASICON58565.2023.10396268. [10] Y. Wei, D. Woldegiorgis, R. Sweeting, and A. Mantooth, ”Four Control Freedoms AGD for Hybrid SiC MOSFET and Si IGBT Application,” 2021 IEEE Applied Power Electronics Conference and Exposition (APEC), pp. 2211–2216, 2021, doi: 10.1109/APEC42165.2021.9487290. [11] Infineon Technologies, ”IFF750B12ME7 B11 DataSheet,” [Online]. Available: https://www.infineon.com/dgdl/ Infineon-IFF750B12ME7 B11-DataSheet-v01 20-DE.pdf?fileId= 8ac78c8c8929aa4d018a21fb31542600. [Accessed: Feb. 10, 2025] [12] ROHM Semiconductor, ”RE1C001UNTCL-E datasheet,” [Online]. Available: https://fscdn.rohm.com/en/products/databook/datasheet/ discrete/transistor/mosfet/re1c001untcl-e.pdf. [Accessed: Feb. 10, 2025] [13] Texas Instruments, ”THS3491 900-MHz, 500-mA High-Power Output Current Feedback Amplifier DataSheet,” [Online]. Available: https:// www.ti.com/lit/ds/symlink/ths3491.pdf. [Accessed: Feb. 11, 2025]. [14] ROHM Semiconductor, ”RD3H200SN N-Channel 45V 20A Power MOSFET DataSheet,” [Online]. Available: https://fscdn.rohm.com/en/products/databook/datasheet/discrete/ transistor/mosfet/rd3h200sntl1-e.pdf. [Accessed: Feb. 21, 2025]. [15] ROHM Semiconductor, ”RD3H160SP P-Channel -45V - 16A Power MOSFET DataSheet,” [Online]. Available: https://fscdn.rohm.com/en/products/databook/datasheet/discrete/ transistor/mosfet/rd3h160sptl-e.pdf. [Accessed: Feb. 21, 2025]. [16] Analog Devices, ”Design Note 61: Peak Detectors Gain in Speed and Performance,” [Online]. Available: https: //www.analog.com/media/en/technical-documentation/design-notes/ peak-detectors-gain-in-speed-performance.pdf. [Accessed: Feb. 25, 2025].