A 41.7 MS/s 2.4 ps-rms-jitter Time Converter With 4-Core Interleaved Analog-Multiplexed Architecture

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Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.” Title: A 41.7 MS/s 2.4 ps-rms-jitter Time Converter With 4-Core Interleaved AnalogMultiplexed Architecture Authors: Francesco Malanga, Mehmet Caglar Koca, Mehmet Ali Uluisik, Giulia Acconcia, Ivan Rech Affiliation: Politecnico di Milano, Piazza Leonardo da Vinci 32, 20133 Milan, Italy Corresponding Author: Francesco Malanga ([email protected]) DOI: 10.1109/ISCAS56072.2025.11043405 A 41.7 MS/s 2.4 ps-rms-jitter Time Converter With 4-Core Interleaved Analog-Multiplexed Architecture Francesco Malanga, Mehmet Caglar Koca, Mehmet Ali Uluisik, Giulia Acconcia, Ivan Rech Department of Electronics, Information, and Bioengineering (DEIB),Politecnico di Milano, Milano, Italy [email protected] Abstract—This paper presents a single channel time-toamplitude converter (TAC) that exploits an on-chip timeinterleaving technique to reach an unprecedented conversion rate. Implemented in a 350-nm SiGe process, the TAC features a high conversion rate of up to 41.7 MS/s and a timing jitter of just 2.4 ps-rms over a configurable full-scale range (FSR), selectable among 4 binary-scaled options ranging from 12.5 to 100 ns. The TAC exhibits a peak-to-peak DNL of 0.9% and a maximum INL of 1.2% of the LSB, ensuring linearity across the entire FSR. Index Terms—Timing, low jitter, time-to-amplitude converter (TAC), time-interleaving, fully-differential amplifier, low-dropout (LDO) regulator. I. INTRODUCTION Timing circuits are vital for time-resolved applications with stringent requirements for precision, linearity [1], [2], [3], [4], and conversion frequency [5]. Among the various methods for implementing a timing circuit, a time-to-amplitude converter (TAC) followed by an analog-to-digital converter (ADC) provides high precision and linearity while distributing trade-offs across two cascaded cells rather than integrating them into a single chip [6], [7], [8]. However, TACs have a significant limitation: the measurement and reset times typically lead to a relatively low conversion frequency [9]. On the other hand, interleaving Ntiming circuits can boost the conversion frequency by a factor of Nbut this increases system complexity due to the need for additional pads and ADCs [10]. Moreover, the best commercial ADCs often have much higher conversion rates than TACs, resulting in underexploitation of the full capabilities of the ADC channels. Hence, a more efficient solution is a TAC architecture with parallel conversion channels, employing an on-chip time-interleaving technique to internally multiplex the channels through a single input and single output connection. This paper presents a 4-core interleaved analog-multiplexed TAC, achieving a maximum conversion rate of 41.7 MS/s, combined with timing jitter as low as 2.4 ps-rms and peak-topeak differential nonlinearity (DNL) of just 0.9% of the 0.78ps LSB over the shortest full-scale range (FSR) among the four available options: 12.5, 25, 50, and 100 ns. The paper is organized as follows: Section II describes the operating principle of the analog-multiplexed TAC, Section III details the circuit architecture, Section IV presents the post-layout simulations and results, and Section V provides the conclusions. This work was supported by the European Union under Grant No. 101135876 and Ministero dell’Universit` a e della Ricerca under Grant No. 2022JRSST2. II. OPERATING PRINCIPLE A TAC functions as a high-resolution chronometer, generating an output voltage that reflects the measured time interval by charging a capacitor with a constant current: Vc=Iconv Cconv ·∆T+Vc,0(1) where Iconv is the constant conversion current, Cconv is the capacitance of the conversion capacitor, ∆Trepresents the time interval to be measured, and Vc,0is the initial voltage on the conversion capacitor. The resulting analog signal is then converted into a digital value using an ADC. The top-level architecture of the analog-multiplexed TAC is shown in Fig. 1. It consists of four identical parallel conversion cores, where the time-to-voltage conversion occurs; an output stage that connects these cores to an external ADC; interleaving logic that manages the time-interleaved operation; and a dithering DAC, which applies dithering to mitigate the impact of the ADC on the overall linearity of the acquisition chain. Each conversion core is controlled by its respective front-end logic. Upon receiving start signals, the front-end logic blocks of the cores are sequentially activated by the interleaving logic, allowing multiple conversion operations to occur in parallel. The output stage, which consists of a differential analog multiplexer followed by a fast fully-differential operational amplifier, serves as the interface between the conversion cores and the ADC. The analog multiplexer sequentially selects the converted signals, and the differential amplifier adjusts their dynamic range to match the input dynamics of the ADC. It is crucial for this output stage to possess high bandwidth to accommodate the fast interleaving rate, as the system throughput depends on it. With a settling time much shorter than the dead time of the individual cores, the high-speed output stage enables a significantly higher overall count rate compared to a single-core system. III. ANALOG-MULTIPLEXED TAC STRUCTURE The operating principle described in Section II has been implemented through the novel 4-core interleaved analogmultiplexed TAC, with its simplified schematic shown in Fig. 1. A key innovation in this design is the output stage, which, together with the novel interleaving logic, enables timeinterleaved operation across four parallel conversion cores. These cores, adapted from a single-core TAC [9], have been further optimized by integrating a low-dropout (LDO) voltage Rdith RF Rdith RF Vin+ Vin– OUT_ OUT+ Vout– Vout+ VCM CF CF VBG,2 Ri Ri DC VDD MUX Dithering Logic Output Stage Dithering DACInterleaving Logic Control Logic EN Shift Register MUX Shift Register Reset Strobe Config Calib. ResetDAC ClockDAC VREF + – Ext. St+ Ext. St– + – Ext. Sp+ Ext. Sp– RF CF Cconv Iconv Cconv Iconv VBG,1 SP ST VDD SP ST 0123 LDO Conversion Stage + –VCC VDD Front-end Logic D Q D Q Input Logic Ishift TAC+0 TAC–0 Conversion Cores EN Cdec IDAC+ IDAC– Fig. 1. Overall architecture of the analog-multiplexed TAC. The outputs of the parallel conversion cores are sequentially selected by the output stage. regulator, reducing timing jitter caused by crosstalk between the cores and thereby enhancing system precision. In this design, a single shared dithering DAC has been included to minimize the chip area. Additionally, all connections are differential to reduce disturbance effects. A. Front-end Logic & LDO Voltage Regulator The switches in the conversion stage are controlled by the ST and SP signals, which are generated by the front-end logic upon the arrival of start and stop signals. These start and stop signals arrive at the chip as low-voltage differential signals (LVDS) and are converted to rail-to-rail CMOS signals by the input comparators. They are then internally distributed as clock signals for the D-type flip-flops in the front-end logic to facilitate operation across four cores. The timing jitter of the front-end logic has a direct impact on the measurement precision. Therefore, to minimize timing jitter caused by crosstalk between conversion cores, the frontend logic of each core is powered by a dedicated LDO voltage regulator. The LDO voltage regulator design presented in [12] has been implemented and further improved to provide a clean and stable supply, ensuring precise output transitions. The schematic of the LDO voltage regulator is shown in Fig. 2. The folded-cascode topology of the error amplifier achieves high gain with a single dominant pole. A source follower, M15, in shunt feedback with a bipolar transistor, Q1, is placed between the error amplifier and the pass transistor, M16, to ensure loop stability by shifting the parasitic pole forward introduced by the pass transistor [13]. Ahuja compensation, implemented with Cc, ensures stability over a broad range of load conditions while the 18 pF decoupling capacitor, Cdec, improves the transient response. Monte Carlo simulations show that the DC loop gain never falls below 78 dB, while the phase margin is always greater than 59°, with a minimum gain-bandwidth product (GBWP) of 12 MHz. This guarantees fast response and circuit stability. Furthermore, the LDO attenuates external power supply fluctuations with a power supply rejection ratio (PSRR) of 83 dB at DC and 30 dB at 1 MHz. The reference voltage is externally supplied to minimize output noise. This also allows for adjustments in its value, which may help address potential offset issues in Ahuja compensation [14]. B. Interleaving Logic The block diagram of the interleaving logic is illustrated in Fig. 3. In response to a start signal, the EN shift register activates an available conversion core by enabling its D-type flip-flop, assigning each start signal to a single core and allowing for the time-interleaving of subsequent signals. If all cores are busy when the next start signal arrives, the busy logic disables the shift register, discarding any additional startstop pairs. Based on the arrival of a stop signal, the control logic classifies measurements as either valid or over-ranged. If no stop signal is detected within the FSR, the over-range VDD VREF VFB VFB VOUT VBG,1 VBG,2 VBG,3 VBG,2 VBG,1 M1M2 M3 M4 M7M8 M10 M9 M5M6M11 M12 CC M13 M14 M15 Q1 M16 R1 R2Cdec Fig. 2. Schematic of the LDO voltage regulator. EN Shift Register Busy Logic Disable Front-end Logic Over Range Logic Reset Logic Conversion Stage Valid Logic MUX Shift Register FPGA Shift Logic Control Logic Strobe EN 0 EN 1 EN 2 EN 3 MUX 0 MUX 1 MUX 2 MUX 3 Fig. 3. Block diagram of the interleaving logic. EN Shift Register sequentially enables the cores, Control Logic checks the validity of the conversion, and MUX Shift Register manages the analog multiplexer transitions. logic resets the cores. For valid measurements, the control logic triggers the ADC via the Strobe signal to sample the output voltage. This same signal also triggers the shift logic, which switches the analog multiplexer to the next core through the selection signals from the MUX shift register. Overall, the interleaving logic ensures that the data are stored first, then the multiplexer transitions to the next core, and finally, the selected core is reset. C. Output Stage As in [9], an output stage is needed to align the dynamic range of the converted signals with the ADC input dynamics and to add the differential dithering signal to them. Preserving the downshifting current generator, Ishift, from [9] and excluding the dithering contribution (i.e., IDAC+ =IDAC−= 0 in Fig. 1) for simplicity, the differential output is expressed as Vout,diff =VTAC,diff · RF+Rdith Ri+Ron −Ishift ·(RF+Rdith)(2) where VTAC,diff is the differential conversion stage output and Ron is the multiplexer on-resistance. With Ishift = 400 µA and RF+Rdith =Ri+Ron = 2.5 kΩ, the converted signals are transferred to the ADC with unity gain, shifted down by 1 V. The output common-mode voltage is set to 0.9 V by the common-mode feedback network of the operational amplifier. The 4x1 analog multiplexer features four parallel 5-V transmission gate switches that offer bidirectional conduction, constant on-resistance (Ron), and reduced charge injection, which are essential for maintaining the unity differential gain of the output stage across varying input voltages, thereby improving system linearity. The transmission gates have been sized with (W L)p=34.8µm 0.5µm and (W L)n=22.4µm 0.5µm , resulting in a width ratio of 1.6 to ensure equal transconductance between the two transistors and a flat Ron profile across the input range. While larger switches could further reduce Ron and improve linearity, they would also lead to higher parasitic capacitance, slowing down the stage. The output stage includes a fast, GHz-bandwidth operational amplifier to support the high interleaving rate of the system. Its schematic, along with the common-mode feedback network, is shown in Fig. 4. The fully differential design minimizes common-mode disturbances and crosstalk between the conversion cores. The amplifier achieves a high GBWP using 5-V transistors. A folded-cascode gain stage with a bipolar input pair provides high gain in a single stage. The cascode BJTs Q3−6, regulated by the common-mode feedback, boost the loop gain by increasing output resistance. The emitter followers Q7−10, biased by current generators M6−9, reduce the output resistance and ensure a sufficient collector–emitter junction voltage for Q3−6to operate in the correct region. The large sizes of Q9−10 and M8−9provide high current to the ADC, yielding a slew rate of 740 V/µs with the ADC load. The nulling-resistor compensation with Ccand Rc, as well as the feedback capacitor CFin Fig. 1, ensures loop stability. Monte Carlo simulations show a consistently high GBWP, never dropping below 1.2 GHz. The average loop gain of 69 dB ensures minimal transfer errors. The phase margin remains above 45°, which guarantees stability and fast settling time, even in the face of process variations and mismatch. Additionally, the common-mode feedback ensures a minimum common-mode rejection ratio (CMRR) of 50 dB, efficiently suppressing common-mode disturbances at the output. IV. POST-LAYOUT SIMULATIONS AND RESULTS The die micrograph of the chip is shown in Fig. 5. The chip is implemented in 350-nm SiGe technology with a 5-V supply voltage and has an area of 4.16 mm2. The chip is currently undergoing testing; however, the expected performance has VREF2 RcCc Vin+ Vin– VREF3 VREF3 VREF1 VREF1 VREF2 VDD M1M2 M3M4 M5M6 M7 M8M9 Q1Q2 Q7 Q8 Q9 Q10 vo+ vo– M10 M11 Q11 Q13 Output Stage Differential Amplifier CMFB Error Amplifier Q3Q4 Q6 Q5 M12 M13 CCM1 RCM1 RCM2 CCM2 VCM Vout+ Vout– VDD Q15 Q14 Fig. 4. Schematic of the fully-differential operational amplifier, including its common-mode feedback network. Fig. 5. Die micrograph of the TAC fabricated in 350-nm SiGe technology. (a) DAC, (b) interleaving logic, (c) start/stop differential trigger distribution, (d) conversion cores, (e) output stage (zoomed-in on the right). been evaluated through post-layout simulations conducted under various process and temperature conditions. The precision of the TAC is calculated as the quadratic sum of uncorrelated jitter and noise components. The timing jitter of the digital part, from the comparator input to the conversion stage switches, is 0.73 ps-rms. The voltage noise of the circuit can be divided into two dominant uncorrelated components: white noise and integration noise. The former, mainly sourced from the downshifting current generator in the output stage, is 290 µV-rms. The latter is proportional to the square root of the measured time interval due to gated integration during the charging of the conversion capacitors. Combining these contributions, the worst-case timing jitter is 2.4 ps-rms over the 12.5 ns FSR, as reported in Fig. 6. The differential nonlinearity (DNL), along with the integral nonlinearity (INL), is shown in Fig. 6. The TAC exhibits a peak-to-peak DNL below 0.9% of the LSB, with degradation at short time intervals due to the oscillating transient behavior of the conversion current generators. The INL, featuring a similar behavior, never exceeds 1.2% of the LSB. Fig. 7 illustrates the differential output voltages of the conversion cores and the analog-multiplexed TAC, showing the measurement of consecutive intervals with a pseudo-random pattern over the 12.5 ns FSR. While one conversion core is being sampled by the output stage, the previous core can be in the reset phase, and the next core can be in the integration phase. The external ADC, operating at a sampling rate of 125 MHz, offers 14-bit resolution with a corresponding LSB 10 12 Conversion Interval [ns] -1.2 -0.6 0 0.6 DNL & INL [% LSB] 1.8 2 2.2 2.4 Precision rms [ps] DNL INL Precision 8642 0 Fig. 6. DNL and INL of the TAC expressed in percentage of LSB and timing precision expressed as rms jitter as a function of the input time interval. 0 1 2 Voltage [V] Core 0 Core 1 Core 2 Core 3 96 120 144 168 Time [ns] -1 0 1 Voltage [V] OUT 7248240 Fig. 7. Differential outputs of conversion cores (top) and the output stage (bottom). The conversion rate can be as high as 41.7 MS/s. of 122 µV (782 fs). Using half an LSB as the margin for steady-state accuracy, Monte Carlo simulations indicate that the maximum settling time for a full-scale transition is always shorter than 3 clock cycles of the ADC. Therefore, when the external ADC operates in synchronization with the periodic stop signal, the overall dead time of the conversion process is determined solely by the settling time of the output stage. Consequently, under the worst conditions, the TAC achieves a maximum conversion rate of 41.7 MS/s. If synchronization with the ADC is not possible, an additional ADC clock cycle must be considered as an uncertainty margin in the dead time computation, thereby limiting the maximum conversion rate to 31.3 MS/s. Table I summarizes the performance of the TAC alongside state-of-the-art works. This work is expected to achieve a remarkably high conversion rate with few picosecond precision and near-ideal DNL. V. CONCLUSION The 4-core interleaved analog-multiplexed TAC, designed in 350-nm SiGe technology, demonstrates the feasibility of onchip interleaving through the internal multiplexing of parallel conversion cores, achieving unprecedented conversion rates while preserving the performance of a single-channel system. Future enhancements to this architecture will aim to scale up the number of cores, potentially leading to a pipelined and interleaved design that boosts throughput through the use of an inner sampling architecture (S&H) or by incorporating the external ADC directly onto the chip. TABLE I PERFORMANCE SUMMARY AND COMPARISON [9] [15]* [16] [17] This Work* Process [nm] 350 65 28 130 350 Range [ns] 12.5 100 180/20 1600 12.5 Resolution [ps] 0.78 - 43/4.7 22 0.78 Precision [ps-rms] 1.9 55.4 33.1/7.14 10 2.4 DNLmax [LSB] 0.02 - 0.58/1.13 0.9 0.005 Frequency [MS/s] 12.3 - 4.94/3.51 40 41.7 Power [mW] 70 0.26 0.07/0.19 162 300 Area [mm2] 0.2 0.013 0.01 3.7 4.16 *Simulated performance REFERENCES [1] L. M. Hirvonen et al., “Lightsheet fluorescence lifetime imaging microscopy with wide-field time-correlated single photon counting,” Journal of Biophotonics, vol. 13, no. 2, Feb. 2020. [2] A. Rudkouskaya, N. Sinsuebphon, X. Intes, J. E. Mazurkiewicz, and M. Barroso, “Fluorescence lifetime FRET imaging of receptor-ligand complexes in tumor cells in vitro and in vivo,” Proceedings of SPIE, vol. 10069, Feb. 2017. [3] Z. Cai, H. Xu, J. Xiao, and J. Yang, “An improved BIJM circuit based on undersampling technique,” IEICE Electronics Express, vol. 15, no. 8, p. 20180124, Jan. 2018. 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