Analysis Of Harmonic Mitigation Techniques For Cascaded Asymmetric Inverters

POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 22 |NUMBER: 1 |2024 |MARCH Analysis Of Harmonic Mitigation Techniques For Cascaded Asymmetric Inverters Lakshmi PRASANNA1, Jyothsna.T.R.2 1Electrical Engineering, Research Scholar, Andhra University, Maddilapalem, Visakhapatnam, India 2Electrical Engineering, Professor, Andhra University, Maddilapalem, Visakhapatnam, India [email protected], Thummalajy[email protected] DOI: 10.15598/aeee.v22i1.5641 Article history: Received Dec 30, 2023; Revised Mar 7, 2024; Accepted Mar 22, 2024; Published Mar 31, 2024. This is an open access article under the BY-CC license. Abstract. Multilevel inverters (MLIs) are attracting the attention of academics as well as industry as a feasible technology for an extensive variety of purposes, like renewable energy sources, and Electric vehicles. MLIs are commonly employed as a part of the sophisticated converter configurations in both high and medium voltage applications. The creation of minimised switch MLI structures remains a key objective of the present research with the goal to achieve superior results despite of involved a greater number of switches. Basically, various layouts of asymmetrical configuration using enhanced cascaded bridge topologies are identified in a brief overview and evaluated against important parameters. It is a method of designing multiple voltage levels using identical switch count and fewer devices. This work describes numerous varieties of harmonic mitigation techniques, and it also outlines the most effective switching angle optimizations to produce various levels. Furthermore, the effectiveness of configuration is evaluated based on minimising THD due to decreasing lower order harmonics. THD is evaluated against various mitigation techniques employing certain proportions of source voltages coming from solar energy /batteries. THD is calculated theoretically and contrasted to simulation outcomes for the suggested configurations. The simulated waveforms of various configurations are examined using Hardware in loop (HIL) application. Keywords Asymmetric Inverter, Harmonic mitigation techniques, Low frequency scheme, Total Harmonic Distortion,OPAL-RT(OP4510). 1. Introduction The incorporation of renewable energy sources into the currently operating power network significantly improved system reliability. The most important environmentally friendly power sources are solar and wind energies. Solar energy interconnection necessitates the inclusion of converters, a type of simply dc to ac converters. The primary features of implementing MLIs in applications such as electric vehicles and renewable energy sources are enhanced power density, greater effectiveness, less harmonic distortion, more effective voltage control, flexibility, adaptability, and compatibility with renewable energy sources. MLIs are a desirable option for a variety of applications in the renewable energy and electric vehicle sectors due to these advantages MLIs are frequently utilised for such applications [1,2]. Classic MLI configurations such as neutral point clamped MLI (NPCMLI), cascaded H-bridge MLI (CHBMLI), and flying capacitor MLI (FCMLI) have become commonplace in practical applications. The CHB inverter topology necessitate minimal component count than other conventional inverter topologies for creating an identical level of output. CHB inverters are transitioning from a traditional perspective to real-world applications due to capabilities that includes high degree of modularity, the ability to safely link to medium voltage with superior power quality [3,4]. As a result, MLIs using fewer components are employed in recent studies to create the identical number of levels identical to the traditional configuration. Despite this, the approach of minimizing component counts displays certain difficulties to academics. However, researchers encountered a few obstacles while c 2024 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 36 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 22 |NUMBER: 1 |2024 |MARCH attempting to minimize component counts, such as enhanced rated voltage of switching devices, losses in extensibility, minimization of concurrent modes count, occasionally demand of bidirectional switches, advanced control methodologies, a massive number of sources to accomplish the anticipated level count from the existing topologies [5–9]. Nevertheless, by integrating sustainable energy sources to act as independent input for the cascade inverters, this drawback can be rectified. In comparison to other conventional inverter structures, the CHBMLI needs less switch count and all other factors taking into count to create identical voltage levels in the output [10]. By utilising improved cascaded bridge topologies in asymmetrical configurations, it is possible to achieve multiple voltage levels with a minimum number of switches by considering benefits of asymmetric voltage division. These configurations are desirable for a wide range of applications since they offer positive aspects like less switch count, optimized number of levels, greater efficiency, and improved fault tolerance. Due to features such as a good extent of modularity, the ability to securely connect to medium voltage, and good power quality CHB inverters transitioned from a traditional view to real world applications. Subject to the level of output voltage CHBMLI is generally called symmetric or asymmetric. Those are (i) equal voltage cascaded MLI(ECHBMLI), where all input voltages are in equal magnitude, (ii)natural sequence cascaded MLI(NSCHBMLI), where all input voltage follows arithmetic progression each is differed by one, (iii) binary cascaded MLI(BCHBMLI), where successive input voltages are doubled,(iv)trinary cascaded MLI(TCHBMLI), in which successive input voltages are tripled,(v)quasi-linear cascade MLI(QLCHBMLI), where all input voltages are kept constant so that the anticipated resulting voltage is reached. Modulation techniques are the fundamental aspects for any MLI structure. In fact, suggesting novel modulation schemes that can be implemented for any type of structure in order to meet specified requirements can be viewed as a distinct area of research [9,13]. Modulation is the process of control the voltage waveform using switches to meet specified requirements. MLI modulation schemes are commonly categorized as high frequency (HF) or low frequency (LF). In [27], fifteen level configuration is described utilizing high frequency control scheme. Hybrid modulation scheme is employed for fifteen level topology described in [26]. The low frequency control scheme possesses numerous significant features, which includes (a) highly efficient with low frequency to fundamental frequency proportion; (b) excellent voltage boosting and a wide converter capacity; (c) fewer filter demands; (d) complete omission of lower harmonics; (e) low switching losses with restricted harmonic regulation; and (f) additionally performance index is optimised for various superior aspects. Various modulation schemes for 15-level topology are presented [23,24]. The worth of utilizing a LF scheme than HF scheme are reduced switching losses, minimum stress on switches, improved device utilization factor, and enhanced converter efficiency. Selective harmonic elimination (SHE), nearest level control (NLC), and space vector control (SVC) are some of the popular LF schemes [11,12]. Utilizing NLC fifteen level is developed in [25]. Employing NLC distinct thirteen level topologies designed [28–30]. If greater the number of levels, SVC is a reasonable technique only issue is it does not eliminate specific harmonic. The above problem is mitigated using the SHE method by adjusting the switch angles mentioned in [10,14]. Review of SHE technique algorithms described [18–20]. Minimization of harmonics utilizing Particle Swarm Optimization (PSO) approach for symmetrical MLI configuration is presented [15,17]. Furthermore, PSO approach [21] is lacking to estimate switching angles for specified modulation indices (ma) based on computational results from Genetic Algorithm (GA) approach [22]. As the level of output extents, obtain solutions using SHE become more challenging to implement. As a consequence, another straightforward approach of SHE addresses above issue have been executed in [16], that is harmonic mitigation which involves remarkable minimization of lower order harmonics rather than entirely eradicating them. An asymmetrical cascaded bridge MLI topology is proposed in this work, as well as mitigation techniques. The following positive aspects are offered by the recommended work: •The application to mitigation techniques has been efficiently carried out, it is easily resolved to configure up mathematical analysis and leads to lower voltage stress. •It operates efficiently with a wide range of loads. •The article outlines an open-loop structure and new cascade asymmetric inverters that are tested using the OPAL-RT simulator. This work has the following structure Section 2. confronts proposed topologies with all switching states for thirteen and fifteen respectively. Section 3. focuses on mitigation techniques, Voltage stress analysis and Loss analysis. Section 4. explores simulation results, Thermal modelling and HIL Implementation, Section 5. compares proposed asymmetrical configurations with other topologies and Section 6. refers to conclusion of work. c 2024 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 37 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 22 |NUMBER: 1 |2024 |MARCH Load S4 S2 S1 S3 S5 S7 S8 S6 S12 S10 S9 S11 V1 V2 V3 - V0 + Fig. 1: Proposed Topology 2. Proposed Topology Figure 1 shows the planned H-bridge configuration before learning more about configurations. It has three voltage sources and twelve switches that are IGBTs in antiparallel with diodes. The following subsections detail the switching states and modes of operation for the voltage sources that are classed as 13-level, and 15-level configurations based on ratings. 2.1. Thirteen-Level Configuration Figure 2 shows the switching states for this method, which is a part of the NSCHBMLI. In Figure 2, red denotes the conducting path of the matching switches, while green denotes the non-conducting path. Twelve switches are in view with three preferred voltage sources are arranged as a natural sequence magnitudes while creating levels. Since voltage sources are rated the same, all switches are also rated the same. table 1 represents the switching capabilities of switches for creating the required level of voltage. Table 1 displays 0 for no conductivity and 1 for conductivity of the switches. The remaining switches, such as S4,S3, S8,S7,S12, and S11 illustrated in figure 2, are complementary operations of the switches as indicated above and are shown in table1 as S1,S2,S5,S6,S9, and S10. The operating mode of this configuration is based on NSCHBMLI therefore, the peak output is expressed as equation (1). The following details the configuration’s operating mode: Vopeak = ∞ X n=1 n(n+ 1) 2Vdc.(1) 0Vdc: To achieve zero output voltage level in this mode of operation, either S1,S3,S6,S8,S9, and S11 conduct or S2,S4,S5,S7,S10, and S12 conduct, as shown in Figure 2(d)&2(f) and Table 1(7) mode, respectively. ±1Vdc:S1,S2,S6,S8,S9, and S11 conduct in accordance with the indications in Figure 2(c) and Table 1(6) mode to obtain +1Vdc as the output voltage level. To obtain −1Vdc as the output voltage level, S3,S4, Tab. 1: Operating modes of 13-level configuration Switching Action Mode Voutput S1S2S5S6S9S10 1 1 1 1 1 1 1 +6Vdc 1 0 1 1 1 1 2 +5Vdc 0 0 1 1 1 1 3 +4Vdc 1 0 0 1 1 1 4 +3Vdc 1 0 1 1 1 0 5 +2Vdc 1 1 0 1 1 0 6 +1Vdc 1 0 0 1 1 0 7 0 0 0 1 0 0 1 8 −1Vdc 0 1 0 0 0 1 9 −2Vdc 0 1 1 0 0 0 10 −3Vdc 1 1 0 0 0 0 11 −4Vdc 0 1 0 0 0 0 12 −5Vdc 0 0 0 0 0 0 13 −6Vdc S5,S7,S10, and S12 conduct as shown in Figure 2(f) and Table 1(8) mode respectively. ±2Vdc:S1,S3,S5,S6,S9, and S11 conduct as shown in Figure 2(b) and Table 1(5) mode to reach +2Vdc as the output voltage level. To obtain −2Vdc as the output voltage level, S2,S4,S7,S8,S10, and S12 conduct as shown in Figure 2(f) and Table 1(9) mode respectively. ±3Vdc:S1,S3,S6,S7,S9, and S10 conduct as shown in Figure 2(c) and Table 1(4) mode, in order to produce +3Vdc as the output voltage level. S2,S4,S5,S7, S11, and S12 conduct in the order depicted in Figure 2(j) and Table 1(10) mode respectively, to produce an output voltage level of −3Vdc. ±4Vdc: As illustrated in Figure 2(b) and Table 1(3) mode, the switching pattern for producing +4Vdc as the output voltage level. The conductivity pattern of the switches is depicted in Figure 2(k) and Table 1(11) mode respectively to obtain −4Vdc as the output voltage level. ±5Vdc: Figure 2(a) and Table 1(2) mode, which demonstrate the switching patterns used to provide +5Vdc as the output voltage level, respectively. As illustrated in Figure 2(l) and Table 1(12) mode, the switching pattern used to generate −5Vdc as the output voltage level. ±6Vdc:S1,S2,S5,S6,S9, and S10 conduct in the manner depicted in Figure 2(a) and Table 1(1) mode respectively, to produce an output voltage level of +6Vdc.S3,S4,S7,S8,S11, and S12 conduct as illustrated in Figure 2(h) and Table 1(13) respectively, to produce an output voltage level of −6Vdc. 2.2. Fifteen-Level Configuration This design is a variation on the BCHBMLI, and Figures 2&3 illustrates their ways of switching operation. The configuration used in this instance is a binary one with all voltage source ratings. Similar to the example c 2024 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 38 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 22 |NUMBER: 1 |2024 |MARCH Load S4 S2 S1 S3 S5 S7 S8 S6 S12 S10 S9 S11 V1 V2 V3 - V0 + (a) Load S4 S2 S1 S3 S5 S7 S8 S6 S12 S10 S9 S11 V1 V2 V3 - V0 + (b) Load S4 S2 S1 S3 S5 S7 S8 S6 S12 S10 S9 S11 V1 V2 V3 - V0 + (c) Load S4 S2 S1 S3 S5 S7 S8 S6 S12 S10 S9 S11 V1 V2 V3 - V0 + (d) Load S4 S2 S1 S3 S5 S7 S8 S6 S12 S10 S9 S11 V1 V2 V3 - V0 + (e) Load S4 S2 S1 S3 S5 S7 S8 S6 S12 S10 S9 S11 V1 V2 V3 - V0 + (f) Load S4 S2 S1 S3 S5 S7 S8 S6 S12 S10 S9 S11 V1 V2 V3 - V0 + (g) Load S4 S2 S1 S3 S5 S7 S8 S6 S12 S10 S9 S11 V1 V2 V3 - V0 + (h) Load S4 S2 S1 S3 S5 S7 S8 S6 S12 S10 S9 S11 V1 V2 V3 - V0 + (i) Load S4 S2 S1 S3 S5 S7 S8 S6 S12 S10 S9 S11 V1 V2 V3 - V0 + (j) Load S4 S2 S1 S3 S5 S7 S8 S6 S12 S10 S9 S11 V1 V2 V3 - V0 + (k) Load S4 S2 S1 S3 S5 S7 S8 S6 S12 S10 S9 S11 V1 V2 V3 - V0 + (l) Load S4 S2 S1 S3 S5 S7 S8 S6 S12 S10 S9 S11 V1 V2 V3 - V0 + (m) Load S4 S2 S1 S3 S5 S7 S8 S6 S12 S10 S9 S11 V1 V2 V3 - V0 + (n) Fig. 2: Operating modes of 13-level configuration with (a) V0= +6Vdc, (b) V0= +5Vdc, (c) V0= +4Vdc, (d) V0= +3Vdc, (e) V0= +2Vdc, (f) V0= +1Vdc, (g) V0= 0, (h) V0= 0, (i) V0=−1Vdc, (j) V0=−2Vdc, (k) V0=−3Vdc, (l) V0=−4Vdc, (m) V0=−5Vdc, (n) V0=−6Vdc. c 2024 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 39 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 22 |NUMBER: 1 |2024 |MARCH Load S4 S2 S1 S3 S5 S7 S8 S6 S12 S10 S9 S11 V1 V2 V3 - V0 + (a) Load S4 S2 S1 S3 S5 S7 S8 S6 S12 S10 S9 S11 V1 V2 V3 - V0 + (b) Fig. 3: Two operating modes of 15-level configuration with (a) V0= +3Vdc, (b) V0=−3Vdc. (m-1)/2 -(m-1)/2 Levels ωt α1α2π/2 α(m-2) α(m-1) αm α(m+1) α(3m-1)/2 3π /2 α3(m-1)/2 α(2m-3) α2(m-1) α(m-1)/2 π 2π α(m+1)/2 0 Fig. 4: Multilevel inverter output voltage waveform given above, the ratings for the first H-bridge switch are different from those for the next two. The switching behaviour for various operating modes is shown in Table 2. The peak output voltage of this configuration is indicated as equation (2). It adheres to the same set of circumstances as described in Table 1. Here is an explanation of how the modes of operation transition. Vopeak = ∞ X n=1 (−(1 −2n))Vdc.(2) Tab. 2: Switching modes of 15-level configuration Switching Action Mode Voutput S1S2S5S6S9S10 1 1 1 1 1 1 1 +7Vdc 1 0 1 1 1 1 2 +6Vdc 1 1 0 1 1 1 3 +5Vdc 1 0 0 1 1 1 4 +4Vdc 1 1 1 1 1 0 5 +3Vdc 1 0 1 1 1 0 6 +2Vdc 1 1 0 1 1 0 7 +1Vdc 1 0 0 1 1 0 8 0 0 0 1 0 0 1 9 −1Vdc 0 1 0 0 0 1 10 −2Vdc 0 0 0 0 0 1 11 −3Vdc 0 1 1 0 0 0 12 −4Vdc 0 0 1 0 0 0 13 −5Vdc 0 1 0 0 0 0 14 −6Vdc 0 0 0 0 0 0 15 −7Vdc 0Vdc: As previously mentioned in Table 1(7) mode, the analogous switches are conducted in the same manner for this configuration to achieve zero output voltage level, as demonstrated in Figure 2(g)&2(h) and Table 2(8) mode respectively. ±1Vdc: As previously mentioned Table 1(6) mode, the path it takes is depicted in Figure 2(f) and Table 2(7) mode respectively, for the creation of +1Vdc as the output voltage level. Similar to how Table 1(8) was reproduced in Figure 2(i) and Table 2(9), it is possible to acquire the output voltage level of −1Vdc. ±2Vdc:S1,S3,S5,S6,S9, and S11 conducts are depicted in Figure 2(e) and Table 2(6) mode respectively, for formation of +2Vdc as output voltage level. S2,S4, S7,S8,S10, and S12 conducts are illustrated in Figure 2(j) and Table 2(10) mode respectively, for providing −2Vdc as output voltage level. ±3Vdc: In order to provide the +3Vdc output voltage level depicted in Figure 3(a) and Table 2(5) mode, S1,S2,S5,S6,S9, and S11 conduct, respectively. As demonstrated in Figure 3(b) and Table 2(11) mode, respectively, S3,S4,S7,S8,S10, and S12 conduct in the same way to generate the −3Vdc output voltage level. ±4Vdc: In the same way as Table 1(1) mode was described before, Table 2(4) mode and Figure 2(d) both display the +4Vdc output voltage level. The output voltage level of −4Vdc is produced in the same manner as that described in Table 1(7) mode and is depicted in Figure 2(k) and Table 2(12) mode, respectively. ±5Vdc: It follows the same conduction path pattern as in Figure 2(c) and produces an output voltage level of +5Vdc, which is depicted in Table 2(3) mode. Similar to the conduction pattern exhibited in Figure 2(l), it yields −5Vdc as the output voltage level depicted in Table 2(13) mode. ±6Vdc:S1,S3,S5,S6,S9, and S10 conducts are illustrated in Figure 2(b) and Table 2(2) mode respectively, for formation of +6Vdc as output voltage level. S2,S4, S7,S8,S11, and S12 conducts are illustrated in Figure 2(m) and Table 2(14) mode respectively, for providing −6Vdc as output voltage level. ±7Vdc: The same pattern of the switches’ conduction path, observed in Figure 2(a), is followed and results in the output voltage level of +7Vdc, which is represented c 2024 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 40 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 22 |NUMBER: 1 |2024 |MARCH in Table 2(1) mode. Following the same conduction path as the switches in Figure 2(n), it produces the output voltage level of −7Vdc, which is illustrated in Table 2(15) mode. 3. Mitigation Techniques, Voltage Stress Analysis and Loss Analysis 3.1. Mitigation Techniques The switching angles considered for a quarter wave symmetry is shown in Figure 4. There are 2(m-1) switching angles are expressed in the wave form for an m-level (m is an odd number) output voltage waveform. As seen from Figure 4, switching angles are divided in to four quadrants. The first quadrant (range from 0 to π/2) switching angles are called as main switching angles. By using main switching angles remaining quadrant angles are calculated easily. In First quadrant interval (0-π/2), main switching angles are denoted as α1, α2, ......, α(m−1)/2.(3) In second Quadrant interval (π/2−π), the switching angles are represented as α(m+1)/2=π−α(m−1)/2, ...., α(m−1) =π−α1.(4) In third quadrant interval(π−3π/2), the switching angles are indicated as αm=π+α1, ...., α3(m−1)/2=π+α(m−1)/2.(5) In fourth quadrant interval(3π/2−2π), the switching angles are indicated as α(3m−1)/2= 2π−α(m−1)/2, ...., α2(m−1) = 2π−α1. (6) Equal phase method: The formula (7) is capable of being utilized to create an assessment of switching angles in this method. The switching angles are equally distributed, with an average spectrum of 0-π/2. The number m denotes the generated number of levels. αi=i∗180 m,(7) where i= 1,2,...,(m−1)/2 Half equal phase method: Since the output is too narrow as well as the resulting waveform appears as a triangle in EPM, the HEPM approach has been created to obtain a larger and more effective output from the MLIs. The switching angles in the 0-π/2spectrum are calculated using the formula as follows: αi=i∗180 (m+ 1).(8) Half Height method: Even though the first two methods can smoothly arrange the main switching angles, the output waveform does not look like a sinusoidal. By using this method, the switching angles in first quadrant are estimated depending on the sine function. The theory is that when sine function value raises to half the altitude of the level, the switching angle is positioned, leading to an improved output wave form. The following formula specifies the main switching angles. αi= sin−12i−1 m−1.(9) Tab. 3: Switching angles of thirteen level topology Method Main switching angle α1α2α3α4α5α6 EPM 13.84 27.69 41.54 55.38 69.23 83.07 HEPM 12.85 25.71 38.57 51.42 64.28 77.14 HHM 4.78 14.47 24.62 35.68 48.59 66.44 FFM 2.39 7.23 12.31 17.84 24.29 33.22 Feed Forward method: Unlike other approaches, this method was designed to minimize the difference between the two half cycles of the output waveform, as shown by the equation (10) αi=1 2sin−12i−1 m−1(10) As a result, the main switching angles are effectively obtained for ’m’ number of levels by using four Equations (7)-(10). The calculation of switching angle is independent with respect to other methods as seen from equations (7)-(10). For thirteen level, fifteen level topologies, the main switching angles are calculated based on the four methods and depicted in Table 3&Table 4 respectively. The formula of Modulation Index (MI) in terms of fundamental maximum voltage (Vm) is expressed as equation (11). From equation (12) it seems that modulation index is modified due to the variation of main switching angles respectively. Therefore, depending on the inverter configuration optimized value of MI changes for various main switching angles respectively. MI =Vm V1+V2+..... +Vn ,(11) Vm=4 πV1cos α1+V2cos α2+.... +Vncos α(m−1)/2 (12) c 2024 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 41 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 22 |NUMBER: 1 |2024 |MARCH (a) (b) Fig. 5: Voltage stress of switches for distinct configuration with (a) 13-Level, (b) 15-Level. Tab. 4: Switching angles of fifteen level topology Method Main switching angle α1α2α3α4α5α6α7 EPM 12 24 36 48 60 72 84 HEPM 11.25 22.5 33.75 45 56.25 67.5 78.75 HHM 4.10 12.37 20.92 30.00 40.01 51.79 68.21 FFM 2.05 6.18 10.46 15.00 20.00 25.89 34.10 Tab. 5: Calculated %THD of 13-level and 15-level configurations Mitigation Method %THD 13-level 15-level EPM 20.26 18.84 HEPM 18.61 17.54 HHM 6.35 5.5 FFM 21.15 20.67 Theoretical calculation of THD: By using the equation (13) Total Harmonic Distortion (THD) is calculated. Where P is the switching angle count and αis the main switching angle respectively. For example, in case of 13-level inverter P becomes 6 and the first term of numerator changes as π2∗36/8. The remaining two terms is expressed as equation (14) & (15) respectively. Using Table 4 the main switching angles for thirteen level configuration for individual method using equation 14 %THD is calculated. In the same fashion for other suggested configuration, THD formula is expressed. For all the four methods %THD calculated value is expressed in table 5 3.2. Voltage Stress Analysis Maximum voltage stress of complementary switches has identical magnitudes. The maximum voltage stress of devices is expressed as (16), (17), and (18). Vs1=Vs2=Vs3=Vs4=Vdc,(16) Vs5=Vs6=Vs7=Vs8= 2Vdc,(17) Vs9=Vs10 =Vs11 =Vs12 = 3Vdc.(18) where VSn represents peak voltage of switch when it is turn-off. For this structure, the total standing voltage (TSV) is denoted as equation (19) TSV = 4 ∗(Vs1+Vs5+Vs9) = 24Vdc.(19) The proportion of sum of switch turn-off voltages to peak voltage seems through the load is TSV (p.u.). It is 4p.u. in present state for the proposed topology. Figure5 portrays a bar chart demonstrating voltage stress of individual switching device. At this instance for 13level configuration TSV (p.u.) is 4. Considering identical approach for 15-level configuration voltage stress and TSV are calculated. TSV (p.u.) is identical to 13level for 15-level configuration. For 13-level configuration blocking voltage of switches depicted as bar chart shown in Figure 5(a). From Figure 5(a), at +6Vdc level S1,S2,S5,S6,S9and S10 switches are conducting and remaining switches are appeared as a nonconductive element. As a result, the blocking voltage of switches S3and S4is 1Vdc,S7and S8are 2Vdc, and S11 and S12 is 3Vdc, respectively. Figure 5(a) depicts the blocking voltage of switches for a 13-level configuration in the same way that it does for other modes of operation. In similar fashion for 15-level configuration depicted in Figure 5(b). 3.3. Loss Analysis Switching and conduction losses are different types of power losses experienced by switching devices. Conduction losses are brought on by on-state resistance c 2024 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 42 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 22 |NUMBER: 1 |2024 |MARCH THD = v u u t π2p2 8−π 4p−1 P i=0 (2i−1) αi−p P i=1 cos αi2! p P i=1 cos αi,(13) 2ndterm =π 4(α1+ 3α2+ 5α3+ 7α4+ 9α5+ 11α6),(14) 3rdterm = cos α1+ cos α2+ cos α3+ cos α4+ cos α5+ cos α6.(15) while switching losses are a result of delays in the switch’s on/off processes. It is possible to express the switching loss during the turn-on process as Pswlturnon(i) = fcarrier Zton 0 v(t)i(t)dt =fcarrier Zton 0Vswoff,i ton (ton −t)ion,i ton tdt =1 6fcarrier ∗Vswoff,i ∗ion,i ∗ton,(20) Pswlturnoff (i) = fcarrier Ztoff 0 v(t)i(t)dt =fcarrier Ztof f 0Vswoff,i toff tioff,i toff (toff −t)dt =1 6fcarrier ∗Vswoff,i ∗ioff,i ∗toff .(21) where Pswlturnon(i),Pswltunoff (i)and Vswoff denotes the ith switch’s turn on, turn off loss, and off-state switching voltage, respectively. Currents during the switch’s onand off-states, respectively, are called Ion and Ioff . Total switching losses (Psw) are calculated by summing turn-on and turn-off losses. Psw(Total) = Nsw X i=1   XNon(i) j=1 Pswlon (ij) +XNoff (i) j=1 Pswloff (ij)  (22) where Nswis the total number of switches of the proposed MLI. Conduction losses are appeared in a switch during the conduction period due to on-state resistance and voltage drop across the switch. Generalized equation for conduction losses of diode and switch as follows PDcon =VDon ∗iDavg +RDon ∗i2 Drms (23) Pswcon =Vswon ∗iswavg +Rswon ∗i2 swrms,(24) where PDcon and Pswcon are diode and switch conduction losses, VDon and Vswon are on-state voltage drop of diode and switch respectively. RDon and Rswon are on-state resistances of diode and switch, iDavg,iswavg, iDrms and iswrms are average and RMS currents of switch respectively. 4. Results & Discussion 4.1. Simulation Results All the suggested configurations in the simulation are developed and simulated in an open-loop architecture employing the simulation tool MATLAB/Simulink. In the beginning, the switching angles of all techniques is determined related to first quadrant, and then the associated angles for the remaining quadrants estimated utilising quarter-wave symmetry estimations. Subsequently acquiring all switching angles for each cycle using the respective method, the corresponding switching time for each of the switching angles during that period is calculated numerically. At this instance, for 13-level configuration entirely 24 switching angles must be computed implying that 24 switching times accumulate using aforementioned methods for a cycle duration 50Hz. The switching modes as well as time have been implemented to operate in a manner if there is a absence of gate pulse, it represents as null output that corresponds to zero switching. Topology and modulation make sure zero switching at the beginning and intermediate points concerning positive cycle as well as negative cycle. A standard grid filter is intended for ensuring the feasibility of the suggested asymmetrical configurations for integration into the grid since the resultant voltage is stepped wave thereby rendering it pure sinusoidal when the system is of open loop. This approach is additionally employed for further research with RL loads in order to make sure the reliability of the suggested inverters. In simple terms, an ordinary low pass passive T/π filter is built iteratively for frequency of 50 Hz considering equation (25) f=1 π√LC .(25) It ought to be pointed out that distinct THD values related to various modulation index (MI) for all the methods addressed here are capable of being accomplished through modification of dc voltages solely since the switching angles remain unchanged for every c 2024 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 43 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 22 |NUMBER: 1 |2024 |MARCH Fig. 6: Switching pulses for 13-level configuration Fig. 7: Outputs of each bridge for HHM (13-level configuration) (a) (b) (c) (d) Fig. 8: Output Voltage and current for 13-level configuration with (a) R-load, (b) Various load scenarios, (c) Distinct RL-loads, (d) Change of source voltages. c 2024 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 44 POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 22 |NUMBER: 1 |2024 |MARCH Tab. 6: Comparison of Distinct 13-level Configurations Parameters [28] [29] [30] Proposed NLevels 13 13 13 13 NSw 15 16 12 12 TSV 6 5 6 4 H-Bridge No No No No Modulation NLC NLC NLC HHM Scheme Pswloss Low Low Low Low THD Medium Medium Medium Low Tab. 7: Comparison of Various 15-level Configurations Parameters [25] [26] [27] Proposed NLevels 15 15 15 15 NSw 16 14 12 12 TSV 6 5.5 5 4 H-Bridge No No No No Modulation NLC Hybrid LSPWM HHM Scheme Pswloss Low Medium High Low THD Medium Medium High Low 5. Comparison In this section, distinct MLI configurations related to thirteen level and fifteen level are presented in Table 6 and Table 7 respectively. The configuration in [28] requires 15 switches and operating scheme is NLC. In [29], the switches count is 16 and in similar to [28] it also operates utilizing NLC scheme. In [30] switches count is in same fashion as proposed and operating scheme is NLC. In comparison to other methods HHM provides minimum switching loss as well as THD. Coming into fifteen level configurations [26] working on hybrid methodology (combination of HF scheme and LF scheme) and count of switches is 14. The functioning of configuration [27] is related to HF scheme and switches count is 12. Due to HF scheme losses are more than LF scheme and it is also related to working application. [29] needs 16 switches and control methodology is NLC. In contrast to other configurations proposed asymmetric configuration provides optimized results. 6. Conclusion The recommended Cascaded bridge inverter utilizing asymmetrical operation presents anchored switching devices along with all three dc sources to produce output voltage patterns employing thirteen and fifteen levels. The present study built a simple control as well as modulation approach employing a mathematical switching method. By using PLECS software total losses are measured. In addition, the suggested configuration has reduced conduction and switching losses for accomplishing unique criteria in terms of cost factors and effectiveness. Likewise, the modified module using each kind of uneven dc sources, the suggested cascaded bridge structure can be implemented for distinct levels. Furthermore, THD in the proposed inverter output is minimum, as IEEE 519-2014 specifications. For HHM, optimized switching angle computation have been achieved by using numerical and simulation analysis, along with in the HIL approach for all the configurations. In relation to other methods, the simulation outcomes demonstrate the fact that HHM encounters lowest THD. Moreover, HHM exhibits highest RMS with precise variations in maximum output voltage along with current. Generally, photovoltaic panels through appropriate control methods are capable of being incorporated with the proposed topology for showing execution of grid either in on or off issues via an effective layout. Author Contributions The authors equally contributed in the present research, at all stages from the formulation of the problem to the final findings and solution. References [1] . J. Rodríguez, J. S. Lai, and F. Z. Peng, “Multilevel inverters: A survey of topologies, controls, and applications,” IEEE Transactions on Industrial Electronics, vol. 49, no. 4, pp. 724–738, Aug. 2002, DOI: 10.1109/TIE.2002.801052. [2] S. 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Expo., 2019, pp. 6224– 6230, DOI: 10.1109/ECCE.2019.8912869. [30] J. Zeng, W. Lin, D. Cen, and L. Junfeng, “Novel K-type multilevel inverter with reduced components and self-balance,” IEEE J. Emerg. Sel. Topics Power Elect., vol. 8, no. 4, pp. 4343–4354, Dec. 2020, DOI: 10.1109/JESTPE.2019.2939562. About Authors Lakshmi PRASANNA (corresponding author) was born in Rajahmundry, India. She received her B.E. and M. Tech from Andhra University and VJTI in 2008 and 2010, respectively. Presently she is working as a Research Scholar at Andhra University, Visakhapatnam. Her research interest includes Multilevel inverters, Electric Drives and Electric Vehicles. Jyothsna. T.R. was born in Visakhapatnam, India. She received her M. Tech and Ph.D. from Andhra University, Visakhapatnam in 1997 and 2012 respectively. Presently she is working as a Professor in the Department of Electrical Engineering, Andhra University, Visakhapatnam. Her research interest includes Double fed Induction Generator (DFIG), Optimization techniques, Multilevel inverters, Electric Drives and Electric Vehicles. c 2024 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 53