Diseño de circuitos analógicos y de señal mixta con consideraciones de diseño físico y variabilidad

UNIVERSIDAD DE SEVILLA Departamento de Electrónica y Electromagnetismo Diseño de circuitos analógicos y de señal mixta con consideraciones de diseño fisico y variabilidad TESIS DOCTORAL Memoria presentada por Antonio Toro Frías para optar al grado de Doctor Directores Rafael Castro López Francisco V. Fernández Fernández UNIVERSIDAD DE SEVILLA Departamento de Electrónica y Electromagnetismo Diseño de circuitos analógicos y de señal mixta con consideraciones de diseño fisico y variabilidad TESIS DOCTORAL Memoria presentada por Antonio Toro Frías para optar al grado de Doctor Directores Rafael Castro López Francisco V. Fernández Fernández Acknowledgements Me gustaría mostrar mi agradecimiento a todos los que me han ayudado durante mi camino hasta acabar este trabajo. Sin su ayuda y sobre todo sin su apoyo no habría conseguido llegar hasta aquí. A mis directores Rafa y Paco, junto a Elisenda, por su apoyo durante estos años, por todo lo que he aprendido a su lado y por su paciencia. Junto a ellos, a los demás “platform”, Reinier y Manu, hacer la tesis a vuestro lado siempre fue más fácil, fue una suerte trabajar juntos. A mis compañeros de despacho, en especial en los tiempos del PA34. Al resto de personal del IMSE que de alguna manera me ha ayudado durante este tiempo, con sus palabras de ánimo y sus sabios consejos. Agradecer infinitamente el apoyo de mi familia, en especial por el apoyo y el ánimo, especialmente en los malos momentos, que me han ayudado a llegar hasta aquí, gracias papa, gracias mama. A mi hermana, futura ingeniera. Por último, gracias a Elisabet, por estar a mi lado durante estos años, por, al menos, intentar entender algo de lo que hay en este trabajo, gracias por tu apoyo, contigo este tiempo ha sido más fácil. Gracias. A mis padre y mi hermana . . . A Eli . . . To my parents and my sister. . . To my future wife . . . xvi List of figures 2.12 Binary tree of the layout template of the op-amp circuit. ............ 35 2.13 Layout template programmed in a pCell. .................... 36 2.14 Variables defined for resistors R1 and R0 (blocks A and C). ........... 37 2.15 Test bench circuit. ................................ 39 2.16 Traditional optimization flow .......................... 42 2.17 POF generated with a non-LA optimization. .................. 44 2.18 G-LA sizing examples. ............................. 45 2.19 G-LA POF with AR∼1.0............................. 46 2.20 Examples with AR∼1.0............................. 46 2.21 non-LA-POF and simulation using GCModule with AR∼1.0.......... 47 2.22 Non-LA POF+(G-LA). Projections of the objectives on 2D planes. ...... 48 2.23 G-LA POFs generated with different values of AR ............... 49 2.24 Geometry-Aware POF generated with different AR. Projections of the objectives onto 2D planes. ................................. 50 2.25 Examples with AR∼0.25............................. 51 2.26 Examples with AR∼4.00............................. 51 2.27 LA POFs using different values of AR. ..................... 52 2.28 Comparison G-LA vs LA. AR=1.0 ....................... 53 2.29 Comparison G-LA vs LA. AR=0.25 ....................... 54 2.30 Comparison G-LA vs LA. AR=4.0 ....................... 54 2.31 Layout-Aware POFs with a maximum available area. ............. 55 2.32 Layout-Aware POFs with a maximum available area. Projections of the objectives on 2D planes. ............................... 56 3.1 Different areas defined in a template-layout. .................. 62 3.2 Trade-off between area and power. ....................... 64 3.3 Different area metrics in the POF obtained. .................. 64 3.4 Different ratios in the POF obtained. ...................... 65 3.5 Different ratios and Alost in the obtained POF. ................ 65 3.6 Layout with highest(right) and lowest (left) value of Rminimum in the generated POF. ....................................... 66 3.7 Different ratios and Alost in POF with AR∼1.0.................. 67 3.8 Different ratios and Alost in POF with AR∼4.0................. 68 3.9 Layout with highest(right) and lowest (left) value of Rminimum in the POF with AR∼1.0..................................... 69 List of figures xvii 3.10 Layout with highest(up) and lowest(down) value of Rminimum in the POF with AR∼4.0..................................... 70 3.11 Example of the information about metrics in the basic blocks of a layout template 71 4.1 Diagram flow of the POF-based Layout-Aware with a library of templates implementation. ................................. 75 4.2 Configuration file used by MASSA. ....................... 76 4.3 Basic block description file used by MASSA. .................. 76 4.4 Template 1 description. .............................. 77 4.5 Binary tree of the layout Template 2. ...................... 78 4.6 Template 2 description. ............................. 79 4.7 Binary tree of the layout Template 3. ...................... 79 4.8 Template 3 description. ............................. 80 4.9 Binary tree of the layout Template 4. ...................... 80 4.10 Template 4 description. .............................. 81 4.11 Binary tree of the layout Template 5. ....................... 81 4.12 Template 5 description. ............................. 82 4.13 DC-gain/Area POF obtained for Case Study 1. ................ 83 4.14 Individuals re-evaluated using all layout templates. .............. 84 4.15 Examples of layout obtained using a library of templates. ........... 85 4.16 Analysis of the ratio Rminimum. ........................ 86 4.17 Different ratios and Alost in the POF obtained in the Case Study 1. ...... 86 4.18 pm/fu POF obtained using a library of templates. ................ 87 4.19 Analysis of the ratio Rminimum in the fu/pm POF. ............... 88 4.20 Analysis of the ratios and Alost in the fu/pm POF. ............... 88 4.21 POF A generated using geometric constraint 225µmx100µm. ........ 89 4.22 POF B generated using geometric constraint 150µmx150µm. ........ 89 4.23 POF C generated using geometric constraint 100µmx225µm. ........ 90 4.24 Different geometric constraints POFs. Projections of the objectives. ..... 90 4.25 Analysis of the ratio Rminimum using different geometric constraints. ..... 91 4.26 Analysis of the ratios in the POF C. ....................... 91 5.1 Distribution of defects ( Dde f ect ) at Vgb =1.2V , Vdb =0V and temperature T=25◦C. ..................................... 96 5.2 Temperature dependence of the time constants for a pMOS ........... 97 xviii List of figures 5.3 Dependences of time constants with the gate and drain voltage for a pMOS transistor .................................... 98 5.4 Probabilistic defect occupancy (pocc) with Vgb=0.7V during 1000s. . . . . . 100 5.5 Block diagram of the basic reliability simulation flow. ............. 104 5.6 Example of pocc after 1s, 103s and 107s. .................... 104 5.7 Shifting the distribution of defects to extrapolate the aging. .......... 105 5.8 Stretching the stress waveform until the next intermediate step .........107 5.9 A set of pocc generated using different frequencies ...............107 5.10 Flow A: the SV and TDV samples are aged separately. ............ 108 5.11 Flow B: each SV sample is aged separately using a random TDV sample in each intermediate step (only one SV sample is shown). ............ 109 5.12 (a) Flow C.1 and (b) Flow C.2: each SV sample is aged separately trying to not lose information about TDV (only one SV sample is shown). ....... 110 5.13 ∆Vth generated using 100 samples of TDV with and whitout collapsing pocc). 110 5.14 ∆Vth obtained using simulation flows B, C.1and C.2.............. 112 5.15 Flow D: the mean values of SV and TDV samples are used in each intermediate step. ....................................... 113 5.16 3-stage current mirror used to compare the proposed simulation flows. . . . . 113 5.17 CDF of the copy factor of the 3-stage current mirror. ............. 114 5.18 Different options to update the stress conditions through multiple steps: linear scale (above) or logarithmic scale (below). .................. 116 5.19 Illustration of intermediate steps for a single transistor. ............ 118 5.20 Selection of intermediate steps for a fixed number of steps. .......... 120 5.21 Evolution of the threshold voltage shift and stress conditions in the input transistor in a pMOS current mirror. .......................121 5.22 Relative error in the threshold voltage shift versus the number of steps. . . . . 122 5.23 Schematic of a two-stage Miller op-amp .................... 122 5.24 Relative error against number of steps in the calculation of the performances of the circuit for different scales. ........................ 123 5.25 Number of steps used versus maximum deviation in threshold voltage Vth.. . 124 5.26 Diagram used to calculate the circuit lifetime. ..................127 5.27 Example 1 of lifetime calculation. ........................127 5.28 Example 2 of lifetime calculation. ....................... 128 5.29 Simulation flow implemented in CASE. ..................... 129 List of figures xix 5.30 Circuit section in the input file where a current mirror is defined. ....... 130 5.31 Subcircuit automatically generated by CASE using the circuit defined in Figure 5.30. ..................................... 130 5.32 MonteCarlo section in the input file where a current mirror is defined. . . . . . 131 5.33 File automatically generated using CASE with information defined in Figure 5.32. 131 5.34 Performance section in input file. .........................131 5.35 Output file example. ............................... 132 6.1 The modified version of the evaluation process of NSGA-II to optimize the circuit lifetime. ................................. 139 6.2 Lifetime-aware POF. .............................. 143 6.3 Lifetime versus design objectives: DC-gain and unity gain frequency. . . . . 143 6.4 POF obtained using 100, 200 and 400 individuals. .............. 144 6.5 Lifetime versus design objectives in the three case studies. .......... 145 6.6 DC-gain versus unity gain frequency in the three case studies. ........ 145 6.7 Illustration of individual representation metric for Reliability-aware optimization. 147 6.8 Modifed version of NSGA to generate reliability-POF. ............. 148 6.9 Example of the generation of the new population using the new modified process. 151 6.10 Reliability-Aware POF. ............................. 153 6.11 .Yield versus circuit performances ....................... 154 6.12 Pareto Optimal Front generated adding the yield as an objective to be maximized. 155 6.13 Comparison of the yield versus circuit performances when the yield is an objective or not. ................................. 155 6.14 Comparison of circuit performances with and without TDY(t=Tli f etime) as an objective. .................................... 156 6.15 Number of fronts and individuals in the front 1 in each generation using the Yield as an objective. ...............................157 6.16 Evaluations used in each child population. ....................157 6.17 Pareto Optimal Front generated using different representative metrics. . . . . 159 6.18 Comparison of the TDY(t=Tli f etime) versus circuit performances using different representative metrics to drive the optimization. .............. 159 6.19 Circuit performances obtained using different representative metrics. . . . . . 160 6.20 Pareto Optimal Front generated using different number of individuals. . . . . . 161 6.21 Circuit performances generated using different number of individuals. . . . . . 161 6.22 Pareto Optimal Front generated using different constraint for yield. ...... 162 xx List of figures 6.23 Circuit performances generated using different constraint for yield. ...... 163 6.24 Circuit performances generated using different constraint for TDY(t=5years).164 List of tables 2.1 Slicing tree and devices of the op-amp in figure 2.12. ............. 35 2.2 Design variables. ................................ 38 2.3 Constraints. .................................... 41 2.4 Design objectives or additional constraints. ................... 41 2.5 CPU time per individual. ............................. 57 3.1 Values of different ratios. ............................ 65 3.2 Values of different ratios in population with AR∼1.0.............. 68 3.3 Values of different ratios in population with AR∼4.0.............. 69 4.1 Description of the basic blocks used. ....................... 77 4.2 Design variables. ................................ 83 4.3 Individuals in the POF and results of the re-evaluation using other templates. 85 4.4 Number of individuals that use each layout template with the different geometric constraints. ................................... 89 5.1 Parameters of the defect distribution ( Dde f ect ) at Vgb =1.2V , Vdb =0V and temperature T=25◦C. ............................... 97 5.2 Parameters for the dependences with stress conditions for pMOS transistor. . 99 5.3 TDV characteristics values obtained from different SV samples. .........111 5.4 Comparison of proposed simulation flows. ................... 114 6.1 Typical IC reliability requirements. ....................... 135 6.2 Design constraints used for Lifetime-aware optimization. ........... 142 6.3 Individuals evaluated on each different evaluation step. ............ 158 Chapter 1 Introduction 1.1 Motivation Advances in microelectronic technology has been based on an increasing capacity to integrate transistors, moving this industry to the nanoelectronics realm in recent years. Moore’s Law [ 1 ] has predicted (and somehow governed) the growth of the capacity to integrate transistors in a single IC. Nevertheless, while this capacity has grown steadily, the increasing number of design tasks that are involved in the creation of the integrated circuit and their complexity has led to a phenomenon known as the `` design gap ´´ . This is the difference between what can theoretically be integrated and what can practically be designed. Since the early 2000s, the International Technology Roadmap of Semiconductors (ITRS) reports, published by the Semiconductor Industry Association (SIA), alert about the necessity to limit the growth of the design cost by increasing the productivity of the designer to continue the semiconductor industry’s growth. Design automation arises as a key element to close this ”design gap”. In this sense, electronic design automation (EDA) tools have reached a level of maturity for digital circuits that is far behind the EDA tools that are made for analog circuit design automation. While digital circuits rely, in general, on two stable operation states (which brings inherent robustness against numerous imperfections and interferences, leading to few design constraints like area, speed or power consumption), analog signal processing, on the other hand, demands compliance with lots of constraints (e.g., matching, noise, robustness, ...). The triumph of digital CMOS circuits, thanks to their mentioned robustness, has, ultimately, facilitated the way that circuits can be processed by algorithms, abstraction levels and description languages, 2Introduction as well as how the design information traverse the hierarchical levels of a digital system. The field of analog design automation faces many more difficulties due to the many sources of perturbation, such as the well-know process variability, and the difficulty in treating these systematically, like digital tools can do. In this Thesis, different design flows are proposed, focusing on new design methodologies for analog circuits, thus, trying to close the ”gap” between digital and analog EDA tools. In this chapter, the most important sources for perturbations and their impact on the analog design process are discussed in Section 1.2. The traditional analog design flow is discussed in 1.3. Emerging design methodologies that try to reduce the ”design gap” are presented in Section 1.4 where the key concept of Pareto-Optimal Front (POF) is explained. This concept, brought from the field of economics, models the analog circuit performances into a set of solutions that show the optimal trade-offs among conflicting circuit performances (e.g. DC-gain and unity-gain frequency). Finally, the goals of this thesis are presented in Section 1.5. 1.2 Analog design: sources of perturbation As said before, there is a plethora of perturbations that plague the nominal performance of analog circuits. The difficulty in treating these perturbation systematically is one of the reasons for the lag of analog EDA with respect to digital EDA. In this section, a description of three key perturbations (the first two common in all modern integrating technologies and the other gaining importance with today’s scale of integration) are described. 1.2.1 Layout-induced parasitic devices Since the first silicon technology, the presence of parasitic devices in ICs was reported [ 2 ]. A parasitic device is an unwanted element (e.g., resistance, capacitance) which appears in the manufacturing process. Parasitic devices are unavoidable because all materials used in the manufacturing process possess resistive and capacitive characteristics. These parasitics may critically impact the initial intended performance of the circuit (what is known as nominal performance). To avoid this, the parasitics should be taken into account when designing any circuit. For instance, the parasitic capacitances that appear in the transistor 1.2 Analog design: sources of perturbation 3 structure of the inverter in Figure 1.1, can be easily estimated and accounted for during the sizingaof this circuit block. Fig. 1.1 Schematic of an inverter circuit. Strictly speaking, the accurate estimation of device parasitics also requires that the layout phase has been completed. Traditionally, this process takes place after the electrical sizing is completed. Each component and its interconnections are converted into geometric representation of shapes (i.e., the circuit layout) that, when manufactured with the corresponding set of layered materials, will ensure the required functionality of the circuit. As an illustration, the layout of the inverter circuit (Figure 1.1) is shown in Figure 1.2 where a new schematic of this circuit is illustrated with the inclusion of routing parasitic (only resistive elements). Fig. 1.2 Layout of an inverter and its schematic with inclusion of resistive routing parasitics. A very simple design, as that illustrated here, can contain many parasitic elements (in this case, six parasitic resistors due to routing, but also there are parasitic capacitances due to routing and diffusion capacitors in the transistors). In an analog design, the number of parasitic devices can be very high (in the order of hundreds even for small analog blocks such as simple operational amplifiers). Nowadays, different methods can be used to calculate or estimate these a Broadly speaking, sizing refers to the process of assigning values to the fundamental characteristics of the circuit devices, such as the transistor width and length, resistor values and capacitor values. 10 Introduction occupied by the design, as these figures, which are key to the circuit design, rely on low level design details ; (2) it is possible that specifications at lower levels cannot be met and; (3) it is possible that when the top-level system is verified (during the bottom-up portion of the flow), it does not meet the desired specifications. These drawbacks can imply repeating the whole traditional design process, causing a considerable increase of the design time and possibly hampering design closure. Alternative design flows, known as platform-based methodologies [ 27 , 28 ], have been proposed in the literature to overcome these drawbacks. In these methodologies, the feasibility space of lower levels is generated, that is, the complete set of values for the circuit performances that the specifications can take for a specific topology. One of the main advantages of the platform-based methodologies is the reuse because the feasibility space generated for a certain topology can be reused in many cases. Nevertheless, the transmission of the feasibility space through the hierarchy and how this information is generated are two key problems to use this design flow. Moreover, platform-based methodologies still inherit the drawbacks of pure Top-Down design flows (e.g., the flow must go back if any subsystems does not attain the required specifications). Due to these drawbacks, Multi-Objective Bottom-up (MOBU) flows, shown in Figure 1.6, have been proposed [ 33 , 30 ]. Even so, one key elements of MOBU flows that helps reducing the complexity of dealing with entire feasibility spaces is the concept of Pareto-optimal Fronts (POFs). In the following section, this concept will be described in detail and the optimization method used to generate them will be explained. Fig. 1.6 Bottom-Up methodology. 1.4 Multi-Objective Bottom-Up Methodology 11 1.4.1 Pareto Optimal Fronts POFs have been successfully applied to the electrical sizing of analog circuits. For this purpose, multi-objective optimization techniques are used to generate POFs, another improvement towards bridging the design gap in the analog arena. Most problems in nature have several (possibly conflicting) objectives to be optimized. Many of these problems are frequently treated as single-objective optimization problems by transforming all but one objective into constraints or by a cost function. The second option refers to using a single cost function, a simplification made possible by using a weighted sum of the objectives. In analog design, the design problem will usually be multiobjective, and the goal here is to find optimal trade-offs rather than a single solution. The multi-objective optimization problems can be posed as: Minimize  F(x), F(x) = {f1(x),f2(x),..., fn(x)} ∈ Rn subject to  G(x)>0, G(x) = {g1(x),g2(x),...,gm(x)} ∈ Rm where xLi ≤xi≤xUi,i∈[1,p] The vector x is the set of variables and xLi and xUi are their lower and upper bounds. The vectors  F(x) and  G(x) correspond to the objectives to be optimized and the constraints, respectively. This formulation is for an all-minimization problem; if any of the objectives should be maximized, it can be easily transformed, e.g., by simply multiplying it by −1. In this context, Pareto efficiency is a concept of economics with applications in engineering and social sciences. The term is named after Vilfredo Pareto, an economist who used the concept in his studies of economic efficiency and income distribution. In a Pareto efficient economic system no allocation of given goods can be made without making at least one individual worse off. Given an initial allocation of goods among a set of individuals, a change to a different allocation that makes at least one individual better off without making any other individual worse off is called a Pareto improvement. The concept of POF allows reducing the complete feasibility space and thus, to reduce the complexity of dealing with this information, using only the information of the POF. A definition of the concept of Pareto-dominance criterion in a multi-objective optimization problem is that a solution x1 is said to dominate another solution x2 if  F(x1)< F(x2) and fi(x1)<fi(x2) for at least one function fi . This definition is valid when both individuals fulfill 12 Introduction all design constraints. Otherwise, solution x1 is said to dominate solution x2 if x1 violates design constraints to a lesser extent than x2 . The non-dominated set of the entire feasible search space is known as the Pareto-optimal front (POF). These concepts are shown in Figure 1.7, where both objective functions are minimized. Vector xD is dominated by vector xC , but xC is not Pareto optimal because it is dominated by vectors xA and xB . These vectors are non-dominated because no vector dominates them, so vectors xA and xB are Pareto-optimal. The Pareto front is made up by those individuals that are not dominated. Though in figure 1.7 the Pareto front seems to be a continuous frontier, using a multi-objective algorithm, it is actually a discrete set of circuit designs. Fig. 1.7 Basic concepts of a Pareto-Optimal Front. Figure 1.8 shows a feasible search space in a two objectives problem. In this space, four different POFs can be defined depending if the objectives are minimized or maximized. An example of Pareto-Optimal Front of an analog circuit is shown in figure 1.9, in which the objectives to optimize are the DC-gain and the unity-gain frequency. Pareto-optimal fronts are the solution of the so-called Multi-Objective Optimization problems. The algorithms used to solve this type of problems start with a random set of design solutions (known as individuals) and, very much like the evolutionary process in nature, mutate, cross-over and selects new individuals (across a number of generations) to optimize the circuit performance. The goal is to attain the Pareto-optimal front of the circuit: the set of designs with best trade-offs between the conflicting performances. 1.4 Multi-Objective Bottom-Up Methodology 13 Fig. 1.8 Different POFs in the same feasible search space. The use of Pareto-optimal Fronts in the design of analog circuits is presented in [ 30 ], [ 31 ] and [ 32 ]. But these solutions do not include information about the impact of the sources of perturbation. Using the concept of Pareto-Optimal Front and a hierarchical composition of performance models [ 33 ], it is possible to generate the best feasible designs until the system level, as shown in Figure 1.10. It is important to note that if the impact of the sources of perturbations is not included in the POFs used, when the solution is chosen at the system level, the impact of these sources needs to be included in the design of each sub-block. In this process, re-design loops to include these effects can be needed and even the performance of the chosen solution can be degraded. 1.4.2 Optimizer The problem of finding the POF of an analog circuit is a multi-objective optimization problem (MOOP). During the past 15 years, multi-objective evolutionary algorithms (MOEAs) have 14 Introduction Fig. 1.9 Pareto-Optimal Front of an analog circuit. Fig. 1.10 Bottom Up design flow with the use of POFs and Top-Down solution. shown their usefulness for solving multi-objective optimization problems. In the field of analog integrated circuits, they provide a set of feasible solutions for the optimal synthesis and sizing of different kinds of circuits. As in natural evolutionary processes, emergence of new individuals in each generation is a requirement to introduce improvements in the population. For this purpose, these algorithms make use of the mutation and crossover operators that work on already existing individuals. In a multi-objective optimization problem posed for analog circuits, the vector x is the set of design variables (e.g., transistor W and L). The vectors  F(x) and  G(x) correspond to the design objectives to be optimized (e.g., area, DC-gain) and the design constraints (e.g., margin phase >50o ), respectively. This formulation is for an all-minimization problem; if any of the objectives should be maximized, it can be easily transformed, e.g., by simply multiplying it by −1. 1.4 Multi-Objective Bottom-Up Methodology 15 The solution to this problem is a non-dominated set of individuals (i.e., sized circuits), that is, the Pareto front. To solve the optimization problem, the vectors xi are evaluated in  F(x) . In this case, the circuits are simulated to know the value of their design objectives and design constraints. The individuals that attain the design constraints forms the feasible search space. Using the concept of Pareto dominance, the algorithm will try to reach the Pareto-optimal front. The evolutionary algorithm called NSGA-II dwill be used in this Thesis. NSGA II NSGA-II is based on the evolution of a population of individuals, formed by a popsize individuals, through a number of Mgen generations. To generate the first population, a set of steps are used by NSGA-II: •Initialize population: the initial population is generated. The variables of each individual in this initial population are chosen randomly within pre-defined ranges. These ranges must be defined by the designer, so they rely on previous design knowledge. •Evaluate population: using an evaluator, the values of design objectives and constraints is calculated for each individual of the population. If any design constraint is not fulfilled, the constraint violation (CV) parameter is calculated. This parameter is used by NSGA-II to select the best individuals when none of them fulfills the design constraint. For each individual we have to evaluate these functions and, if any of them is less than 0 (note that the definition of these functions forces them to take positive values), its negative value is accumulated in this parameter. •Assign ranking and crowding distance (CD): all individuals are classified into fronts as follows: non-dominated individuals in front 1 (F1), individuals dominated by at least one individual of front 1, are located in front 2 (F2), individuals dominated by at least one individual of front 2 are located in front 3 (F3), and so on; this step is also called rank assignation, rank 1 for F1, rank 2 for F2, etc. The crowding distance (a measure of how well distributed are the solutions in the performance space) is assigned to each individual and it is a measure of the distance between this individual and those which are closest in its front (in each dimension). If individuals do not meet the design constraints, the constraint violation parameter is used to assign the ranking. d NSGA-II is the most widespread multiobjective evolutionary algorithm in the scientific community with very positive results and the source code is available for free. 16 Introduction To generate a new population, the first population is used as parent population. This population is used to generate a new child population and the rest of the process is repeated across Mgen generations as shown in Figure 1.11: Fig. 1.11 NSGA-II internal operation flow. •Selection: The individuals are taken four by four from this parent population. From these four individuals, a tournament is carried out two by two. This tournament consists in, first, a dominance check. If as a result of this check the individuals are non-dominated, then the one with larger crowding distance is selected. •Crossover and mutation: The selected individuals are used to generate new individuals using the crossover operator. Finally, the mutation operator performs random variations on them. This populations is called child population. •Evaluate population: The individuals forming child population are evaluated. •Combination: the child population and parent population are mixed. •Assign ranking and crowding distance (CD): A new rank assignment process and crowding distance are performed to the new population, mixed population. •Fill population: the best individuals of the population are selected to generate the individuals of the first population. First, the individuals are sorted from lowest to highest rank and the individuals with the same rank are sorted by higher crowding distance. The first popsize individuals form the population 1. 1.5 Goals of this Thesis 17 After using this procedure during Mgen generations, the Pareto-Optimal Front is reported in the final population. For that, an evaluator it is needed to obtain the values of design objectives and constraints. 1.5 Goals of this Thesis In this work, several methodologies are proposed to improve the analog designer productivity. These methodologies provide the solutions in form of Pareto-Optimal Fronts, which promote reuse-based design practices and their use in MOBU design flows. To reduce or, at least, minimize the iteration between different design steps, the methodologies proposed in this work combine the use of POFs with the automated inclusion of sources of perturbations, which means each solution in the POF is completely sized and with accurate information about the impact of these sources. For this purpose, a set of design flows based on the use of the optimization algorithm presented in this chapter and different evaluators, similar to that shown in the Figure 1.12, are proposed in this Thesis. Fig. 1.12 Optimization technique using NSGA-II and an evaluator. In Chapter 2, a new design flow is explained in detail, in which the evaluator includes the physical implementation, which allows including the impact of the parasitic elements in the electrical performance. This process avoids iterations between electrical and physical synthesis. In order to improve this methodology, a method to assess the quality of the automated layout generation technique is discussed in Chapter 3. A new design flow including this improvement is presented in Chapter 4. In addition to the impact of parasitic devices, the impact of spatial variability and aging is growing in new technologies, which causes reliability circuit problems in these technologies. To assess this impact, a reliability simulator is proposed in Chapter 5, which can be used as evaluator to include accurate reliability information during the POFs generation. A new design 18 Introduction methodology to generate POF with reliability information provided by this new evaluator, which is a reliability simulator, is explained in Chapter 6. Finally, conclusions are drawn in Chapter 7. Chapter 2 POF-based Layout-Aware Design Flow As mentioned in Chapter 1, the parasitic devices usually cause a degradation of the circuit performance. Traditionally, electrical sizing and layout design have been addressed by trial and error iterations to compensate for the undesirable effects that parasitic devices cause in the electrical behavior. The first logical step towards efficient automation of the design flow is the undertaking, separately, of the automation of electrical and physical phases. To automate the first one, the most usual technique is an optimization engine linked to a circuit performance evaluator (e.g., an electrical simulator). To automate the second, knowledge-based and optimization-based techniques have been reported. The goal in this chapter is to develop a new design methodology that includes accurate information about the impact of parasitic devices in the POF generation. For this, a new evaluation process is proposed to include this source of perturbation automatically. The followings goals are defined: •Avoid iterations. Iterations between layout generation and electrical sizing to compensate for parasitics prevents fast design closure, not only for the time that these iterations add but also to the complexity of tackling the impact of one parasitic among a list of thousands. •Improve synthesis. Analog circuit design requires very specific expert knowledge to be incorporated into the automated synthesis processes to improve the efficiency of the design process. •Reuse. It is important to extend the notion of library-based approaches, and thereby reduce overall design time. In this sense, the use of POFs helps increasing the degree of reusability. 26 POF-based Layout-Aware Design Flow An example of such floorplan style is shown in figure 2.4 (in this example, the channels or spaces between blocks for inter-block routing are not shown). A useful way to describe the slicing floorplan is by representing the hierarchy structure of the slices with an oriented rooted binary tree called a slicing tree, as shown in this figure. Each node specifies whether the slice is horizontal (H) or vertical (V) or a basic building block. Fig. 2.4 Example of a binary slicing tree representation of a slicing-style layout template. Each basic building block has several possible shapes, that is, different values of the pair (width, height). Given an electrical sizing of the devices of the basic block, all possible combinations of geometric parameters (e.g., number of fingers of the transistors) are examined. This process builds up the so-called shape function for each block. Figure 2.5 shows an example of basic block: a differential pair. In this example, the electrical sizing of the transistors (W,H) is the same, but different geometrical parameters have been used, so that the pair have different forms (width and height pair) for each one. An example of shape function is shown in figure 2.6, for a single transistor block. The geometric parameter here is the number of fingers. GCModule selects the combination of geometric parameters to optimize a certain objective function Φ(W,H) (in this case, the area), in two phases. First, shape functions of basic blocks are combined with a modified Stockmeyer’s algorithm that generates a list of pairs (width and height) of all possible solutions. Then, the point in the shape function with minimum area is selected, and if there are more than one solution with equal minimum area, the solution with minimum area loss (i.e., the amount of area that is not used by the devices or the routing lines, as shown in figure 2.7) is selected. 2.3 Implementation of the proposed methodology 27 Fig. 2.5 Differential pair layout with different number of fingers. Fig. 2.6 Shape function example. GCModule has been implemented in C++. In addition, to area and area loss, GCModule can calculate the solution according to certain geometric constraints set by the designer. The geometric constraints that can be defined are: •Aspect ratio . The ratio between circuit layout width and height ( AR =Wtemplate/Htemplate ) can be specified. Due to the fact that it is almost impossible to achieve an exact aspect ratio, an acceptable deviation ( Ear ) can also be defined. The solution in the shape function will be selected according to the inequality: AR−EarleqWtemplate/Htemplate ≤AR +Ear 28 POF-based Layout-Aware Design Flow 1 2 3 4 5 6 7 8 Routing Area loss Power rails Wtemplate Htemplate Fig. 2.7 Area loss example. •Width . The designer can impose maximum and minimum allowable values of the circuit layout width ( Wtemplate ). These values are defined by a predetermined value ( W ) and a margin ( Wm ). The solution have to satisfy the inequation: W−Wm≤Wtemplate ≤W+Wm •Height . In the same way as the minimum and maximum Width, the designer can impose a predetermined height of the layout solution. H−Hm≤Htemplate ≤H+Hm • Simultaneous width and height limit values. Mask generation, parasitic extraction, and electrical simulation To implement the floor-plan sizing and thus generate all masks in order to extract parasitics and then evaluate the circuit performances through electrical simulation, the commercial platform Cadence Design FrameWork II (DFWII) [ 49 ] is used. Among many different functionalities, this design enviroment includes SKILL [ 50 ], a Lisp dialect used as scripting language and parameterized cells (pCell) description language. In addition, Cadence DFWII provides numerous SKILL-function libraries for different tasks, like “open a view type”, “do a Design Rules check (DRC)”, “open a file”, etc. To implement all actions within Cadence DFWII in an automated flow, a SKILL script has been developed, that also communicates Cadence DFWII with the optimization tool and GCModule (this will be explained in detail in Section 2.3.2). The different tasks carried out in Cadence DFWII are: 2.3 Implementation of the proposed methodology 29 •Mask generation using Parametrized Cells (pCells) To automate the layout generation based on templates, a complete library of parametrized cells (differential pair, cascode structure, resistor, capacitor, etc) is needed. A pCell is a flexible layout generator that can be easily programmed and that accepts certain device values (e.g., W, L) and geometric parameters (e.g., number of fingers). A pCell can be as simple as a MOS transistor and as complex as an entire analog system. These pCells have been developed using the SKILL language. The key to SKILL’s power is a large set of library functions that allows to manipulate data structures such as cells, nets, mask information, etc. pCells can be used hierarchically, meaning that a large pCell can contain other smaller pCells •Parasitic extraction Parasitic extraction is the calculation of the parasitic elements in both the designed devices and the required wiring interconnects of an electronic circuit: detailed device parameters, parasitic capacitances, parasitic resistances and parasitic inductances. The major purpose of parasitic extraction is to create an accurate model of the real circuit, so that detailed simulations can emulate actual circuit responses. For each individual, the corresponding SKILL script proceeds as follows in batch-mode b : (1) it opens a database of the layout editor (Virtuoso); (2) it instances the layout template of the circuit under optimization, using an appropriate pCell, and its variables (coming from the optimizer and GCModule); (3) it flattens the layout (it is important to access to the pin names); (4) it extracts all parasitics and saves the extracted view in a new cell; (5) it closes the Virtuoso database. To implement step (4), there are parasitic extraction tools like Diva [ 51 ] and Assura [ 52 ] (although the use of another tool can be easily implemented using SKILL language). In this case, Diva has been used for two different reasons: 1. Automating the parasitic extraction is easier with Diva, thanks to a single SKILL function for this purpose. 2. In contrast to other tools it allows the parasitic extraction without DRC (Design Rule Checking) and LVS (Layout Versus Schematic) test, which represents a time saving (as instances of layout templates should be DRC and LVS-correct by construction). bBatch-mode is the execution of a set of tasks in a program on a computer without manual intervention. 30 POF-based Layout-Aware Design Flow •Electrical simulation To evaluate the circuit compliance with respect to the optimization problem, the value of design objectives and constraints has to be calculated, that is, a simulation of the extracted view is required. For this analog simulation, we use OceanScripting within Cadence DFWII. OceanScripting allows choosing the simulator, the type of analysis required, and allows including SKILL code that permits automating different measures. Besides, it is possible to use it in batch mode, which is very important to automate the design flow. OceanScripting files can contain three different types of commands: – Simulation Set-up . First, the designer specifies the simulator. In this case, we have used Spectre because it works better with the design kit used in the demonstration part of this Thesis (any other available simulator can be use nonetheless). – Simulator Run. The declared electrical analyses are carried out. – Data Access. It is possible to access to the results as well as to perform any calculation on the results using SKILL. Finally, the output information (design objectives, constraints) can be saved to a file. 2.3.2 Communication between the optimizer module and the evaluator module As it has been discussed in a previous section, there are different tools in this design flow. The integration and communication between these tools is key to automate the design flow. Figure 2.8 shows all tools and their communication using scripts and pipes. To communicate Cadence DFWII with external tools (like the optimizer), an efficient communication protocol have been programmed using InterProcess Communications (IPC) SKILL functions. This communication protocol allows running the Layout-Aware flow in full batch mode to enhance automation. To start the flow, Cadence is initialized by using the non-graphic mode, which allows speeding up the layout-aware flow. After this, a single SKILL script is launched. A diagram with the execution thread is shown in Figure 2.9. Cadence DFWII is the parent process, and it launches the optimizer (NSGA-II) as a child process, while the optimizer launches GCModule as a child process to parallelize the execution. While a solution is processed by Cadence DFWII (mask generation, extraction and simulation), this flow allows a parallel 2.3 Implementation of the proposed methodology 31 Fig. 2.8 Full diagram flow of the POF-based Layout-Aware implementation. execution of the GCModule and these internal Cadence processes (that is, while a solution is being extracted and simulated, the GCModule is sizing the floor-plan of the next circuit). Fig. 2.9 Diagram of execution and communication between Cadence and NSGA-II. 32 POF-based Layout-Aware Design Flow This communication protocol is implemented in a SKILL script. The IPC functions allow the parent process (Cadence) to communicate with a child process by writing to the child process’s stdin channel and reading from its stdout channel. This communication is synchronous, and it uses busy-waiting or spinning c . Cadence DFWII checks if a child process is still alive, that is, if the optimizer is running. If the optimizer has finished its execution (that all generations have been completed, or the Pareto-front has been found), Cadence is ended. The scripts that implement the communication between tools were shown in figure 2.8. These scripts allow evaluating each individual from the values of their variables and the contents of the file template.in in which the information generated during the thread of execution is collected. The file template.in is the main file in the process. All information about the circuit, the OceanScripting file and geometric constraints is in this file. In summary, the problem is defined by a set of: variables, design objectives, design constraints, and geometric constraints. With this information, NSGA-II creates a random population formed by Nind (popsize) individuals, and each individual is evaluated. For this, GCModule generates the values of its geometric parameters to minimize the area (attaining the geometric constraints). Within Cadence, the layout is generated and its parasitics are extracted before the electrical simulation of the circuit. NSGA-II uses selection, crossover and mutation operators to generate a new population across Mgen generations. At the end of the evolutionary process, the Pareto-optimal Front is returned. Therefore, the obtained designs are optimized geometrically and they are robust against the impact of parasitics, meaning that the optimized performances already consider the impact of parasitics and there is no need for entering a complex, nonsystematic and time-consuming cycle of iterations to compensate for the damage of these layout parasitics. Following the design flow, the scripts are: 1. The optimizer writes the value of variables in the file var.in. 2. The PERL script interface.pl adds the values of these variables into template.in. The resulting file is called ocean. 3. The shell script run.sh prepares the execution of the GCModule. 4. GCModule collects information on layout slicing structure (its binary tree) and the geometric constraints. c The busy-waiting or spinning is a technique in which a process repeatedly checks to see if a condition is true, such as whether a keyboard input is available 2.4 Case studies 33 First, GCModule reads the number of slices (horizontal divisions), and the number of basic blocks in each slice. Then, GCModule runs the modified version of the Stockmeyer algorithm, in which no horizontal divisions are allowed after a vertical division. Finally, it incorporates the values of the geometrical variables, creating a file called ocean.ocn. 5. The PERL script par_extract.pl gets the values of all variables and creates a file called param.par in order to instance the layout template with Virtuoso. 6. OceanScripting and Spectre perform the evaluation of the individual using the Ocean- Scripting file ocean.ocn. 7. The PERL script interface_meas.pl extracts the values of the design objectives and the design constraints from a file called meas.out written by the OceanScripting. This information is written in a file “obj&con.out” to be read by the optimizer. 2.4 Case studies The circuit block selected to illustrate the POF-based Layout Aware Design Flow is an operational amplifier (op-amp). Op-amps are among the most widely used electronic circuits, being used in a vast array of consumer, industrial, and scientific devices. This is because using op-amps, it is easy to make amplifiers, filters, oscillators, data converters, and more. Mathematical functions like signal addition, subtraction, multiplication, and integration can be easily accomplished. The technological process used to demonstrate the POF-based Layout-Aware design methodology is a 0.35 - µm , 4-metal, CMOS technology. However, this methodology can be applied to any modern technology. Different case studies are presented to show the advantages of the proposed methodology. 2.4.1 Circuit description The schematic of the two-stage fully differential, RC Miller-compensated CMOS operational amplifier is shown in Figure 2.10. In order to stabilize the common-mode voltages at the output nodes a Common-mode Feedback Circuit (CMFB) is required. However, to simplify the optimization process and for the sake of illustration of the methodology, this CMFB circuit will be considered as ideal, as shown in Figure 2.11. The circuit includes a Miller compensation with nulling resistor. The compensation is coupled between the output voltage and the cascode stage. Stability is improved by exploiting 34 POF-based Layout-Aware Design Flow Fig. 2.10 Schematic of the op-amp used in the optimizations. the pole splitting technique, that is, separating the dominant poles. However, the zero introduced by the Miller compensation can interfere, limiting the advantages of the higher frequency pole. To eliminate or move this zero, a nulling resistor is used. Fig. 2.11 Ideal CMFB circuit. 2.4 Case studies 35 Circuit Layout template As discussed previously, a layout template is used to speed up the layout generation required in the flow. The transistors are grouped in different basic blocks, as shown in Table 2.1. The placement is defined in a binary tree shown in figure 2.12. Block Device Variables Geometric parameter Description AR1Rsep,Rwidth,Zvalor zm Folded Resistor BM3,M4,M10,M11 W3,L3,W10,L10 m3, m10 Cascode Structure CR0Rsep,Rwidth,Zvalor zm Folded Resistor DC1Cvalor cx Unit Capacitor EM14 W14,L14 m14 Folded Transistor FM1,M2W1,L1m1 Differential Pair GM15 W14,L14 m14 Folded Transistor HC0Cvalue cx Unit Capacitor IM6,M7,M8,M9W6,L6m6 Cascode Structure JM5,M12,M13 W5,L5,W12,L12 m5, m12 Current Mirror Table 2.1 Slicing tree and devices of the op-amp in figure 2.12. Fig. 2.12 Binary tree of the layout template of the op-amp circuit. Each basic block is a pCell programmed in SKILL, and it has one or more geometric parameters (used to adjust its geometry), as shown in Table 2.1. The values of the variables of each basic block are proposed by NSGA-II and with this information, GCModule calculates the value of each geometric parameter. These values define the points of each shape function 42 POF-based Layout-Aware Design Flow no information about physical implementation is used while in a G-LA design flow, the physical implementation is considered. That is, G-LA allows to include accurate information about the diffusion capacitors in each transistor, due to the implementation of each transistor is known. A second case study is presented, in which the complete Layout-Aware (LA) design flow is used, that is, in addition to the parasitic devices considered in G-LA, the parasitic devices due to the routing are also included during the optimization process. Finally, a third case study is presented using different constraints on the total occupied area. The Pareto-optimal fronts in these case studies have been generated using 100 individuals evolving across 220 generations; these values were set heuristically, by simply checking that no significant evolution took place after such number of generations. 2.4.2 Case study 1: Non Layout-aware versus Geometric-Layout-Aware The first case study intends to compare the results using the proposed Geometric-Layout-Aware flow with a traditional, non-Layout-Aware flow depicted in figure 2.16. As in the design flow explained in this chapter, the operation of this flow is based on an iterative loop involving an optimizer and an evaluator. In this case, it is not necessary any information about layout so the design flow is simpler than the one implemented in this Thesis. Spectre Cadence DFWII NSGA II Fig. 2.16 Traditional optimization flow The electrical synthesis (or traditional optimization) has been implemented using NSGA-II and Spectre (within Cadence DFWII) as optimizer and evaluator respectively. In this process, diffusion capacitors are the only information about parasitics that is added, but the transistors are implemented without multiplicity, that is, using only one finger. 2.4 Case studies 43 As this optimization flow does not take into account accurate information on the layout implementation (as the Layout Aware Design Flow does), it is not possible to know the area in the physical implementation of the circuit. For this reason, it is necessary to use a rough estimation of the area. For this, it is assumed that the occupied area can be, as a first approximation, proportional to the area of the devices. To calculate this area, first, the area of the gate of all transistors is calculated using equation 2.6 and the values for the area occupied by the strips of the resistors and square capacitors are calculated using Technological parameters Rsq =50ΩWe f f =0.35µm Ca=0.86 ·10−3pF Cpp =0.092 ·10−3pF areatr =2·W1L1+2·W3L3+W5L5+4·W6L6 +2·W10L10 +2·W12L12 +2·W14L14 (2.6) areares =Rwidth ·Rvalue ·(Rwidth −We f f )Rsq (2.7) areacap = [(−4·Cpp +q16 ·C2 pp +4·CaCvalue )/(2·Ca)]2(2.8) Finally, the total are is calculated as Area =areatr +areares +areacon (2.9) Using this non Layout Aware (non-LA) multi-objective optimization, a case study is presented, in which, the optimizer has been configured to maximize the DC-gain and the unity-gain frequency (fu) and minimize the area. The additional constraints that have been used in this optimization are the output swing (os >4.0V) and the slew rate (sr >55V/µs). After the optimization, the final population forms a Pareto-optimal front because all individuals are non-dominated and they all fulfill constraints. Figure 2.17 shows this population. If a designer wants to use a circuit design from this POF, the circuit layout needs to be created. Once this is done, the impact of parasitics could be added. However, as it will be shown later, this could mean carrying out several time-consuming iterations to correct the non-desired perturbations. Before illustrating the complete POF-based Layout Aware design flow, an intermediate case study is presented (which will also serve as baseline to contrast the results of the non-LA solution). This case study only considers the geometry aspects of the final layout but not the extracted parasitics due to routing. 44 POF-based Layout-Aware Design Flow Fig. 2.17 POF generated with a non-LA optimization. This flow is called Geometric-Layout-Aware (G-LA) design flow, in which, only the diffusion parasitics are included, albeit with a difference to the non-LA flow: the diffusion parasitics are better calculated since there is precise information on the actual geometry of, for instance, folding of transistors. The use of layout templates and the modified Stockmeyer’s algorithm allows to define geometric constraints in the geometry-aware sizing. With this case study, the goal is to show that electrical sizing together with geometry optimization (i.e., floorplan sizing) is a first step towards full layout-aware (LA) (i.e., geometry + full parasitics) sizing. As a side note, it is worth mentioning an aspect related to the lack of flexibility of templates. The Geometric-Layout-Aware (G-LA) sizing complements the use of the template-based approach with a way to improve that flexibility by finding the most adequate values of the geometric parameters to improve area and area usage. These effects are clearly shown in Figure 2.18. The figure depicts two layouts (generated using GCModule) with the same design variables but different aspect ratios and a layout solution also from the same template with obvious quality differences (the layout on the left occupies much less area and have less area loss). This means that for a layout-aware sizing solution (always requiring a fast and highquality layout generation method), a floorplan-sizing technique is mandatory if the "lack of flexibility" is to be alleviated. Next chapters will show an additional method to further improve the way layout templates are used in the LA design flow. 2.4 Case studies 45 Fig. 2.18 G-LA sizing examples. Using the G-LA sizing, a new POF has been generated with the same design objectives and constraints than in the previous non-LA optimization. The difference from the previous optimization is that the area occupied can be minimized accurately because the physical synthesis is included in the optimization process. In addition, the layout geometry is limited using a geometric constraint for the aspect ratio. In this case, the chosen value is 1.0 with a margin of error of 20% (approximately square geometries). The final population is shown in Figure 2.19 Different examples of individuals which form the POF are shown in Figure 2.20. It is worth mentioning that the area loss (Alost) in this case is very small. To compare this result with the POF obtained previously using a non-LA optimization, the physical implementation of each circuit design obtained in non-LA POF would have to be generated. For this reason, to see what happens if floorplan sizing is carried out for the design whose geometry was not optimized during the electrical sizing, we have used GCModule on these individuals and then, they have been simulated. In addition, GCModule has been configured to generate the layout with the same geometric constraint than in G-LA POF, that is, AR∼1. The results obtained are shown in Figure 2.21 and projections of the results onto the 2D objectives planes are shown in Figure 2.22 to ease its visualization. The area increases noticeably, but this happens because the area used in non-LA optimization is only the area of 46 POF-based Layout-Aware Design Flow Fig. 2.19 G-LA POF with AR∼1.0. Fig. 2.20 Examples with AR∼1.0 the devices, and the area used in individuals plotted in figures 2.21 and 2.22 includes the actual layout implementation. In addition, we can see that the performance in DC-gain and unity gain frequency are slightly better. This improvement comes from the fact the transistors have been folded, which may reduce the diffusion capacitances as well as modify the diffusion resistances (in the traditional optimization, the multiplicities that were used were all equal to 1, which yield very large 2.4 Case studies 47 Fig. 2.21 non-LA-POF and simulation using GCModule with AR∼1.0 diffusion regions for large transistors). For the sake of illustration, the following formula provides the value of the diffusion capacitor when a transistor is folded in mfingers: Cf olded =CA be f ore(m+1 2m)+CP be f ore(mK +W m+1 W+2K)(2.10) ;where: Cf olded: capacitance after doing folding Cbe f ore: capacitance before doing folding CA: capacitance per unit area CP: capacitance per unit perimeter m: multiplicity W: full area of the transistor K: default width of the diffussion region, specified by the technology 48 POF-based Layout-Aware Design Flow Note from equation 2.10 that, if we ignore the perimeter, and use a large value of m, the capacitance can be halved. But although the circuit performances seem to improve when the physical implementation is generated, one important aspect deserve consideration here: all individuals fail to complete all or some constraints, which makes this non-LA POF inadequate to cope with the goal of avoiding iterations between electrical and physical design phases. This means that all individuals in this front should be redesigned in order to meet all constraints. Fig. 2.22 Non-LA POF+(G-LA). Projections of the objectives on 2D planes. 2.4.3 Case study 2: Geometric-Layout-Aware and Layout-Aware In the previous case study, a Geometric-Layout-Aware (G-LA) POF has been used to show the impact of the physical implementation into the design flow. For this, a geometric constraint over the aspect ratio was used. In this section, a new group of case studies are shown in which different values for the aspect ratio are considered as geometric constraints to demonstrate that: • geometric optimization is possible; • different geometric constraints may have an impact on the electrical performance • the template used (with its placement and routing) can have an impact on the quality of the solutions. 2.4 Case studies 49 The design objectives and constraints are the same as in the previous POF generated using the geometric constraint AR ∼1 . In this case, two additional G-LA POF have been generated using two different values for the aspect ratio: 0.25 and 4.0, with a margin of error of 20%. The three final populations are shown in Figure 2.23. As it can be seen, using the same design objectives and constraints but different geometric constraints, the Pareto fronts obtained are very different. Fig. 2.23 G-LA POFs generated with different values of AR To better visualize the impact of the geometric constraint AR on the circuit performances, all possible projections of the fronts onto 2D objective planes are shown in Figure 2.24. In the DC-gain/fu projection, we can see that populations have a similar performance but the population with higher aspect ratio ( ∼4 ) does not get high values for unity-gain frequency. This is due to the fact that transistors implemented in the individuals of this population have a very high value of the multiplicity, which makes the diffusion parasitic capacitors of these transistors larger. On the other hand, individuals in population with a square layout ( AR ∼1 ) have a much smaller area than individuals in other populations. In addition, we can note that Alost is much larger in layouts with aspect ratio ∼0.25 and ∼4 than in layouts with aspect ratio ∼1, which are illustrated in Figure 2.19. For this, different examples of individuals in each new population are shown in Figures 2.25 and 2.26, using an aspect ratio 0.25 and 4.00 respectively. In view of the results obtained, it is demonstrated that the use of the Stockmeyer’s algorithm gives provides a certain degree of flexibility to the layout template. Moreover, using this G-LA sizing technique, it is quite straightforward to note that an optimal geometry (in this case an 50 POF-based Layout-Aware Design Flow Fig. 2.24 Geometry-Aware POF generated with different AR. Projections of the objectives onto 2D planes. aspect ratio close to 1) can make an impact on the circuit performance, due to the strong link between geometry (e.g., number of fingers) and parasitics. This is why any Layout-Aware sizing solution has to deal with both geometry and sizing at the same time. In addition, to evaluate the impact of all parasitic devices, a new group of three POFs have been generated using the full design methodology implemented. These new POFs are called Layout-Aware (LA) POF since the individuals that form them have been evaluated with full Layout-Aware design flow, that is, with full set of parasitics devices (both from diffusion and routing). 2.4 Case studies 51 Fig. 2.25 Examples with AR∼0.25 Fig. 2.26 Examples with AR∼4.00 58 POF-based Layout-Aware Design Flow geometries have an impact on electrical performance and in the quality of the solutions. The first occurs because the number of fingers of the transistors and the length of the routing lines is very different, and hence, the parasitics are very different. The second is due to the use of only one template, which means that the relative placement and routing are fixed, and maybe the same template is not the most adequate for any geometry. In the next Chapter, a methodology to improve this problem is proposed, in order to achieve a POF-based Layout-Aware design flow where the geometry does not limit the performance obtained in the POF generation. With the method proposed in Chapter 3, a new POF based Layout-Aware design flow is proposed in Chapter 4, where the quality of the instance of the layout templates is improved. Chapter 5 A stochastic reliability simulator 5.1 Motivation In addition to the impact of the parasitic devices, as mentioned in Chapter 1, the variability due to the fabrication process and aging has an important impact on the circuit reliability. The impact on the circuit performance caused by process variability has been well studied [ 56 ] [ 7 ] [ 5 ]. Nowadays, commercial and electrical simulators allow evaluating the impact of process variability on the circuit performance during the design process. The mechanisms and effects of transistor aging have been reported in the last decades. To evaluate the circuit reliability in the presence of these effects, different simulators have been proposed in the literature. In this chapter, a new reliability simulator is proposed, which can be used as an evaluator to include accurate reliability information during the generation of POFs. The first reliability simulators were developed during the late 1980s and early 1990s. The most complete of them is the Berkeley Reliability Tools (BERT) [ 57 ] developed at the University of California Berkeley. These tools are a set of methods to simulate the impact of HCI degradation (it should be noted that HCI was the major effect that caused transistor aging in 80’s technological nodes) and to predict the circuit failure due to oxide breakdown and/or electromigration. Later, BTI effects became more important among the aging phenomena and commercial simulation tools were been developed to assess the impact on the circuit performance. In this sense, RelXpert [ ? ], a reliability simulator developed by Celestry (acquired later by Cadence), allows the inclusion of BTI and HCI effects in the circuit performance simulation after a period of full-time operation (called Tfinal or Tage ). Eldo [ ? ], from Mentor Graphics, and MOSRA 94 A stochastic reliability simulator [ ? ], from Synopsys, have similar capabilities. All commercial reliability simulators use deterministic models to include the aging phenomena on the circuit reliability simulation. It is very important to note at this point that all these commercial reliability simulators use deterministic models to include the aging phenomena on the circuit reliability simulation. However, as discussed in Chapter 1, the continuous scaling of CMOS technologies requires traditional deterministic models to be replaced by new ones that account for stochastically distributed failure mechanisms. In this sense, the first stochastic reliability simulator was presented in [ 58 ], in which spatial stochastic reliability effects (i.e., process variability), temporal stochastic reliability effects (Soft Break-down) and temporal deterministic reliability effects (in this case, HCI and BTI) are included. Its simulation flow is based on an iterative application of a deterministic reliability simulator, that is, the stochastically distributed failure mechanisms of aging are not accurately included because a deterministic model for BTI is used. The new tool proposed in this chapter is the first in using a true stochastic model to calculate the transistor degradation together with another stochastic model to take into account the process variability. The stochastic models used to include both sources of variability are presented in Section 5.2. The use of a stochastic model presents, however, fundamental new problems for circuit reliability simulation, for example, how to include two sources of variability, spatial and temporal, or how to implement an efficient simulation flow that spends an acceptable CPU time for reliability simulation of analog circuits. Each of these problems is discussed in Section 5.3, and finally, the simulator is presented in Section 5.4. 5.2 SV and TDV models In this section, the model used to include the spatial variability (SV) and time-dependent variability (TDV) in a reliability simulator are presented. These models will be illustrated with values for its parameter corresponding to a UMC 65 - nm CMOS process. To evaluate the impact on the circuit performances of both stochastic sources of perturbations, a number of samples of the statistical distribution of the variability will be used in the new stochastic reliability simulator. 5.2.1 Spatial variability Process variability and mismatch cannot be removed from the circuit manufacturing process as discussed in Section 1.2.2. For this reason, semiconductor foundries analyze and characterize 5.2 SV and TDV models 95 the device variability for each new technology node. This information is typically provided to designers as model files that can be used by EDA tools for simulation of their circuit designs. These model files allow to carry out a worst-case, corner, or Monte-Carlo analysis, which is the most accepted and well-known technique to accurately know the impact of variability on the circuit performance. In this Thesis, a stochastic SV model is used by the reliability simulator to generate a number of samples of SV to evaluate the impact of SV on the circuit performances. For this purpose, a set of equations has been extracted from the Monte-Carlo UMC 65 - nm file. Using these equations, a number of samples can be generated for the most important transistor parameters threshold voltage (Vth) and mobility (µ) in order to include this information in a Monte-Carlo analysis using the new stochastic reliability simulator. The remaining transistor parameters that are affected by SV (e.g., tox) can be included in the simulation quickly and easily. 5.2.2 Time-dependent variability As mentioned above, deterministic models to calculate transistor degradation have to be replaced by stochastic models due to the stochastic behavior of the aging phenomena in nanometer technologies. In this context, the Probabilistic Defect Occupancy (PDO) model [ 17 ] has been developed in recent years. This approach allows including the stochastic BTI and HCI effects at the same time. The PDO model estimates the transistor degradation as the sum of a permanent component and a recovery component. The recovery component is attributed to the BTI effects, whereas both BTI and HCI effects also cause a permanent degradation. In nanoelectronic circuits, one of the most important degradation mechanisms is BTI, which appears when a gate voltage is applied. BTI produces discrete threshold voltage shifts ( ∆Vth ). This degradation starts relaxing very quickly after the removal of the gate voltage. In addition to this, when a drain voltage is applied together with a gate voltage, the transistor degradation is caused by the combined effect of BTI and HCI. Most reported approaches to evaluate the degradation on the device characteristics assume that the degradation mainly manifests on a threshold voltage variation. In this work, this assumption is kept. Recovery component of the transistor degradation To estimate the recovery component of the transistor degradation, the PDO model emulates the charging/discharging of the different defects that coexist in each transistor channel. Typically, various defects coexist at the same time in the same device and the transistor degradation ( ∆Vth ) 96 A stochastic reliability simulator caused in one device can be calculated as the additive contribution of all the charged defects. Each defect is defined by τc , the time required to capture the charge, τe , the time required to emit the charge and η , the shift produced in the threshold voltage ∆Vth when the defect is occupied. The capture time τc and the emission time τe of each defect are technology-dependent and also depend of the so-called stress conditions, which are given by the voltages applied at the transistor terminals and the temperature. Figure 5.1 illustrated the distribution of defects in the τc - τe space ( Dde f ect(τc,τe) ) for a pMOS transistor, which has been characterized by using the technique presented in [ 59 ]. For a defect, this figure represents the probability of a defect is defined for each pair τc - τe at Vgb =1.2V , Vdb =0V and T= 25◦C . Dde f ect is a bivariate log-normal distribution defined by the mean values of capture and emission times < τc > and < τe >, their standard deviations στc and στe and a correlation coefficient ρ . Table 5.1 shows the parameter used in this work to include the distribution of defects for pMOS and nMOS transistors in UMC 65-nm technology. Fig. 5.1 Distribution of defects (Dde f ect) at Vgb =1.2V, Vdb =0V and temperature T=25◦C. The process of trapping/de-trapping these defects are energy-activated processes, so it is expected that device degradation gets worse at higher temperatures. The relation between τe and τc, and the temperature follows the equation: τ′ e=τe0·eEaτe/(KB·T) τ′ c=τc0·eEaτc/(KB·T)(5.1) 5.2 SV and TDV models 97 Log10] <τe> <τc>στeστcρ pMOS 6.03562 6.56476 5.76383 6.00236 0.8923 nMOS 4.65463 6.00120 6.10030 5.99200 0.8954 Table 5.1 Parameters of the defect distribution ( Dde f ect ) at Vgb =1.2V , Vdb =0V and temperature T=25◦C. where τe0 and τc0 are the capture and emission times at T= 25◦C , Eaτe and Eaτe are parameters related to the energy defect level and the energy band diagram [ 60 ] and KB is the Boltzmann constant. Figure 5.2 shows the dependence of both times with the temperature used in this Thesis. As can be seen in this figure, high temperatures cause the emission and capture times to decrease; this means the trapping/de-trapping processes are much faster and, hence, the transistor degradation is accelerated. Fig. 5.2 Temperature dependence of the time constants for a pMOS In addition to the temperature, the stress conditions are defined by the voltages applied at the transistor terminal. The relationships between the emission and capture times and the gate and drain voltages applied to the transistor are shown in Figure 5.3. When the gate voltage is high, the vertical electric field in the transistor is intense. This causes an increase in transistor degradation because the time needed to capture a charge decreases at the same time that the emission times increase. When a drain voltage is applied, the vertical electric field near the drain is smaller than when Vdb =0a , which leads to an increase of the capture times. In this aPDO model assumes that Vs=Vb. 98 A stochastic reliability simulator situation, the HCI effects appear, increasing at the same time the permanent degradation and the emission times. Fig. 5.3 Dependences of time constants with the gate and drain voltage for a pMOS transistor To know the emission and capture times when different gate and drain voltages are applied to the transistor terminals, the following equations are used: τ′ e=τe0·eβe·Vgb ·eγe·Vdb τ′ c=τc0·Vgb Vre f βc ·eγc·Vdb (5.2) where Vre f is the gate-bulk voltage for which the distribution of defects ( Dde f ect ) has been characterized experimentally and, in this case Vre f =1.2V , and τe0 and τc0 are the capture and emission times at this voltage. The dependence of the emission time with drain voltages and the dependence of the emission time with gate voltage are exponential, however the capture times follows a potential law with gate voltage. This is because when no voltage is applied to the transistor gate, no defects can be charged. Table 5.2 shows the parameters used in this work for the dependencies with stress conditions. Using this information, in the τc - τe space where Dde f ect is characterized, the PDO model calculates the probability for each defect to be occupied, i.e., the probability of occupancy pocc(τc,τe). 5.2 SV and TDV models 99 EaτeEaτcβeβcγeγc pMOS 0.23 0.32 3.43 -8.84 3.54 5.52 Table 5.2 Parameters for the dependences with stress conditions for pMOS transistor. The probability of occupancy, pocc , is calculated with the PDO model using the stress conditions in the each transistor. Using equations 5.1 and 5.2, parameters τ′ e and τ′ c are calculated in the space τc - τe where Dde f ect is defined. When these stress conditions are applied during a time interval ∆t , the probability that a defect defined by τ′ c and τ′ e is emitted ( pe ) or captured (pc) is calculated as: pe=∆t τ′ e pc=∆t τ′ c (5.3) Algorithm 1 is used to calculate the probability of occupancy of each defect defined by τc - τe . If pe and pc are greater than 1, during ∆t the defect could be emitted and captured more than once ( τc,τe<∆t ). In this case, the probability of occupancy for this defect is calculated as the ratio between the number of times the defect could be captured and the sum of the number of times that could be emitted and captured. This equation is valid if only pc and/or pe is greater than 1. Nevertheless, if pc and pe are between 0 and 1, the probability of occupancy for this defect is the sum of: (1) the probability that this defect is already charged ( poccn ) and not being emitted during ∆t , and (2) the probability that this defect is not charged and is captured during ∆t, Algorithm 1 Calculate pocc for a defect defined by (τc,τe)in the time n+1 after ∆t Require: poccn(τc,τe),pe,pc 1: if (pe>1 or pc>1 ) then 2: poccn+1=pc/(pe+pc) 3: else 4: poccn+1=poccn·(1−pe)+(1−poccn)·pc 5: end if 6: return poccn+1(τc,τe) Using Algorithm 1, an example of pocc has been calculated when a transistor is stressed during 105s. with Vgb =Vdb =0.7V and temperature T=25◦C . The probability of occupancy 100 A stochastic reliability simulator ( pocc ) obtained is shown in Figure 5.4. This figure represents the probability that a defect characterized by the pair (τc,τe) is charged when these stress conditions are applied to a transistor. The defects with small capture times and high emission times are charged, shown in red in this figure. On the other hand, the defects with high capture times are discharged, shown in blue. Fig. 5.4 Probabilistic defect occupancy (pocc) with Vgb=0.7V during 1000s. Using the distribution of defects ( Dde f ect ) and the probability of occupancy, pocc , shown in Figures 5.1 and 5.4, and the specific transistor size, a large number of samples of the transistor degradation (  ∆Vth rec ) for each device can be obtained. Algorithm 2 shows how the information generated ( pocc and Dde f ect ) is used to generate a number of samples ( Nsamples ) of the variation of the threshold voltage (  ∆Vth rec ) induced by the recovery component of the transistor degradation. For each sample, the number of defects D that coexist in the transistor is calculated, which strongly depends on the area of the device. First, using the area of the device and the defects density for the technology Ddens , the mean number of defects for this device area is calculated. If the number of defects is very high (larger than Dmax ), that is, if the channel area of the transistor is relatively large, the standard deviation of the recovery component is very small. This is the reason why in older technologies, where the area of the devices is larger than in sub 90nm technologies, the transistor degradation could be modeled deterministically. If the mean value of the number of defects is less than Dmax , a Poisson-distributed function is used to generate the number of defects for each sample (line 6 in Algorithm 2). This means that two devices with the same area may not have the same number of defects. Then, the capture 5.2 SV and TDV models 101 Algorithm 2 Calculation of the stochastic recovery component Require: pocc,Dde f ect, transistor sizes (W,L), Nsamples,Ddens 1: i=0 2: Dmean =W·L·Ddens 3: while i<Nsamples do 4: ∆Vth(i) = 0 5: if Dmean <Dmax then 6: D=genNumberDe f ect(Dmean) 7: while j<Ddo 8: j++ 9: [τc,τe] = genDde f ect(Dde f ect) 10: P=random 11: if P<pocc(τc,τe)then 12: ∆Vth(i)rec+ = gen∆V(W·L) 13: end if 14: end while 15: else 16: ∆Vth(i)rec =detVth 17: end if 18: i++ 19: end while 20: return  ∆Vth rec and emission times are generated for each defect using the information of the distribution of defects ( Dde f ect ) (line 9 in Algorithm 2). With the defect defined (knowing its τe and τc ) the probability of occupancy ( pocc ) is used to know if this defect is charged or discharged. If the defect is charged, its contribution η to ∆Vrec th of this sample is generated and added to ∆Vrec th of this sample. This contribution η is exponentially distributed in a set of defects and it is inversely proportional to the area of the device [ 61 ]. Finally, Algorithm 2 generates a vector ∆Vrec th for each transistor where Nsamples of threshold voltage degradation have been calculated. If the transistor degradation can be approximated by a deterministic value, its value detVth is calculated from: detVth =Ddens·<η>·ZZ Dde f ect(τc,τe)·pocc(τc,τe)dτedτc(5.4) 108 A stochastic reliability simulator Ntran = M ∑ i=1 NSV ·(NTDV )i(5.10) where NSV is the number of samples for SV, NT DV is the number of samples for TDV and M is the number of steps. Like in the previous section, a final Monte-Carlo simulation is carried out to obtain the degraded performances of the circuit. The number of samples to carry out the Monte-Carlo analysis is, in this case, NSV ·(NTDV )M . In summary, using Flow A each initial SV sample is considered in the final Monte-Carlo analysis with (NT DV )M samples accounting for TDV. Considering that the minimum value for statistical significance is 30 (both for SV and TDV), that the number of steps M can be between 30 and 100, and that the time for a single transient analysis and to calculate pocc can take at least one second, the minimum time to perform only the transient analyses rises up to 2·1038 years, which means that Flow A , despite being the most accurate one, is incomputable in practice. Fig. 5.10 Flow A: the SV and TDV samples are aged separately. This means that the use of a stochastic model for aging and the intermediate steps required to take into account the bi-directional link between aging and stress conditions to the simulation flow proposed in Figure 5.10 makes this problem unaffordable. A possible solution to improve how the stochastic aging models are dealt with the simulation flow and, thus, make it affordable 5.3 The reliability simulation flow 109 is presented in Figure 5.11. This simulation flow reduces the number of transient analyses by generating just one TDV sample for each SV sample. This flow tries to imitate what would happen in reality, where each SV sample is aged separately; and at each intermediate step, a random sample of the statistical TDV distribution is used to update the stress conditions. Although Flow B avoids the incomputability problem of Flow A, the use of only one sample of the TDV probability distribution at each intermediate step means that a lot of information about the stochastic nature of aging is lost. Using this simulation flow, the total number of transient analyses is NSV ·M and the number of samples generated for the Monte-Carlo analysis is just NSV . Fig. 5.11 Flow B: each SV sample is aged separately using a random TDV sample in each intermediate step (only one SV sample is shown). A new simulation flow is proposed in Figure 5.12.a, which tries to palliate the loss of information caused by using Flow B. In Flow C.1, each SV sample is also aged separately. This means that after an initial transient analysis, one probability of occupancy ( pocc ) is generated for each SV sample. This process provides NT DV samples for the degradation of each SV sample at time T1 . These samples are used to obtain the new stress conditions. This means that NT DV probabilities of occupancy ( pocc ) are now calculated for each SV sample. In this point, unlike in Flow A, these NT DV distributions are collapsed into a single pocc to generate NT DV samples at time T2 (using a single pocc ). Therefore, only NT DV transient analyses are carried out (for each SV sample) at Ti (whereas Flow A needs (NT DV )i at Ti ). It is important to point out that the collapsing process can only be used for TDV but not for spatial variability because the correlation between TDV and SV would be lost. 110 A stochastic reliability simulator Fig. 5.12 (a) Flow C.1 and (b) Flow C.2: each SV sample is aged separately trying to not lose information about TDV (only one SV sample is shown). First, to demonstrate that no information is lost when collapsing pocc between Ti and Ti+1 , Figure 5.13 compares the transistor degradation histograms obtained by using 100 different transient analysis from 100 TDV samples at Tiand then: • generating, at Ti+1 , 100 TDV samples using each pocc obtained with each transient analysis (i.e., 10,000 total samples), or • generating, at Ti+1 , 10,000 TDV samples after collapsing the 100 pocc s obtained from each transient analysis. Fig. 5.13 ∆Vth generated using 100 samples of TDV with and whitout collapsing pocc). 5.3 The reliability simulation flow 111 The mean value and standard deviation differences between the two TDV distributions shown in Figure 5.13 are smaller than 0.1% . Therefore, Flow C.1 does not lose any TDV information at each intermediate step when the obtained probabilities of occupancy ( pocc ) are collapsed into a single pocc . Thus, the number of transient analyses required to carry out this simulation flow is NSV ·NT DV ·M which is quite a big reduction compared with the number needed using Flow A but it still is very high. To further reduce this number while keeping the accuracy of the reliability simulation, a new simulation flow Flow C.2 is presented in Figure 5.12.b. As in the previous simulation flows presented, each SV sample is aged separately, so one pocc is generated for each sample (through a transient analysis). But, unlike in Flow C.1, instead of generating NT DV samples in each intermediate step, the mean value of these samples is calculated as explained in section 5.2.2 (equation 5.4). The mean value is then used as the characteristic that is representing the distribution to obtain the new stress conditions. In this way, only one pocc is generated and the resulting number of transient analysis is NSV ·M . At time instant Tfinal , NT DV samples can be generated using such pocc . This means that NSV ·NT DV samples would be used in the Monte-Carlo analysis. To study the impact of these three simulation flows, Table 5.3 shows the degradation of the transistor in Figure 5.14, obtained from 3 different samples of SV at Tfinal =1 year. In this table, Flow B generates a single TDV sample and Flow C.1 and Flow C.2 generate two almost identical distributions of TDV samples of transistor degradation. The different values of mean and standard deviation reveal the existing correlation between SV and TDV (i.e., different samples of SV yield different shift in the threshold voltage) that comes from the bi-directional link between stress and aging. Simulation flow B C.1 C.2 µ σ µ σ µ σ Units Sample #1 18.1 - 21.20 4.82 21.20 4.83 mV Sample #2 22.6 - 26.24 5.21 26.24 5.21 mV Sample #3 21.0 - 19.86 5.12 19.87 5.12 mV Table 5.3 TDV characteristics values obtained from different SV samples. A reliability simulation of the single transistor configuration shown in Figure 5.14 has been carried out with all three simulation flows presented. The comparison between the different methods is made such that, at Tfinal , the number of samples in the final Monte-Carlo simulation is the same ( 10,000 ) and 50 intermediate steps are used. For this, Flow B uses 10,000 samples 112 A stochastic reliability simulator of SV and generates 1 TDV for each, while Flow C.1 and Flow C.2 use 100 SV samples and generate 100 TDV samples for each. The QQ-plots in Figure 5.14 show the ∆Vth degradation at Tfinal =1 year. In this case, as shown in Figure 5.14(a), Flows C.x obtain similar statistical characteristics, but significantly differ from the results obtained with Flow B. This difference stems from the fact that Flow B uses many more samples of SV. Figure 5.14(b) shows the contribution of TDV to the total ∆Vth variability This QQ-plot shows that TDV distributions derived by the aging model are very similar because all three methods use a relatively high number of SV samples. This means that, for the same number of Monte-Carlo samples at the final circuit evaluation, Flow B would yield better accuracy. Nevertheless, Flow B and Flow C.1 require a high number of transient analyses (in this case, 5·105 ), while Flow C.2 can generate the same number of samples to include in a Monte-Carlo analysis taking much less time (in this case, 5 ·103). Fig. 5.14 ∆Vth obtained using simulation flows B, C.1and C.2. Although the three simulation flows presented allow addressing the problem of the inclusion of a stochastic aging model in a reliability simulator, the CPU time needed is still very high for a single reliability analysis. For this reason, a new simulation flow is proposed that tries to reach the same accuracy level of Flow B while drastically reducing the CPU time. Similar to Flow C.2, where the mean value of the TDV-induced degradation is used, in this new flow, labeled Flow D, the mean value of the SV distribution is used as a characteristic value of the SV distribution. This simulation flow is illustrated in Figure 5.15. Using this approach, the final Monte-Carlo analysis at T= Tfinal is carried out by using different samples of TDV obtained with M transient analysis together with samples generated by SV. This means that, unlike the simulation flows previous presented, the number of transient analysis needed is independent of the number of samples used in Monte-Carlo analysis. Using this simulation 5.3 The reliability simulation flow 113 flow, a single probability of occupancy ( pocc ) is obtained at Tfinal and random TDV samples are generated and included in the Monte-Carlo analyses together with random SV samples. Fig. 5.15 Flow D: the mean values of SV and TDV samples are used in each intermediate step. To compare all four simulation flows described above, a 3-stage current mirror, shown in Figure 5.16, has been used. This circuit is especially sensitive to transistor mismatch caused by both SV and TDV, and the stress conditions are very dependent of the degradation of transistors M1, M3 and M5. Fig. 5.16 3-stage current mirror used to compare the proposed simulation flows. Table 5.4 shows a comparison of the number of transient analysis needed using each simulation flow when 50 intermediate steps are used and Tfinal = 5 years. The cumulative distribution function of the copy factor is shown in Figure 5.17. As it can be seen, the results are very similar between Flow B and Flow D.Flow C.1 and Flow C.2 obtain different performance because the impact of SV samples is quite important. Note that in these simulation flows, each SV sample is used 100 times in the Monte-Carlo analysis while in the other two, each SV 114 A stochastic reliability simulator sample is used just once in the Monte-Carlo analysis (thus increasing the number of SV samples as shown in Table 5.4). Fig. 5.17 CDF of the copy factor of the 3-stage current mirror. As it can be seen in the CDFs, Flow D is quite similar to Flow B, but with far lower CPU time requirements (the number of transient analyses is 10,000 times smaller). Any difference between these two simulation flows is caused by the impact of SV in the bi-directional link between stress and aging, which is not considered in Flow D. Nevertheless, although the bi-directional link between stress conditions and aging is not fully considered in this simulation flow (as far as the influence of SV is concerned), the results can still be accurate simply because Flow D can account for many more SV samples with far less CPU time, and this is because the mean is a sufficiently representative of the SV distribution (to calculate the transistor degradation). Flow NSV NTDV generated for each SV M of transient analysis MC samples B 10,000 1 50 500,000 10,000 C.1 100 100 50 500,000 10,000 C.2 100 100 50 5,000 10,000 D 10,000 1 50 50 10,000 Table 5.4 Comparison of proposed simulation flows. A set of simulation flows has been proposed to deal with an efficient reliability simulator for nano-scale analog ICs, which involves using accurate SV and TDV models. The incomputability of this problem has been addressed by proposing a set of simulation flows. The proposed simulation flows provide a good trade-off between CPU time and accuracy where: 5.3 The reliability simulation flow 115 • Flow B can include the correlation between SV and TDV very accurately, but at the expense of larger computation (from days to years). • Flow C.1 can include the correlation between SV and TDV with a high computation time. In addition, each SV sample is used NT DV times, which can be a problem. • Flow C.2 can include the correlation between SV and TDV reducing the computation time needed, but each SV sample is used NT DV times, which can be a problem. • Flow D can handle a very large number of samples with a reduced number of transient analyses as long as the correlation between SV and TDV is sufficiently weak. For these reasons, even if the correlation between SV and TDV is quite important, the large number of samples involves in the Monte-Carlo analysis in Flow D makes this simulation flow the most convenient in a reliability simulator. 5.3.3 Time-step adaptive algorithm In the previous section, a simulation flow to take into account stochastic models for SV and TDV together with the use of intermediate steps to update the stress conditions has been presented. These stress conditions do change during the period of full-time operation due to the device degradation and, therefore, a number of intermediate step is required. This option is already included in some commercial tools like RelXpert or MOSRA, where these steps may be uniformly distributed along a linear or logarithmic scale, as can be seen in Figure 5.18. Note that a higher number of steps implies a higher computational cost due to the need for new transient analyses and the re-calculation of transistor degradation at each step. However, using intermediate steps by uniformly distributing a user-defined number of them along a linear or logarithmic scale presents some drawbacks. On the one hand, if the number of steps selected is too small, the stress conditions are not correctly updated and accuracy might be lost. On the other hand, if the number of intermediate steps is too high, no new information is provided for these intermediate steps and computation time is, therefore, wasted. Another important drawback of current commercial tools is that these simulators use deterministic, instead of stochastic, models for aging, which is another source for accuracy loss. Another problem when intermediate steps are used is to guess the appropriate size of these steps, beyond linear or logarithmic scales, to improve the accuracy with less steps than using conventional approaches. To solve this problem, a method to maximize the step size while 116 A stochastic reliability simulator Fig. 5.18 Different options to update the stress conditions through multiple steps: linear scale (above) or logarithmic scale (below). guaranteeing the simulation accuracy is proposed in [ 58 ]. For this, a maximum relative shift of each circuit performance is used that cannot be exceeded at each intermediate step. The next step size is calculated with an empirical formula if the limits defined by the designer are not exceeded. If that is not the case, it means that the step size was too large and the step needs to be repeated with a smaller size. This approach then adapts the step size using the circuit performance to maximize its size. However, this approach presents two main drawbacks: • The required computational effort could be very high due to the required performance analysis. When a stochastic TDV is used, this implies an expensive Monte-Carlo analysis. In addition, some step could have to be repeated (which means that a performance analysis would have to be repeated as well). • The decision on the step size is based on the relative shift of the circuit performances rather than on the stress conditions themselves. It is obvious that a change in the circuit performance always involve a change in the stress conditions (and, hence, a new transient analysis is needed), but a change in the stress conditions (only caused by a transistor wear-out) does not always involve a change in the circuit performances. Paying attention only to circuit performances could mean that changes in the stress conditions are not really and always detected and, therefore, accuracy losses could occur. A different solution to this problem has been presented in [ 64 ], based on the aging-induced variation of the threshold voltage ∆Vth . In this solution, the designer defines an interval where 5.3 The reliability simulation flow 117 an accurate aging analysis with a very high number of steps is carried out, and an accurate value of ∆Vth is calculated in this interval. Then, the analysis is repeated but with a larger step size in this same interval. The maximum size is selected as the size where a maximum allowed error, defined by the designer, is still fulfilled. This all means that the adaptation of the step size is really only done at the beginning of the simulation (that is, the size of the step is calculated for every different simulation), but the step size is kept constant during the simulation. This is, in fact, a problem since the initially calculated step size could not be valid for the whole reliability simulation. Moreover, critical decisions are left to the designer, such as the size of the initial interval or how many steps are needed for the accurate reference value. For example, if the first interval is too small, the selected step size will be small and a lot of unnecessary steps could be carried out. In this section, a new algorithm to calculate an adaptive step size is proposed. The target of this algorithm is that the stress conditions can be efficiently updated taking into account that: • The distribution of the steps must be adaptive: the algorithm must self-adapt to the different evolution of aging and stress conditions (in contrast to the fixed scales used by the current commercial tools). • The information required by the algorithm must not depend on user-defined parameters (such as an initial step size) that may drastically impact the efficiency of the reliability simulation. With this aim, the drawbacks of the approach in [64] are avoided. • The algorithm must track changes in the stress conditions, which are always produced by changes in the wear-out of the transistors. However, tracking the stress conditions implies performing a transient analysis with the subsequent CPU load increase. Therefore, using an appropriate aging model, this algorithm tracks the transistor wear-out (i.e., shift in Vth ) which does not require any additional analysis. With this aim, the drawback of the approach in [58] (which tracked circuit performance variations) is avoided. To avoid the drawbacks in [ 58 ] and [ 64 ], the method presented in this Thesis adapts the step size based on the transistor wear-out. The cornerstone of this method is the maximum variation in the transistor degradationc(∆Vth) before updating the stress conditions. An example using a single transistor is shown in Figure 5.19. At each step, the algorithm defines, as an objective, a specific value for the transistor degradation ( ∆Vob jM th ). The step size c Without loss of generality, other parameters like variation in the mobility of the transistor could be included in this algorithm. 124 A stochastic reliability simulator Fig. 5.25 Number of steps used versus maximum deviation in threshold voltage Vth. 5.3.4 Lifetime calculation In this scenario of many variability sources affecting the circuit performance over time, a critical issue is the accurate calculation of the circuit lifetime. To do so, the concept of time-dependent yield ( TDY(t) ) is introduced„ which is defined as the time-varying percentage of designs that fulfill a set of performance specifications or performance constraints at time t . These design constraints are defined by the designer and usually refer to circuit performances (such as keeping the DC-gain of an op-amp greater than a given value) and to operating conditions (for example that a MOS transistor operates in the saturation region). The lifetime of the circuit is then defined as the time that the circuit is operating with a TDY larger than a certain threshold value (for one or more performance specifications or constraints). To calculate the yield of a circuit during the design phase, Monte-Carlo simulation is the most commonly used technique. The yield at time zero is then computed by taking the ratio of the number of Monte-Carlo samples that fulfill constraints to the number of samples that do not fulfill those same constraints. It is reasonable to think that accuracy should be a main factor in calculating TDY and lifetime (so as not ending up with over-design, for instance). However, as with many other design tools and methodologies, accuracy comes at the price of computation time. Therefore, whichever the reliability simulation solution used, efficiency, in terms of low CPU time together with the highest level of accuracy, should be a main focus. To emphasize the importance of being efficient in terms of CPU time, it is important to remark 5.3 The reliability simulation flow 125 that, in most reported solutions for the computation and optimization of lifetime [ 64 , 66 ], a reliability simulation is used iteratively and, hence, called in multiple times, so reducing the CPU load is essential. Though reported solutions for yield and lifetime calculation are based on failure models due the different reliability effects, no published work, to the best of the authors’ knowledge, takes into account the stochastic nature of aging phenomena using a stochastic simulator. Nevertheless, some contributions can be mentioned here. The works presented in [ 66 , 67 ] take into account SV and TDV jointly but, instead of a complete stochastic analysis of the aged distribution of the design, they are only focused on the estimation of worst-case designs (so neither a stochastic distribution of the performance of the circuit at a target time nor the yield is provided). In [ 68 ], a single-objective optimization tool is presented. The lifetime is defined as a new constraint and the reliability simulator is used iteratively to evaluate the design candidates of the solution. However, although yield is defined as a percentage of the designs that fulfill the design constraints in a predefined target time in a similar way that this work does, a deterministic simulator is used, so the calculation of the lifetime does not take into account the stochastic nature of aging. In contrast to the works in the literature, this Thesis focuses on the calculation of the lifetime without introducing any approximation (such as considering only the worst case of a design) to calculate the yield of the circuit during its lifetime. For this purpose, a Monte-Carlo based method to evaluate the performances is required. A trivial solution would be to compute yield and lifetime at each of the M steps of a reliability simulation. However, this can become computationally prohibitive and, therefore, an efficient methodology is required to reach the same accuracy level while improving CPU usage. The simulation methodology to calculate the lifetime is based on the stochastic reliability simulation flow using the adaptive step size algorithm proposed in section 5.3.3. In the proposed solution, to avoid unnecessary calculations, the designer can define a temporal window, setting a minimum time ( Tmin ) and a maximum time ( Tmax ), where the analysis of the lifetime is carried out. To set the adaptive step size algorithm, the designer must define a parameter deltaV to specify the accuracy for the adaptive step size algorithm. Besides, the designer defines, as with a regular simulation, the design specifications or design constraints and the number of samples to carry out the Monte-Carlo analysis ( MC ). To determine the lifetime of the circuit, a minimum TDY ( TDYmin ) is defined, which will be used, at each step of the lifetime calculation, as the value the calculated yield is compared to with. 126 A stochastic reliability simulator The complete flow is depicted in Figure 5.26. As an accurate Monte-Carlo analysis ( ≈1,000 samples) is very time consuming, the designer has then to define the number of samples for an accurate Monte-Carlo, MC , and the reduction factor, K , for a reduced Monte-Carlo analysis. Typically, a value of K between 10 and 50 is used because this is a typical number of steps between Tmin and Tmax . To distinguish both computations, hereinafter two concepts will be used: yield calculation (involving a full Monte-Carlo analysis of MC samples) and yield estimation (with a reduced Monte- Carlo analysis of MC/K samples). Figure 5.26 has then two different parts: on the left, the yield is estimated and, on the right, the yield and the lifetime are calculated. These two different parts consist of: a first one where a reduced number of samples ( MC/K ) is used to estimate the yield at each step ( TDY′ i ), and a second one where the yield is calculated using the defined number of samples by the designer ( MC ) and the lifetime is calculated. During the lifetime calculation, if the estimated yield ( TDY′ i ) is lower than the minimum yield defined (Ymin), a new Monte-Carlo is carry out with the full number of samples (MC). It is important to notice that the lifetime calculation is always done using the number of samples defined by the designer ( MC ) and if the lifetime happens to lie between Tmin and Tmax , at least two Monte-Carlo analysis have been carried out. In that case, it is considered that there is a moment in time Ti where the estimated yield is lower than the minimum yield. Then a complete reliability analysis using MC samples is carried out. If the obtained TDY is lower than the minimum yield defined Ymin (that is, both the estimated value and the calculated value lie below the minimum yield), the yield must be evaluated again in the previous time step Ti−1 using MC samples too. If the obtained yield is larger than the minimum one, it means that the lifetime has been found ( Ti ). On the other hand, if the lifetime is larger than Tmax or lower than Tmin, only one Monte- Carlo is carried out at either point in time. A lifetime reliability analysis has been carried out using the two-stage Miller amplifier defining 0.7 as minimum yield. The moment in time when the yield over time falls below this value, the circuit is considered ”dead” and the lifetime equals that time value. The design constraints to compute the yield are: phase margin >60o , DC-gain >50dB , unity gain frequency >45MHz and all transistors set on their correct operating regime. For the first example, the temporal window is established between 1 month and 20 years. The lifetime time calculated by the simulation flow is 2.395297·107 seconds ( ∼ 9 months and 1 week). Figure 5.27 shows the Monte-Carlo analysis used to calculate the circuit lifetime (red-X if the yield is estimated and blue- X if it is calculated). On the x-axis, the moments in time when the stress conditions have been updated are shown. In this case, Tmin was set to 30 days ( 2.592 ·106 seconds) and for this reason, in the first steps (which have been used to update the 5.3 The reliability simulation flow 127 Fig. 5.26 Diagram used to calculate the circuit lifetime. stress conditions before Tmin ) no Monte-Carlo analysis has been carried out since this moment is not considered in the defined temporal window. Fig. 5.27 Example 1 of lifetime calculation. Another case study is illustrated in Figure 5.28, where the same circuit topology but a different sizing is used. In this case, the lifetime is 3.591648·108 seconds (around 11 years and 4 months). In this case a total of 112 analyses have been needed to estimate the yield and 3 full Monte-Carlo analyses have been carried out to calculate the circuit lifetime. This example is also shown to illustrate the importance of the temporal window. In this example, the CPU-time 128 A stochastic reliability simulator needed is very high, because Tmin is equal to the first case (30 days). If this time were longer (e.g., 1 year), the CPU time would have been drastically reduced. Fig. 5.28 Example 2 of lifetime calculation. These two examples show how the circuit lifetime simulation flow works in different situations, where the lifetime calculated is smaller (first case) or larger (second case) than the estimated. In the first example, when the estimated TDY is lower than the Ymin , the TDY is calculated and it results in a lower value than Ymin. In this situation, the search of the calculated lifetime is carried out backwards in time until the moment that TDY(t)>Ymin is found (which occurs, for the first example, in the previous step Ti−1 ). In the second example, when the estimated TDY is lower than Ymin , the TDY is calculated but, now, the result obtained is larger than Ymin . In this situation, the circuit is not considered ”dead” yet, so the search of the calculated lifetime continues forward until TDY(t)<Ymin, which requires, for this second example, two more steps. 5.4 The reliability simulator CASE This section presents CASE, a reliability simulator based on the approaches presented in the previous section. In addition, the implementation of an efficient and automated simulation flow and the use of a commercial electrical simulator allow to achieve very accurate results with an affordable CPU time (note that once of our goals is to use this simulator as evaluator in an iterative optimization process). The simulation flow is depicted in Figure 5.29, where the use of an off-the-shelf electrical simulator is needed to evaluate the circuit performance. The inputs of the reliability simulator are contained in two separate files: 5.4 The reliability simulator CASE 129 Fig. 5.29 Simulation flow implemented in CASE. •Configuration file. It contains a set of parameters to configure the simulation method, such as the number of samples used in Monte Carlo simulation ( Nsamples ), the time where the variability analysis is done ( Tfinal ) or the mesh where τc - τe are defined, that is the maximum, minimum and grid value where the probabilities of defects occupancy pocc and the distribution of defects Dde f ect are calculated. •Input file. This file contains the user-entered information about the circuit, the simulation test-benches (for the transient and Monte Carlo analyses) and the circuit performance information to be rendered by the simulator. The flow of this reliability simulator begins by reading the input file, and the three files (Sub-circuit, Transient and Monte-Carlo files, as shown in Figure 5.29) are automatically 130 A stochastic reliability simulator generated. The circuit under study is defined in the Sub-circuit file; here, additional devices (such as a voltage source to emulate a threshold voltage degradation ( ∆Vth ) and the parameters to include SV for those devices selected for reliability analysis) are automatically included as shown in Figures 5.30 and 5.31. Transistors whose name begins by “mr” are used in the reliability analysis. In the example in Figure 5.30, a current mirror circuit is defined where transistors m3 and m4 are not included in the reliability analysis. Fig. 5.30 Circuit section in the input file where a current mirror is defined. Fig. 5.31 Subcircuit automatically generated by CASE using the circuit defined in Figure 5.30. The file for the transient analysis to obtain the stress suffered by each selected device, and the file to perform a Monte-Carlo simulation of the aged circuit is also generated and the sub-circuit is automatically included. In addition, these files are prepared to perform a Monte Carlo analysis as shown in Figure 5.33 using the test-bench defined in the MonteCarlo section of the input file defined in Figure 5.32. 5.4 The reliability simulator CASE 131 Fig. 5.32 MonteCarlo section in the input file where a current mirror is defined. Fig. 5.33 File automatically generated using CASE with information defined in Figure 5.32. When the files are generated, at each intermediate step (the first is time zero ( t=0 )), a transient analysis is carried out including the transistor degradation defined in the file Data_var (as shown in Figure 5.29). Finally, at Tfinal , a Monte-Carlo analysis is carried out. For this, the complete variability information is written in the file "Data_var". The circuit performances defined in the input file are read, each performance can be defined as a design constraint as shown Figure 5.34, where P1 has to be greater than X , P2 smaller than Y and P3 has to be greater than 80% of the nominal design value for this performance. Fig. 5.34 Performance section in input file. 132 A stochastic reliability simulator With the simulation method described, it is then possible to carry out a thorough statistical analysis of the aged circuit, with which the designer can accurately assess the reliability of the circuit. Statistical values for each specified performance are calculated as shown in Figure 5.35. In addition, the yield over time or time dependent yield ( TDY(Tfinal) ) is calculated, that is, the ratio of the number of samples that attain the design specification or constraints defined in section performances after a period of full-time operation Tfinal. Fig. 5.35 Output file example. In addition, CASE includes the simulation flow to calculate lifetime automatically. CASE is coded in C language and it is easily used in a automated design methodology due to the possibility of working in batch-mode. 5.5 Summary This Chapter presents a a reliability simulation flow that takes into account the stochastic nature of aging, the joint inclusion of SV and TDV and the much needed update of stress conditions over time. A tool named CASE has been implemented to fully automate that reliability simulation flow. CASE wraps around a commercial simulator to carry out the essential electrical analyses that are needed in the reliability simulation flow. CASE is versatile in the sense that it can carry out these analyses with a variety of options, like, for instance, the use of an adaptive algorithm to set the intermediate steps in time (selecting either a desired accuracy level or a CPU time budget), or the capability to evaluate the impact of either SV, TDV, or both, on the circuit performances at a specified time Tfinal . With the help of CASE, designers can efficiently account for the impact of process variability and aging in the design process. CASE can calculate the circuit performance after a period of full-time operation, calculating the time dependent yield ( TDY ) at this time. In addition, CASE can calculate the circuit lifetime, 5.5 Summary 133 that is, the time when a proportion, larger than a certain threshold ( Ymin ), of the designs stops fulfilling constraints (TDY(t)<Ymin). In addition, the reliability simulation flow and CASE have been developed such a proper trade-off between accuracy and CPU time is achieved. This trade-off is at the base of the adaptive step size algorithm as well as the technique to simultaneously include both statistical distributions of SV and TDV. 170 References [36] P. Vancorenland, G. Van der Plas, M. Steyaert, G. Gielen, and W. Sansen, “A layoutaware synthesis methodology for RF circuits,” in IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281), pp. 358–362, IEEE. [37] M. Dessouky and M.-M. Louerat, “A layout approach for electrical and physical design integration of high-performance analog circuits,” in Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525), pp. 291–298, IEEE Comput. Soc. [38] H. Onodera, H. Kanbara, and K. Tamaru, “Operational-amplifier compilation with performance optimization,” IEEE Journal of Solid-State Circuits, vol. 25, pp. 466–473, apr 1990. [39] M. Ranjan, W. Verhaegen, A. Agarwal, H. Sampath, R. Vemuri, and G. Gielen, “Fast, layout-inclusive analog circuit synthesis using pre-compiled parasitic-aware symbolic performance models,” in Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp. 604–609, IEEE Comput. Soc. [40] R. Martins, N. Lourenco, A. Canelas, R. Povoa, and N. Horta, “AIDA: Robust layout-aware synthesis of analog ICs including sizing and layout generation,” in 2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), pp. 1–4, IEEE, sep 2015. [41] R. Martins, N. Lourenco, S. Rodrigues, J. Guilherme, and N. Horta, “AIDA: Automated analog IC design flow from circuit level to layout,” in 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), pp. 29–32, IEEE, sep 2012. [42] T. Christiansen, L. Wall, J. Orwant, and B. D. Foy, Programming Perl. O’Reilly, 2012. [43] B. W. Kernighan and R. Pike, “Using the shell,” in The UNIX Programming Environment, ch. 3, pp. 71–101, Prentice Hall, 1984. [44] Cadence Design Systems, Inc., OCEAN Reference, 2001. [45] Cadence Design Systems, Inc., Cadence Interprocess Communication SKILL Reference. [46] L. Stockmeyer, “Optimal orientations of cells in slicing floorplan designs,” Information and Control, vol. 57, pp. 91–101, may 1983. [47] H. Koh, C. Sequin, and P. Gray, “OPASYN: a compiler for CMOS operational amplifiers,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 2, pp. 113–125, 1990. [48] J. Conway and G. Schrooten, “An automatic layout generator for analog circuits,” in [1992] Proceedings The European Conference on Design Automation, pp. 513–519, IEEE Comput. Soc. Press. References 171 [49] Cadence Design Systems, Inc., Cadence las referencias las buscaré el finde. [50] T. Barnes, “SKILL: a CAD system extension language,” in 27th ACM/IEEE Design Automation Conference, pp. 266–271, IEEE. [51] Cadence Design Systems, Inc., Diva® Reference, 2005. [52] Cadence Design Systems, Inc., Assura® Parasitic Extraction, 2005. [53] H. Habal and H. Graeb, “Constraint-Based Layout-Driven Sizing of Analog Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, pp. 1089–1102, aug 2011. [54] N. Lourenço, R. Martins, and N. Horta, “Layout-aware sizing of analog ics using floorplan & routing estimates for parasitic extraction,” in Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, pp. 1156–1161, EDA Consortium, 2015. [55] R. Martins, A. Canelas, N. Lourenco, and N. Horta, “On-the-fly exploration of placement templates for analog IC layout-aware sizing methodologies,” in 2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), pp. 1–4, IEEE, jun 2016. [56] S. K. Saha, “Compact MOSFET Modeling for Process Variability-Aware VLSI Circuit Design,” IEEE Access, vol. 2, pp. 104–115, 2014. [57] R. Tu, E. Rosenbaum, W. Chan, C. Li, E. Minami, K. Quader, P. Ko, and C. Hu, “Berkeley reliability tools-BERT,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 10, pp. 1524–1534, 1993. [58] E. Maricau and G. Gielen, “Background on IC Reliability Simulation,” in Analog IC Reliability in Nanometer CMOS, pp. 79–91, New York, NY: Springer New York, 2013. [59] M. Moras, J. Martin-Martinez, V. Velayudhan, R. Rodriguez, M. Nafria, X. Aymerich, and E. Simoen, “Negative bias temperature instabilities in pMOSFETS: Ultrafast characterization and modelling,” in 2015 10th Spanish Conference on Electron Devices (CDE), pp. 1–4, IEEE, feb 2015. [60] A. Avellán, D. Schroeder, and W. Krautschneider, “Modeling random telegraph signals in the gate current of metal–oxide–semiconductor field effect transistors after oxide breakdown,” Journal of Applied Physics, vol. 94, pp. 703–708, jul 2003. [61] B. Kaczer, P. J. Roussel, T. Grasser, and G. Groeseneken, “Statistics of Multiple Trapped Charges in the Gate Oxide of Deeply Scaled MOSFET Devices—Application to NBTI,” IEEE Electron Device Letters, vol. 31, pp. 411–413, may 2010. [62] http://ptm.asu.edu/, “Arizona state university predictive technology model.” 172 References [63] A. Zhang, C. Huang, T. Guo, A. Chen, S. Guo, R. Wang, R. Huang, and J. Xie, “Reliability variability simulation methodology for IC design: An EDA perspective,” in 2015 IEEE International Electron Devices Meeting (IEDM), pp. 11.5.1–11.5.4, IEEE, dec 2015. [64] E. Afacan, G. Berkol, G. Dundar, A. E. Pusane, and F. Baskaya, “A deterministic aging simulator and an analog circuit sizing tool robust to aging phenomena,” in 2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), pp. 1–4, IEEE, sep 2015. [65] E. Afacan, G. Berkol, A. E. Pusane, G. Dundar, and F. Baskaya, “Adaptive sized Quasi- Monte Carlo based yield aware analog circuit optimization tool,” in 2014 5th European Workshop on CMOS Variability (VARI), pp. 1–6, IEEE, sep 2014. [66] X. Pan and H. Graeb, “Reliability optimization of analog integrated circuits considering the trade-off between lifetime and area,” Microelectronics Reliability, vol. 52, no. 8, pp. 1559–1564, 2012. [67] X. Pan and H. Graeb, “Reliability analysis of analog circuits using quadratic lifetime worst-case distance prediction,” in IEEE Custom Integrated Circuits Conference 2010, pp. 1–4, IEEE, sep 2010. [68] E. Afacan, G. Berkol, G. Dundar, A. E. Pusane, and F. Baskaya, “A lifetime-aware analog circuit sizing tool,” Integration, the VLSI Journal, vol. 55, pp. 349–356, sep 2016. [69] Seobin Jung, Jiho Lee, and Jaeha Kim, “Yield-Aware Pareto Front Extraction for Discrete Hierarchical Optimization of Analog Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, pp. 1437–1449, oct 2014. [70] G. Berkol, E. Afacan, G. Dundar, A. E. Pusane, and F. Baskaya, “A novel yield aware multi-objective analog circuit optimization tool,” in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2652–2655, IEEE, may 2015. [71] B. Liu, F. V. Fernandez, and G. G. E. Gielen, “Efficient and Accurate Statistical Analog Yield Optimization and Variation-Aware Circuit Sizing Based on Computational Intelligence Techniques,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, pp. 793–805, jun 2011. [72] F. V. Fernandez, J. Esteban-Muller, E. Roca, and R. Castro-Lopez, “Stopping criteria in evolutionary algorithms for multi-objective performance optimization of integrated inductors,” in IEEE Congress on Evolutionary Computation, pp. 1–8, IEEE, jul 2010.