Harmonic orientation of pulse width modulation technique in multilevel inverters

POWER ENGINEERING AND ELECTRICAL ENGINEERING, VOL. 9, NO. 1,MARCH 2011 29 ©2011 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING ISSN 1804-3119 HARMONIC ORIENTATION OF PULSE WIDTH MODULATION TECHNIQUE IN MULTILEVEL INVERTERS Urmila BANDARU.1, Subbarayudu D 1 1 Department of EEE, G. Pulla Reddy Engineering College, Kurnool, Andhra Pradesh, India [email protected], ds[email protected]m Abstract. The Multilevel Inverter topology gives the advantages of usage in high power and high voltage application with reduced harmonic distortion without a transformer. This paper presents a comparative study of orientation of higher ordered harmonics with increase in switching frequency around the frequency modulation index of nine level diode clamped inverter for different Switching frequency Multicarrier Pulse width Modulation. Keywords Multicarrier Pulse Width Modulation, diode clamped inverter, Switching frequency optimal PWM, Sub-Harmonic PWM, Constant switching frequency, harmonic orientation, multilevel converter, Total harmonic distortion. 1. Introduction Multilevel Pulse Width Modulation (PWM) inverters have been gained importance in high performance power applications without requiring high ratings on individual devices, as static var compensators, drives and active power filters. A multilevel inverter divides the dc rail directly or indirectly, so that the output of the leg can be more than two discrete levels. As both amplitude modulation and pulse width modulation are used in this, the quality of the output waveform gets improved with low distortion. The advantages of multilevel inverter are good power quality, low switching losses, reduced output dv/dt and high voltage capability. Increasing the number of voltage levels in the inverter increases the power rating. The three main topologies of multilevel inverters are the Diode clamped inverter, Flying capacitor inverter, and the Cascaded H-bridge inverter [1], [2], [3]. The PWM schemes of multilevel inverters are classified in to two types the multicarrier sub-harmonic PWM (MC-SHPWM) and the Multicarrier switching frequency optimal pulse width modulation (MC-SFOPWM) [4], [5]. The MCSHPWM diode clamped multilevel inverter strategy reduced total harmonic distortion at high switching frequency [6]. This paper considered the most popular structure among the transformerless voltage source multilevel inverters, the diode-clamped converter based on the neutral point converter proposed by Akagea et al [1]. 2. Multilevel Inverter Illustration Fig 1(a) shows a two level inverter. Fig 1(b) shows a three level inverter. Fig 1(c) shows N level inverter. All the capacitors comprises to a voltage of Vdc. Fig. 1. Schematic Diagram of (a) Two level Inverter (b) Three Level Inverter (c) N Level Inverter Fig 2 (a) shows the output voltage of a two level inverter. Fig 2 (b) shows the output voltage a three level inverter. Fig 2 (c) shows the output voltage of an N level inverter. Fig. 2. Output Voltage of (a) Two Level Inverter (b) Three Level Inverter (c) Five Level Inverter 2.1 Diode Clamped Multilevel Inverter The number of levels in the line-to-line voltage waveform will be 12 - = Nk .(1) 30 POWER ENGINEERING AND ELECTRICAL ENGINEERING, VOL. 9, NO. 1,MARCH 2011 ©2011 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING ISSN 1804-3119 The number of levels in the line to load neutral of a star or wye load will be 12 -= kp .(2) The number of capacitors required, independent of the number of phase, is 1-= NNcap .(3) While the number of clamping diodes per phase is ( ) 12 -= NDclamp .(4) The number of possible switch states is nstates=Nphases phases states Nn =.(5) and the number of switches in each leg is Sn=2(N-1) ( ) 12 -= NSn.(6) 3. PWM Methods for Multilevel Inverters The two basic approaches used to generate the PWM signals for multilevel inverters are a. Sub Harmonic or Sub-Oscillation carrier based PWM-modulating waveform comparison with offset triangular carriers b. Space Vector PWM-space vector modulation based on a rotating vector in multilevel space and these are the extensions of traditional two level control strategies to several levels. The main advantages of PWM inverters in comparison to square-wave inverters are (i) control over output voltage magnitude (ii) reduction in magnitudes of unwanted harmonic voltages (iii) improved power factor with unity displacement factor. Lowest order harmonic elimination is possible by proper choice of the number of pulses per half cycle. Carrara considered different methods of disposing the many carrier bands required in multilevel PWM. Four alternative carrier PWM strategies with differing phase relationships for a multilevel inverter [15] are as follows: 1) In-phase disposition (IPD), where all the carriers are in phase; 2) Phase opposition disposition (POD), where the carriers above the zero reference are in phase, but shifted by 1800 from those carriers below the zero reference; 3) Alternative phase opposition disposition (APOD), where each carrier band is shifted by 180 0 from the adjacent bands; 4) Phase Disposition (PD), all the carriers are phase shifted by 2π/(N-1) radians. PD strategy is used most frequently because it produces minimum harmonic distortion for the line–to– line output voltage [13]-[15]. 3.1 Sub Harmonic Pulse Width Modulation (SHPWM) Technique or Sinusoidal Pulse Width Modulation (SPWM) In SHPWM technique the intersection of the triangular carrier and the modulation wave determines the generation of the pulse. This requires a carrier of much higher frequency than the modulation frequency. The generated rectilinear output voltage pulses are modulated such that their duration is proportional to the instantaneous value of the sinusoidal waveform at the centre of the pulse; that is, the pulse area is proportional to the corresponding value of the modulating sine wave. Good quality output voltage in SPWM requires the modulation index (MI) to be less than or equal to 1.0. For MI>1 (over-modulation), the fundamental voltage magnitude increases but at the cost of decreased quality of output waveform. The maximum fundamental voltage that the SPWM inverter can output (without resorting to overmodulation) is only 78.5% of the fundamental voltage output by square-wave inverter. In this paper SPWM technique has been considered. The merits and demerits of this PWM technique for different frequencies are compared under comparable circuit conditions on the basis of factors like (i) quality of output voltage (ii) obtainable magnitude of output voltage (iii) ease of control (iv)reduction in total harmonic distortion etc. The peak obtainable output voltage from the given input dc voltage is one important figure of merit for the inverter. If the carrier frequency is very high, an averaging effect occurs, resulting in a sinusoidal fundamental output with high-frequency harmonics, but minimal lowfrequency harmonics. 3.2 Switching Frequency Optimal Pulse width Modulation (SFOPWM) Technique Steinke [12] proposed SFOPWM, a carrier based method where addition of triplen harmonic to the fundamental frequency Sinusoidal lowers the peak magnitude, thus allowing operating in over modulation region. This increases the inverter output voltage without compromising on the quality of the output waveform [3][4]. Equations (7) to (10) are used to obtain the modulating wave. ( ) ( ) ( ) 2 ,,min,,max cbacba offset VVVVVV V+ =.(7) POWER ENGINEERING AND ELECTRICAL ENGINEERING, VOL. 9, NO. 1,MARCH 2011 31 ©2011 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING ISSN 1804-3119 offsetaaSFO VVV -= .(8) offsetbbSFO VVV -= .(9) offsetccSFO VVV -= .(10) The zero sequence modification made by the SFOPWM technique restricts its use to three phase three wire system; however it enables the modulation index to be increased by 15.47% before over modulation or pulse dropping occurs. The amplitude modulation index and frequency modulation index are given in (11) and (12) respectively. c m aAm A mMI )1( - =Ú .(11) m c ff f m=.(12) Where: ·m is the number of carrier waves also the level of the inverter, required for pulse generation ·Am and fm are the amplitude and frequency of the reference wave, a sinusoidal wave respectively ·Ac and fc amplitude of the carrier wave, a triangular wave respectively 4. Analysis of Nine Level Diode Clamped Inverter A three-phase nine-level diode-clamped inverter is shown in fig.4. Each phase is constituted by 16 switches (eight switches for upper leg and eight switches for lower leg). Switches Sa1 through Sa8 of upper leg form complementary pair with the switches Sa1’ to Sa8’lower leg of the same phase. Fig. 3. Circuit Diagram of 3 Phase Nine Level Diode Clamped Inverter The complementary switch pairs for phase ‘A’ are (Sa1, Sa1’), (Sa2, Sa2’), (Sa3, Sa3’), (Sa4, Sa4’), (Sa5, Sa5’), (Sa6, Sa6’), (Sa7, Sa7’), (Sa8, Sa8’) and similarly for B and C phases [1]-[8],[17]. Clamping diodes are used to carry the full load current. Tab. 1 shows phase to fictitious midpoint ‘o’ of capacitor string voltage (VAO) and line to line voltage (VAB) for various switching. Tab. 1. Pole Voltage and Line Voltage of a Nine Level Inverter Sa1 S a2 S a3 S a4 S a5 S a6 S a7 S a8 V AB VAO 1 1 1 1 1 1 1 1 V dc V dc 0 1 1 1 1 1 1 1 V dc /8 3V dc /4 0 0 1 1 1 1 1 1 2Vdc/8 2Vdc/4 0 0 0 1 1 1 1 1 3V dc /8 V dc /4 0 0 0 0 1 1 1 1 4V dc /8 0 0 0 0 0 0 1 1 1 5V dc /8 -V dc /4 0 0 0 0 0 0 1 1 6V dc /8 -2V dc /4 0 0 0 0 0 0 0 1 7V dc /8 -3V dc /4 0 0 0 0 0 0 0 0 0 -Vdc This paper provides analytical methods for the study, performance evaluation, and design of the carrier-based PWM which are widely employed in PWM multilevel voltage-source inverter drives due to the low-harmonic distortion waveform characteristics with well-defined harmonic spectrum, the fixed switching frequency, and implementation simplicity. The one most important modulator characteristics—the total harmonic distortion is analytically modeled and compared for various switching frequencies applied to a Nine Level Neutral Point Clamped or Diode Clamped Inverter. Simulations of the controller and of the inverter have been made in the MATLAB SIMULINK environment. A Nine Level Neutral Point Clamped or Diode Clamped Inverter is simulated for different switching frequencies and the orientation of higher ordered harmonics around the switching frequency is presented. 5. Simulation Results and Discussions A Nine Level Diode Clamped Inverter is simulated for a modulation index of 0.9 and switching frequencies of 1kHz, 2kHz, 3kHz and 4kHz and the orientation of higher ordered harmonics around the switching frequency is presented. For fc=1kHz, the Total Harmonic Distortion is 14.32%. Fig4 indicates 20th harmonic is the dominant and constituting maximum value of the THD and is 10.57% shown in Tab.2. When fc=2kHz, the Total Harmonic Distortion is 14.09%. Fig.5 indicates 30th harmonic is the significant and constituting maximum value of the THD and it is 10.41% shown in Tab.3. Fig.6 shows when fcincreases to 3kHz, the Total Harmonic Distortion is 13.90% where 40th harmonic is the 32 POWER ENGINEERING AND ELECTRICAL ENGINEERING, VOL. 9, NO. 1,MARCH 2011 ©2011 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING ISSN 1804-3119 dominant and constituting maximum value of the THD and is 10.12% shown in Tab.4. From Tab.5 the significant 80th harmonic value is 9.99% of Total Harmonic Distortion 13.77% and is shown in Fig.7 for fc=4kHz. 010 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1 Harmonic order THD= 14.32% Mag P.U. Dominant Harmonic Fig. 4. Pole Voltage THD mf =20, fc=1kHz Tab. 2. List of harmonic orientation around fC=1kHz 010 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1 Harmonic order THD= 14.09% Mag P.U. Dominant Harmonic Fig. 5. Pole Voltage THD mf =40, fc=2kHz Tab. 3. List of harmonic orientation around fC=2kHz 010 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1 Harmonic order THD= 13.90% Mag P.U. Dominant Harmonic Fig. 6. Pole Voltage THD mf =60, fc=3kHz Tab. 4. List of harmonic orientation around fC=3kHz 010 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1 Harmonic order THD= 13.77% M ag P.U. Dominant Harmonic Fig. 7. Pole Voltage THD mf =80, fc=4kHz Tab. 5. List of harmonic orientation around fC=4kHz When a triangular carrier wave has its peak coincides with zero of the reference sinusoid there are P number of pulses per half cycle. 2 f m P=.(13) If zero of the triangular carrier wave coincides with zero of the reference sinusoid there is (P-1) number of pulses per half cycle. The PWM pushes the harmonics into a high frequency range around the switching frequency fc and its multiples around mf, 2mf, 3mf and so on. The frequencies at which the voltage harmonics occur can be related by ( ) cfn fKmjf ×±×= .(14) Where the nth harmonic equals the kth sideband of jth times the frequency modulation ratio mf. KjPKmjn f±=±×= 2,(15) for j=1, 2, 3, ... and k=1, 2, 3, ... Harmonic analysis of the output modulated voltage wave reveals that SPWM has the following important features. For MI <1, largest amplitudes in the output voltage are associated with harmonics of order mf, mf ±1 or 2P±1. Thus by increasing the number of pulses per half cycle, the POWER ENGINEERING AND ELECTRICAL ENGINEERING, VOL. 9, NO. 1,MARCH 2011 33 ©2011 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING ISSN 1804-3119 order of dominant harmonic frequency can be raised, which can then be filtered out easily. For MI>1, lower order harmonic appear, since the pulse width is no longer a sinusoidal function of the angular position of the pulse. Over modulation basically leads to a square wave operation and adds more harmonics as compared to operation in the linear range (MI≤1). Fig.8, Fig.9 and Fig.10 are the pole, phase and line voltages respectively for 10 pulses per half cycle (mf=20). 00.01 0.02 0.03 0.04 0.05 0.06 0. 07 0. 08 0.09 0.1 -100 0 100 Time (s) V oltage(V ) Fig. 8. Pole Voltage fc =1kHz 00.01 0.02 0.03 0. 04 0.05 0.06 0. 07 0.08 0.09 0.1 -100 0 100 Time (s) V oltage(V ) Fig. 9. Phase Voltage fc =1kHz 00.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0. 09 0.1 -200 0 200 Time (s) V oltage(V ) Fig. 10. Line Voltage fc =1kHz Fig.11, Fig.12 and Fig.13 are the pole, phase and line voltages respectively for 20 pulses per half cycle. 00.01 0.02 0.03 0.04 0.05 0.06 0. 07 0.08 0.09 0.1 -100 0 100 Time (s) Voltage(V) Fig. 11. Pole Voltage fc =2kHz 00.01 0.02 0.03 0.04 0.05 0.06 0. 07 0.08 0. 09 0.1 -100 0 100 Time (s) Voltage(V) Fig. 12. Phase Voltage fc =2kHz 00.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -200 0 200 Time (s) V oltage(V) Fig. 13. Line Voltage fc =2kHz Fig14, Fig15 and Fig16 are the pole, phase and line voltages respectively for 30 pulses per half cycle. 00.01 0.02 0.03 0. 04 0.05 0.06 0.07 0.08 0.09 0.1 -100 0 100 Time (s) V oltage(V ) Fig. 14. Pole Voltage fc =3kHz 00.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -100 0 100 Time (s) Voltage(V) Fig. 15. Phase Voltage fc =3kHz 00.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -200 0 200 Time (s) Voltage(V) Fig. 16. Line Voltage fc =3kHz Fig.17, Fig.18 and Fig.19 are the pole, phase and line voltages respectively for 40 pulses per half cycle. 00.01 0. 02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -100 0 100 Time (s) V oltage(V ) Fig. 17. Pole Voltage fc =4kHz 00.01 0.02 0.03 0.04 0.05 0.06 0. 07 0.08 0. 09 0.1 -100 0 100 Time (s) V oltage(V ) Fig. 18. Phase Voltage fc =4kHz 34 POWER ENGINEERING AND ELECTRICAL ENGINEERING, VOL. 9, NO. 1,MARCH 2011 ©2011 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING ISSN 1804-3119 00.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0. 09 0.1 -200 0 200 Time (s) V oltage(V ) Fig. 19. Line Voltage fc =4kHz 6. Conclusions A nine level diode clamped inverter is modeled and simulated for different switching frequencies of SPWM technique and are compared for normal modulation index. High switching frequency decreases the low ordered harmonics thus increasing the higher ordered harmonics which can be filtered out easily by filters in output voltage. Increase in switching frequency improves the quality of the output voltage waveform. Acknowledgments The authors acknowledge the G. PullaReddy Engineering College Management support. References [1] JOSÉ RODRÍGUEZ, JIH-SHENG LAI,FANG ZHENG PENG “Multilevel inverters: A survey of topologies, controls, and applications”, IEEE Trans., vol. 49, no. 4, august 2002. [2] G.CARRARA, S.GARDELLA, M.MARCHESONI, R.SALUTARI AND G.SCIUTTO, “A new multilevel pwm method: a theoretical analysis”, IEEE Transactions on Power Electronics, vol. 7, no. 3, july 1992, pp.497-505. [3] A. NABAE, I. TAKAHASHI, H. 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ENJETI, “A carrier-based pwm method with optimal switching sequence for a multi-level four-leg vsi” IEEE , June 2005, pp 99-105. [15] LEON M. TOLBERT, FANG Z.PENG, THOMAS G. HABETLER, “Novel multilevel inverter carrier-based pwm” IEEE IAS 1998, Missouri, october 10-15, 1998, pp. 1424-1431. About Authors ... Urmila BANDARU was born in the year 1973. She received her M.Tech. from S.K.University in 2008. Her research interests include Power Electronics, Electrical machines, Solar Energy Systems and Micro Electronics. Subba RAYUDU D was born in the year 1973. He received his M.Sc (E ngg) degree from Madras University in 1962 and Ph.D degree from Indian Institute of Technology, Madras, India in1977. His research interests include Electrical machines, Power Electronics, Analog Electronics and Integrated circuit applications.