The Influence of Repetitive UIS on Electrical Properties of Advanced Automotive Power Transistors

THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 20 |NUMBER: 1 |2022 |MARCH The Influence of Repetitive UIS on Electrical Properties of Advanced Automotive Power Transistors Juraj MAREK 1, Jozef KOZARIK 1,2, Michal MINARIK 1, Ales CHVALA1, Lubica STUCHLIKOVA1 1Institute of Electronics and Photonics, Slovak University of Technology in Bratislava, Ilkovicova 3, 812 19 Bratislava, Slovak Republic 2NanoDesign, s.r.o, Drotarska 19a, 811 04 Bratislava, Slovak Republic jura[email protected], jozef.k[email protected], mic[email protected], ales.chv[email protected], lubica.stuchlikov[email protected] DOI: 10.15598/aeee.v20i1.4120 Article history: Received Feb 22, 2021; Revised Nov 08, 2021; Accepted Nov 23, 2021; Published Mar 31, 2022. This is an open access article under the BY-CC license. Abstract. This paper investigates a degradation of three types of automotive power MOSFETs through repetitive Unclamped Inductive Switching (UIS) test typically used to evaluate the avalanche robustness of power devices. It is not uncommon in switching applications that greater than the planned voltage for voltage spikes can occur, so even the best electronic designs may encounter frequent avalanche events. Hence, there is a need to analyse the impact of repetitive avalanching on the electrical performance of power transistors. This article focused on the shift of main electrical parameters: on-resistance RON , breakdown voltage VBR, threshold voltage VT H , and corresponding characteristics, as well as capacitances. Analysis proved that DMOS transistors are less vulnerable to repetitive avalanching. The most impacted parameter was on-resistance RDSon, where a 14 % increase was observed after 6·107stress pulses. The parameters shift is attributed to hot carrier injection in the space charge region of blocking PN junction and involves mainly defects generation/activation in the drain side region of the gate oxide. For the TrenchMOS transistor, a significant shift of I−Vcurves was observed with considerable impact on the RON where an increase of 22 % was observed. The trench corner is verified to be the mainly degraded region by Synopsys Technology Computer Aided Design (TCAD) simulations. Degradation of drain-gate capacitance CDG and input capacitance Cin was observed in all three types of analysed structures. DLTS was used to verify the generation/activation of defects invoked by stress. An increase of DLTS signal corresponding to energy levels of oxygen vacancies and impurities in SiO2and on interfaces were detected on stressed samples. Keywords Degradation, DLTS, repetitive avalanching, repetitive Unclamped Inductive Switching (UIS), TCAD. 1. Introduction Silicon power MOSFETs have still a dominant role in automotive and industrial electronics where the power devices drive relatively high inductive loads [1], [2], and [3]. Therefore, high voltage and high current operations are common requirements for semiconductor devices in power applications [4], [5], and [6]. When a power MOSFET is used in circuit application, an unclamped inductive load presents extremely stressful switching condition. During the switching all of the energy stored in the inductor during on state is dumped directly into the device during its turn off typically by driving it into avalanche mode conduction [4], [7], [8], and [9]. As a consequence, the ability of the MOSFET to withstand instances of Unclamped Inductive Switching (UIS) is an important performance metric. ©2022 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 86 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 20 |NUMBER: 1 |2022 |MARCH Thus, a UIS test condition represents the circuit switching operation for evaluating the avalanche ruggedness of the device [10], [11], and [12]. Typically, a standard UIS test described by JEDEC standards is a single pulse test, but power MOSFETS in real automotive systems can be subjected to events of UIS over the lifetime of their application. Therefore, standard UIS tests cannot fully reveal possible risks arising from repetitive avalanche operations [13] and [14]. An excellent example of an application where repetitive avalanching occurs is the antilock braking system. The system is typically composed of a low-side power MOSFET switch that connects the brake pump to the battery and is switched by a pressure control system connected to the gate [15]. Every time the MOSFET is switched on, the brake pump is connected to the battery and energy is stored in the inductors of the brake pump. When the MOSFET is switched off, the energy in the brake pump is dissipated through the MOSFET by driving it into the avalanche and this event can occur over 500 million times in the operating life of the vehicle’s automotive system [15]. During avalanching, High Concentrations of hot electron-hole pairs (HC) are generated in close proximity of blocking PN junction and gate interfaces [16]. Due to high kinetic energy, hot carriers can be injected and get trapped in insulating layers and interfaces. They are able to break atomic bonds thereby creating interface states or electrically activating defects. This may lead to the change of threshold voltage VT H , breakdown voltage VBR, and on-resistance RON [14]. These changes during the lifetime operation of the device pose considerable risks against the requirement of long-term reliability of automotive power MOSFETs. 2. UIS Test A custom-built avalanche test equipment (Fig. 1(a)) was used for repetitive ruggedness testing to perform more than 108stress pulses. A commercial UIS tester ITC55100 was used for reference measurements and calibration. Commercial tester is not suitable for longterm measurements because each set of 100 pulses is followed by the time period needed for communication. This represents a considerable delay for a larger number of pulses. In Fig. 1(b) the circuit diagram and typical voltage and current waveforms during the test are shown. The test circuit conditions (Fig. 1(b)) were defined by following parameters: supply voltage VDD = 20 V, peak inductance current IAS = 5 A, inductive load L= 1 mH, max gate voltage VG= 10 V, and gate resistance RGen = 25 Ω. The duty cycle was set to 10 % to maintain temperature of tested device under 130 ◦C controlled by an IR camera. The Device Under Test (DUT) is connected to the power supply through the inductor and high side switch HSW. When both DUT and HSW are turned ON, current, limited by the inductor, starts to rise linearly. When the current through inductance reaches the preset value IAS , DUT and HSW are turned off by the control unit, and the VDD source is disconnected from the test circuit, therefore active part of the test circuit now consists only of the DUT, charged inductive load L, and FWD diode. As DUT is turning off, the current through the transistor channel is decreasing until the channel is completely closed. However, the current through inductance cannot change instantaneously. Therefore, the magnetic field of charged inductor induces a counter Electromagnetic Force (EMF) against this change to keep current flowing through inductor. EMF induces high potential across the inductor and DUT which drives DUT to the electric breakdown [8]. Current from the inductor now flows through DUT as an avalanche current, and the current loop is closed by the FWD diode. If no protective circuits are added in parallel to the switch, all build-in energy of the inductor is dissipated directly into the device [12]. Different types of automotive-grade MOSFETS were used for investigations: vertical DMOS rated to 24 V and two Trench MOS transistors rated to 30 V and 90 V. To analyze parameter degradation, I−V and C−Vmeasurements were performed first on virgin samples, and then after each set of stress pulses. To support the analysis of parameter shift due to HCI, TCAD simulations and modeling were performed. Deep Level Transient Spectroscopy (DLTS) measurements were accomplished to analyze parameters and the possible origin of generated/activated electrically active defects. 3. Results and Discussion First, DMOS transistors were subjected to repetitive UIS stress for up to 6·107of stress pulses. Measured on-resistance RON , transfer and C−Vcharacteristics are shown in Fig. 2. The impact of stress on I−Vcharacteristics was very low and non-uniform. Increase by 14 % of onresistance was observed after 6·107of stress pulses. We assume that the increase of on-resistance can be more attributed to the material degradation (degradation of the top side metallization due to the cyclic thermal stress) than to the degradation of channel Si/SiO2interface caused by HCI [13], [14] and [15]. ©2022 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 87 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 20 |NUMBER: 1 |2022 |MARCH (a) + GEN DUT FWD VDD ID VDS HSW Rgen (b) -1,0 -0,5 0,0 0,5 0 4 8 12 16 20 24 28 32 36 40 300 315 330 345 360 375 temperatures TJ, TJM (K) Voltage VGS, VDS (V), Current ID(A) Time (ms) meas. simul. UGS meas. simul. ID meas. simul. UDS meas. TJ simul. TJM (c) Fig. 1: (a) Custom-built repetitive avalanche test equipment. (b) Basic UIS test circuit and (c) typical waveforms of current, voltage and junction temperature of the DUT under UIS test conditions. 103104105106107108 2 3 4 5 6 7 8 9 On-resistance RON (m�) Number of stress pulses (-) gate voltage VGS (V) 4.5 10 virgin sample (a) 1,4 1,5 1,6 1,7 1,8 1,9 0,0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1,0 Number of UIS pulses virgin sample 1x104 1x105 1x106 5x106 1x107 3x107 4x107 6x107 Drain current ID(mA) Gate-source voltage VGS (V) (b) -10 -5 0 5 10 15 3,4 3,6 3,8 4,0 4,2 4,4 4,6 Number of UIS pulses virgin sample 1x106 3x106 4x106 6x106 Capacitance Cin (nF) Gate-source voltage VGS (V) (c) 0 2 4 6 8 10 0,4 0,6 0,8 1,0 1,2 1,4 1,6 1,8 Number of UIS pulses virgin sample 1x106 3x106 4x106 6x106 Capacitance CDG (nF) Drain-gate voltage VDG (V) (d) -2 0 2 4 6 8 10 1 2 3 4 5 Number of UIS pulses virgin sample 1x106 3x106 4x106 6x106 Capacitance CDS (nF) Drain-source voltage VDS (V) (e) Fig. 2: DMOS transistor - impact of repetitive UIS stress on shift of electrical parameters and characteristics: (a) on on-resistance RON , (b) transfer characteristics, (c) input capacitance Cin, (d) drain to gate capacitance CDG and (e) drain to source capacitance CDS . It is a well-known fact that long-term thermal cycling leads to degradation of top metalization. Degradation of power metal leads to increased serial resistance of transistor but has minimal effect on C−V characteristics. Our assumptions are also confirmed by the fact that only a small change in the threshold voltage was observed. From C−Vmeasurements (Fig. 2(c), Fig. 2(d) and Fig. 2(e)), it is clear that the most considerable impact of applied stress was observed for capacitances CIN and CGD whilst shift of drain to source capacitance CDS was negligible. Change of capacitances CIN and CGD was saturated after 6·106of stress pulses, and no further change was observed. This is in good correlation with results observed in published works [16], [17], [18], and [19]. To explain the shift of gate to drain capacitance, TCAD simulations in Synopsys TCAD were performed to visualize the location and distribution of hot electrons in the device’s volume at the beginning of the discharging period when the highest voltage and current are present on the device (Fig. 3(a)). For this reason, hydrodynamic simulations were performed using the University of Bologna (UniBo) model for avalanche generation. Models of structures (for DMOS as well as TrenchMOS) were generated from simulation ©2022 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 88 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 20 |NUMBER: 1 |2022 |MARCH eTemperature (K) 9.7E+03 7.8E+03 5.9E+03 4.0E+03 2.2E+03 2.9E+02 (a) -10 -5 0 5 10 3,2 3,4 3,6 3,8 4,0 4,2 4,4 Capacitance Cin (nF) Gate-source voltage VGS (V) without traps SiO2/Si traps Nt=5x1011 cm-2 (b) Fig. 3: (a) Distribution of hot electrons in the volume of DMOS transistor during the avalanching period of UIS test. (b) Simulated CV curves with defined traps on SiO2/Si interface on the drain side of the gate electrode. 105106107108 6 7 8 9 10 11 12 gate voltage VGS (V) 4.5 10 On-resistance RON (m�) Number of stress pulses (-) (a) 37,5 37,6 37,7 37,8 37,9 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1,0 VGS = 0 V Number of UIS pulses virgin sample 22x106 50x106 10x107 Drain current ID (mA) Drain-source voltage VDS (V) (b) 1,50 1,75 2,00 2,25 0,0 0,2 0,4 0,6 0,8 1,0 Number of UIS pulses virgin sample 22x106 50x106 100x106 Drain current ID(mA) Gate-source voltage VGS (V) (c) Fig. 4: TrenchMOSFET - Impact of repetitive UIS stress on shift electrical parameters and characteristics: (a) on on-resistance RON, (b) breakdown and (c) transfer characteristics. of technological processes provided by samples manufacturer. This also ensured a good match of simulated and real characteristics. Most of the generated hot carriers at the bottom of the P-well are sufficiently far from the transistor channel; therefore, their influence on threshold voltage and on-resistance is limited. Only a small amount of HC is close to the gate dielectric. Injection of HC to the gate dielectric in this part of the structure is therefore responsible for the change of CIN and CGD capacitances. This was verified by TCAD simulation with added traps (fixed charge Nt= 5 · 1011 cm−2) to the SiO2/Si interface in the exposed part of the structure (Fig. 3(b)). Furthermore, 30 V Trench MOSFETs were subjected to repetitive UIS test. In this case shift of transfer and breakdown characteristics were observed (Fig. 4) as well as a small increase of onresistance. Performed TCAD simulations indicate that the drain side of the gate dielectric and channel area is more exposed to hot electrons generated during the avalanching period of the test (Fig. 5). Therefore, the shift of the characteristics and parameters is more significant than in the case of DMOS transistors. The fact that different increase of on-resistance was observed for different gate potentials indicates HCI origin of on-resistance degradation. We think that, in our case, metal degradation invoked by thermomechanical stress during temperature excursions from avalanche pulses was negligible [20], [21], [22], and [23]. Degradation of source metal would cause the increase of metal serial resistance independent from gate voltage. To simulate the impact of trapped/injected charge in the SiO2/Si interface, simulations with defined positive fix charge were performed. Fix charge was defined only on the small part of the SiO2/Si interface (critical area) where high concentrations of hot holes are present during the avalanching period. The results are shown in Fig. 5(b). Last analyzed devices were 90 V rated TrenchMOS transistors; the results are shown in Fig. 6. Whilst in the case of the 30 V devices, only a small impact of repetitive UIS on the VBR was observed, in the case of 90 V rated devices, impact on the VBR voltage dominates for the first million pulses and then it saturates on the value VBR = 98 V (Fig. 6(b)). The impact of repetitive avalanching on the on-resistance RON and transfer characteristic was initially minimal, but for the higher number of stress pulses it becomes more significant (Fig. 6(a) and Fig. 6(c)). To ensure high breakdown voltage and low on-resistance, more deep trenches with superjunction technology are ©2022 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 89 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 20 |NUMBER: 1 |2022 |MARCH Critical region eTemperature (K) hTemperature (K) ImpactIonization (cm-3s-1) 2.00E+20 8.27E+16 3.42E+13 1.42E+10 5.85E+06 2.42E+03 1.00E+00 9.15E+03 7.67E+03 6.20E+03 4.73E+03 3.25E+03 1.88E+03 3.00E+02 6.75E+03 5.68E+03 4.60E+03 3.52E+03 2.44E+03 1.36E+03 2.82E+02 (a) 1,50 1,75 2,00 2,25 0,0 0,2 0,4 0,6 0,8 1,0 SiO2/Si NT(cm-2) no charge 1x1010 1x1011 5x1010 1x1012 5x1012 fixed charge Drain current ID(mA) Gate-source voltage VGS (V) (b) Fig. 5: (a) Distribution of impact ionization, hot electrons and holes during the avalanching period in TrenchMOS. (b) Simulated impact of interface charge on transfer characteristics. 2,4 2,6 2,8 3,0 3,2 3,4 3,6 0,0 0,2 0,4 0,6 0,8 1,0 Number of UIS pulses virgin sample 1x103 2x103 5x103 7x103 1x104 5x104 1x105 5x105 7x105 2x107 1x108 Drain current ID(mA) Gate-source voltage VGS (V) (a) 70 80 90 100 110 120 0,0 0,2 0,4 0,6 0,8 1,0 Drain current ID(mA) Voltage drain-source VDS (V) Number of UIS pulses virgin sample 1x103 2x103 5x103 7x103 1x104 5x104 1x105 5x105 7x105 2x107 1x108 # pulses (b) 103104105106107108109 9,0 9,5 10,0 10,5 16 18 20 On-resistance RON (m�) Number of stress pulses (-) gate voltage VGS = 10 V (c) 0 2 4 6 8 0,2 0,4 0,6 0,8 1,0 1,2 Number of UIS pulses virgin sample 1x103 2x103 5x103 7x103 1x104 5x104 1x105 5x105 7x105 2x107 1x108 Capacitance CDG (nF) Drain-gate voltage VDG(V) # pulses (d) 0 2 4 6 8 10 2,6 2,8 3,0 3,2 3,4 3,6 3,8 4,0 Number of UIS pulses virgin sample 1x103 2x103 5x103 7x103 1x104 5x104 1x105 5x105 7x105 2x107 1x108 Capacitance CDS (nF) Drain-source voltage VDS(V) # pulses (e) Fig. 6: Repetitive UIS invoked shift of electrical parameters and characteristics of 90V rated Trench MOSFET: (a) breakdown voltage, (b) transfer characteristic, (c) on resistance, (d) drain-gate capacitance and (e) drain-source capacitance. used in high and middle voltage range Trench MOSFET technology [8]. Breakdown typically occurs at the same depth as the bottom of the trench. Therefore, channel area and the gate oxide dielectric are only affected by a small amount of generated hot carriers. Therefore, higher number of stress pulses is needed to invoke change of the transfer characteristic or onresistance. On the other hand, the value of the breakdown voltage in super junction structures strongly depends on the additional charge that may disrupt the charge balance and therefore decrease the value of breakdown voltage. To analyze the generated/activated traps, DLTS study was performed using DLTFS system Bio-Rad DL 8000. Measurements were performed on 30 V TrenchMOS transistors using CGD capacitance and different sets of parameters. Measured spectra confirm the large number of defects generated or activated on the drain side of the gate oxide due to hot carrier injection. Observed DLTS spectra for the virgin and stressed sample are shown in Fig. 7 for two parameter sets: •Set 1: Tw= 400 µs, tp= 200 µs, UR=−10 V, UP=−0.05 V. •Set 2: Tw= 200 µs, tp= 200 µs, UR=−1.5V, UP=−0.05 V. One can clearly see a significant increase of DLTS signal for the stressed sample, indicating the presence of a full set of different traps. Because of the high ©2022 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 90 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 20 |NUMBER: 1 |2022 |MARCH 100 200 300 400 500 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 DLTS par set1 virgin stressed DLTS par set 2 virgin stressed simulation DLTS signal (pF) Temperature (K) O-Vac Zn Au-Vac Cu Au Ag Fe (a) 2,8 3,0 3,2 3,4 3,6 3,8 51,0 51,5 52,0 52,5 53,0 53,5 54,0 ln( �� � � th�NC) 1000· T-1 (1· K-1) Level ET-EV (eV) sigma (cm-3) 1 0,365 2,89E-16 2 0,389 1,54E-16 3 0,603 6,76E-14 4 0,668 9,26E-13 5 0,48 3,8E-15 6 0,571 2,2E-15 7 0,489 2,97E-14 8 0,526 9,51E-15 9 0,209 3,22E-20 1 7 2 5 8 4 3 9 6 357 333 312 294 278 263 Temperature (K) (b) Fig. 7: (a) Obtained DLTS spectra of the virgin and stressed sample with simulated positions of dominant trap peaks. (b) Arrhenius plot of the DLTS spectra measured on the stressed sample for parametric set 2. complexity of DLTS spectra and the non-exponential character of many transients during measurements, we were able to determine only a few deep levels, mostly metals and corresponding vacancies, which were in perfect congruence with results from the literature. A direct evaluation method was used for this evaluation. The parameters and position of each trap in spectra was verified by simulation. Results of simulations are also shown in Fig. 7. Parameters and possible origin of each trap are in Tab. 1. Traps that we were not able to verify by simulation are not listed. Based on the character of observed traps, we assume that most of the defects are not generated by HCI, but rather that they are electrically activated. Only trap T1Oxygen vacancy can be attributed to the degradation of SiO2/Si interface due to HC bombardment. Tab. 1: Parameters of dominant traps. Trap Possible origin Et–EVSigma # [24] and [25] (eV) (cm2) T1O-Vac 0.180 3.00 ·10−14 T2Metal impurities in SiO20.293 9.48 ·10−14 T3Au-Vac 0.320 2.00 ·10−15 T4Metal impurities in SiO20.365 1.73 ·10−14 T5Metal impurities in SiO20.489 1.68 ·10−14 T6Metal impurities in SiO20.389 1.46 ·10−14 T7Au 0.526 1.12 ·10−14 4. Conclusion The influence of repetitive avalanche stress on the electrical performance of DMOS and two types of TrenchMOS transistors has been studied using custom-built UIS test equipment. Degradation of drain-gate capacitance CDG and input capacitance Cin was observed in all three types of analyzed structures. However, significant degradation (shift) of I−Vcurves was observed only in Trench MOS devices. DLTS measurements also confirmed the degradation influence of repetitive avalanche stress on the defect distribution. From the performed analysis, it can be argued that DMOS transistors are less vulnerable to HCI in case of repetitive avalanching than Trench MOS devices. Moreover, we observed that the breakdown voltage in modern middle and high voltage Trench MOS devices is more affected by the repetitive avalanching than in standard low voltage TrenchMOS devices. Using DLTS, several deep levels were observed on stressed samples corresponding to vacancies generated on Si/SiO2interface and metal impurities originating from the manufacturing process. Acknowledgment This work comes from the European cooperative project R3-PowerUP, which is partially funded by the ECSEL Joint Undertaking under grant agreement no. 737417. This work was also supported by the Slovak Research and Development Agency under contract no. APVV-20-0266 and by Grant VEGA 1/0727/19 supported by Ministry of Education, Science, Research and Sport of Slovak Republic. Author Contributions J.M. and J.K. performed measurements, sample characterization, and processed the data. J.M. and M.M devised the concept, form, and specifications of the UIS tester. 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Annual Review of Materials Science. 1980, vol. 10, iss. 1, pp. 157–228. ISSN 0084-6600. DOI: 10.1146/annurev.ms.10.080180.001105. About Authors Juraj MAREK received the M.Sc. and Ph.D. degrees in microelectronics from the Slovak University of Technology in Bratislava (STUBA), Bratislava, Slovak Republic, in 2007 and 2011, respectively. He has been a researcher with the Institute of Electronics and Photonics, STUBA, since 2006 and assistant professor from 2020 respectively. His current research interests include modern power devices characterization, reliability, TCAD modeling and simulation. Jozef KOZARIK received his M.Sc. degree in electronics from the Slovak University of Technology in Bratislava (STUBA), Bratislava, Slovak Republic, in 2017. He is currently pursuing his Ph.D. degree at the STUBA Institute of Electronics and Photonics. His research is focused on reliability testing and degradation analysis of wide bandgap semiconductor devices. Ales CHVALA received his M.Sc. and Ph.D. degrees in electronics from the Slovak University of Technology in Bratislava (STUBA), Bratislava, Slovak Republic, in 2005 and 2009, respectively. has been a Researcher with the Institute of Electronics and Photonics, STUBA, since 2007. His current research interests include the TCAD and Simulation Program with Integrated Circuit Emphasis (SPICE) electrothermal modeling, simulation, and characterization of Si, SiC, and GaN based devices. Michal MINARIK received the M.Sc. degree in electronics from the Slovak University of Technology in Bratislava (STUBA), Bratislava, Slovak Republic, in 2020, where he is currently pursuing the Ph.D. degree with the Institute of Electronics ©2022 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 93 THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 20 |NUMBER: 1 |2022 |MARCH and Photonics. His current research interests include in circuit utilization of Wide-Bandgap (WBG) devices. Lubica STUCHLIKOVA graduated from the Faculty of Electrical Engineering, the Slovak University of Technology (STUBA) in Bratislava, Slovak Republic, in 1990 and received the Ph.D. degree in 1996. She works as a professor at the Institute of Electronics and Photonics, STUBA. Since 1990, she has been interested in semiconductor defects engineering and electrical characterization of semiconductor structures, devices, and materials. Since 2009, her main priority is the investigation of emission and capture processes in GaN-based structures. ©2022 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 94