Alternate Search Pattern for Parallel Sphere Decoder in Long Prediction Horizon FCS-MPC

Depósito de investigación de la Universidad de Sevilla https://idus.us.es/ This is an Accepted Manuscript of an article published IEEE Transactions on Industrial Electronics available at: 10.1109/TIE.2023.3312421 “© 2023 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other Works” IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS Alternate Search Pattern for Parallel Sphere Decoder in Long Prediction Horizon FCS-MPC Eduardo Zafra, Student Member, IEEE, Sergio Vazquez, Fellow, IEEE, Abraham M. Alcaide, Member, IEEE, Jose I. Leon, Fellow, IEEE, and Leopoldo G. Franquelo, Life Fellow, IEEE Abstract—The sphere decoding algorithm (SDA) is used in power electronics as a solver of the optimization stage for long prediction horizon finite control set model predictive control (LPH-FCS-MPC). In the literature, a parallel SDA was proposed to enable concurrent search. This strategy increases the number of candidates explored per time, improving the likelihood of finding the optimal solution in real-time. In this work, an alternate search pattern for the parallel SDA is proposed. The main idea is that each parallel sphere decoder block explores a region of the search space following a different search pattern, increasing diversification of candidates before a solution has to be delivered. This approach improves the average optimality of parallel SDA, which in turns enhances the control performance. I. INTRODUCTION RECENT years have witnessed the growth of model predictive control (MPC) in power electronics [1], [2]. These strategies are capable of addressing the control of complex systems and multiple targets in a straightforward manner. In finite control set - MPC (FCS-MPC), the control problem is defined as an integer optimization problem where the control inputs are restricted to the switch positions of the power converter. A discrete prediction model is used to compute the evolution of the system state variables in future sampling instants. The amount of time steps considered in the predictions is known as prediction horizon length (Np). Typically, the optimization problem is solved through an Exhaustive Search Algorithm (ESA) [3]. While straightforward, the main caveat of this method is that the number of combinations grows exponentially with Np. Thus, the problem becomes intractable [4]. However, extending Npprovides remarkable performance benefits [5]. The main existing solutions rely on the reformulation of the optimization problem to an equivalent integer least-squares (ILS) problem as proposed in [4]. In ILS-form, the optimization problem can be solved through a branch-and-bound method known as the sphere decoding The authors gratefully acknowledge the financial support provided by the project PID2020-115561RB-C31 funded by MCIN/AEI/10.13039/501100011033 and the project TED2021- 130613B-I00 funded by MCIN/AEI/10.13039/501100011033 and by the “European Union NextGenerationEU/PRTR”. Eduardo Zafra gratefully acknowledges the financial support provided by the Spanish Ministry of Universities under grant FPU18/02704. Abraham M. Alcaide’s work is supported by Junta de Andalucia under grant P18-RT-1340, and Contrataci´ on de Personal Investigador Doctor. E. Zafra, S. Vazquez, Abraham M. Alcaide, J. I. Leon and L. G. Franquelo are with the Electronics Department, Universidad de Sevilla, Sevilla, C.P. 41092 Spain (e-mail: [email protected], [email protected]). LC Filter f; f; f; f f f ff f o; o; o; o c; c; c; Load dc Fig. 1. Three-phase two-level VSI with output LC filter circuit. algorithm (SDA) that can unequivocally find the optimal solution without exploring the complete set of candidates. In turn, the problem can be solved with a much more modest computational burden in comparison to ESA [5]. Despite this progress, long prediction horizon FCS-MPC (LPH-FCS-MPC) remains computationally challenging due to the high computational variability of the SDA and the relatively high sampling frequency (fs) necessary in FCS-MPC [6]. Typical application of the SDA involves the definition of computational upper bounds that limit the execution time of the SDA and ensure the delivery of a solution albeit suboptimal [7]. Nonetheless, the selection of suboptimal solutions can increasingly degrade control performance as they deviate from the global optimal. An in-depth definition of LPH-FCS-MPC main concepts, solutions and trends can be found in [8]. In [9], a parallel SDA is proposed, allowing a concurrent search that has the potential to remarkably improve performance. Following this approach, the main contribution of this work is the definition of an alternate SDA that performs a concurrent search similar to the parallel SDA in [9]. However, each concurrent sphere decode block follows a different search pattern to cover a greater diversity of candidates during the search stage, improving optimality and control performance metrics. As in [9], the proposal is evaluated in an uninterruptible power supply (UPS) system. II. CASE STUDY AND PROBLEM STATEMENT A voltage source inverter (VSI) and an LC filter with inductor Lfand capacitor Cfdefine the structure of the studied UPS, as shown in Fig. 1. System variables are the filter inductor current if,abc, filter capacitor voltage vo,abc and the output current io,abc. The output load is assumed as linear. The prediction model for the system is described in [9], [10]. Control input ukis the VSI switching state, Sabc,k with Sx|x=a,b,c ∈ {umin, umax}, where umin = 0 and umax = 1 define the FCS in the two-level VSI. Appending ukinputs within Npin a single array, one can define what is known as the switching sequence Uk. Similarly, the output sequence Ykand output reference sequence Y∗ kcan also be defined [9]. The This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2023.3312421 © 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 253.5 16.6 423.5 1118 254.4 256.5 28.0 621.6 844.2 398.5 846.3 400.1 521.6 127.0 253.5 16.6 423.5 1118 254.4 256.5 28.0 621.6 844.2 398.5 846.3 400.1 521.6 127.0 SDA block 0: ‘c’ SDA block 1: ‘c’ SDA block 0: ‘c’ SDA block 1: ‘r’ Parallel SDA 2 ‘cc’ Alternate SDA 2 ‘cr’ (1,0,0) (0,0,0) (1,1,0) (0,1,0) (1,0,1) (0,0,1) (1,1,1) (0,1,1) (1,0,0) (0,0,0) (1,1,0) (0,1,0) (1,0,1) (0,0,1) (1,1,1) (0,1,1) d(0) Uk= = ( , ,0) ( , ,1) ( ,0,0) ( ,1,0) ( ,0,1) ( ,1,1) ( ,0,0) ( ,1,0) ( ,0,1) ( ,1,1) ( , ,0) ( , ,1) i=3 i=2 i=1 i=0 i=3 i=2 i=1 i=0 Fig. 2. Three-layer parallel SDA and alternate SDA in ‘cr’ disposition (Np= 1). In the first four steps, the parallel SDA has explored states {000,100,001,101}. The alternate SDA has explored states {000,100,111,011}. In the parallel SDA set, only one bit changes from the states explored by each block. However, in the alternate SDA, 2 or 3 bits change, explaining the wider cost diversification in the early search stages. Basic SDA operations: “forward” (solid green/blue arrows), “sidetracking” (dashed yellow/orange arrows), and “backtracking” (dashed red/pink arrows). outcome of each Ukis evaluated by a cost function (CF), defined according to the control targets: Jk= k+Np−1 X ℓ=k ∥yℓ+1 −y⋆ ℓ+1∥2 2+λ∥uℓ−uℓ−1∥2 2.(1) The first term addresses the UPS output voltage regulation to a desired reference. The second term penalizes the control effort, limiting the average switching frequency ( ¯ Fsw). Weighting factor λ≥0adjusts the trade-off between the two considered objectives. The optimization problem seeks minimization of Jk. For long Np, this becomes computationally demanding. To solve this problem more efficiently, it is convenient to reformulate it as an equivalent ILS-problem. The necessary operations for this particular case are described in [9]. The final result is the equivalent box constrained ILS-problem: Uopt k=arg min Uk Jk=arg min Uk ∥HUk− ¯ Uunc k∥2 2(2a) s. t. Uk∈ {0,1}3Np,(2b) where (2b) are constraints imposing that Ukbelongs to the FCS extended for Npand ¯ Uunc k=HUunc kis the unconstrained solution to (2a). Matrix His a lattice generator that defines a linear transformation and yields a lattice in the 3Np- dimensional space defined by the set of points {¯ Uk=HUk: Uk∈ {0,1}3Np}. The problem seeks the optimal lattice point Uopt kwith the shortest Euclidean distance Jkto ¯ Uunc k. III. ALTERNATE SPHERE DECODING ALGORITHM The SDA is a branch-and-bound method that can be used to solve (2). Lattice points HUkdefine hyperspheres centered in ¯ Uunc kwhose squared radius is equal to Jk. The vector ¯ Uunc k is the target point and the SDA seeks to find the closest lattice point, i.e. the smallest hypersphere. The search starts by selecting an initial candidate belonging to the FCS, Uini k. During the search phase, the SDA sequentially evaluates new Uk sequences. Integer components of each possible Ukcandidate can be seen as vertices of a connected graph in tree form as can be seen in Fig. 2. Then, a depth-first enumeration strategy is established to ensure that each Ukthat meets the constraints is evaluated once maximum. This process can be described with two integer variables, the tree layer i:i∈[1,3Np]and the switch position variable j=Uk(i) : j∈[umin, umax]. The tree nodes are explored by updating the values of iand jaccording to three basic SDA operations that can be performed during the search: “forward”, “sidetracking”, and “backtracking”, appearing in order of priority. In simple terms, SDA prioritizes complete branch evaluation, performing “forward” operations, before opting for “sidetracking”, or “backtracking” in the case of a dead end (bottom layer or non-optimal solution). Each node adds a partial distance that can be accumulated to the squared radius of the currently explored hypersphere. The accumulated cost in each layer is stored in a 3Np+ 1 dimensional array, d. This allows the algorithm to retrieve the costs of previous layers when needed. Sequential cost computation can be performed as follows: d(i) = ∥H(i, :)Uk− ¯ Uunc k(i)∥2 2+d(i+ 1),(3) where H(i, :) denotes row iof matrix Hand d(3Np) = 0. The search goal is to find smaller hyperspheres that effectively reduce the search space. A partial candidate Uk(i)for which d(i)exceeds the current best is guaranteed to be non-optimal. Thus, they can be disregarded without exploring the entire Uk array. Then, its branch can be pruned from the tree. While superior to the ESA, the SDA is still limited in terms of achievable performance due to its computational variability and search speed limitations. The need for early termination with selection of a suboptimal candidate may be necessary to ensure real-time control, causing performance degradation [7]. To address this, a Parallel SDA was proposed in [9]. Through this technique, the SDA tree is explored concurrently by a number of parallel blocks equal to a power of two (2n). The search space is partitioned in equally sized regions separated by boundary nodes in the tree. Experimental results in [9] backed the validity of this design, as superior performance can be achieved by multiplying the amount of nodes that can be explored in the same time frame by a factor of 2n. The presented research work builds on the parallelization concept and proposes an alternate SDA that consists in parallel blocks that explore their assigned tree portion with a different search pattern. This translates into concurrently exploring candidates with more differing costs. Thus, the probability of finding good branches in terms of costs during the search early stages is improved. Justification for this can be found in (3). The cost of a partial candidate d(i)depends on magnitudes relating to the current node: ∥H(i, :)Uk− ¯ Uunc k(i)∥2 2and This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2023.3312421 © 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 100 200 300 400 500 60 80 100 100 200 300 400 500 2 3 4 5 6 100 200 300 400 500 60 80 100 100 200 300 400 500 2 3 4 5 6 150 200 250 85 90 95 150 200 250 3 3.5 4 a b c d ccrr ccccrrrr ccrrccrr crcr crcrcrcr cc crcr cr cccccccc cccc crcrcrcr max nod max nod max nod max nod 123 70 80 90 100 1 2 3 2 4 6 8 10 1 1.5 2 5 10 e f sw sw cc ccrr cr cccccccc cccc ccccrrrr Fig. 3. Optimality (Op(%)) and average cost (dµ) scaled dividing by 1000 in function of Nmax mod (a-d). a) and b) Conventional SDA, parallel SDA and alternate SDA comparison. c) and d) Different dispositions for alternate SDA. e) and f) Performance metrics in function of ¯ Fsw with Nmax mod = 300. the accumulated partial cost through the parent nodes in the branch: d(i+ 1). Thus, different nodes will tend to have more similar costs as their parents are more similar. This is a common occurrence for the parallel SDA in [9] as concurrent branches are explored with the same conventional search pattern, denoted as search pattern ‘c’. Therefore, with the exception of the boundary node, which is unique for every region, the rest of explored nodes tend to add the same switch positions in the same components of Ukat the same time. Thus, adding very similar costs to the accumulated. In the proposed alternate SDA, by defining a reverse search pattern (denoted as search pattern ‘r’) followed by half of the parallel blocks, this tendency is avoided to a greater degree. In Fig. 2, parallel SDA and alternate SDA strategies with 2 parallel blocks are compared in the simulation case of Np= 1. In this example, the partial cost is represented next to each node. There are eight complete branches Ukin the search space, with total cost represented in the bottom layer i= 0. Each region contains four branches with different total cost. However, if the branches in each region are sorted by cost, the order is the same. The result of adopting a reverse search pattern in the second SDA block is that in the event of early termination, the overall covered search space includes a selection of candidates with more diverse costs. Thus, there is a greater chance that the optimal candidate or a better suboptimal candidate is included among the explored branches. Implementation-wise, both search patterns ‘c’ and ‘r’ can be reduced to the same three basic SDA operations previously defined. However, iand jare updated in a different way. In terms of computational resources, this change is straightforward. Thus, performance improvements come at zero cost in terms of resources or design complexity in comparison to [9]. There are several possibilities in which the alternate SDA disposition can be designed. For instance, it can be proposed to alternate the search pattern for each adjacent tree sector, i.e. disposition ‘crcr...’ every two adjacent sectors, i.e. ‘ccrr...’, four...etc. Henceforth, the notation used in this letter will be SDAn ‘ccrr...’, where n is the number of parallel blocks (n=1 would be a Conventional SDA) and the remaining characters indicate the disposition (‘cc...’ is equivalent to Parallel SDA). IV. PERFORMANCE EVALUATION This section is dedicated to evaluate the performance of the proposed alternate SDA and to determine which disposition of search patterns achieves the best results. The UPS case study is modeled in MATLAB Simulink for simulation results TABLE I VIVADO TESTBENCH RESULTS FOR 1000 OPTIMIZATION PROBLEMS Total time [ms] Nnod / blocks Conventional SDA 560.21 10185438 Parallel SDA 2 376.65 6098122 Alternate SDA 2 362.01 5839279 Parallel SDA 4 260.81 3934207 Alternate SDA 4 242.19 3612578 Parallel SDA 8 181.82 2477722 Alternate SDA 8 165.67 2153083 1.4 1.6 1.8 2 1 2 3 1.4 1.6 1.8 2 1 2 3 a b sw sw Fig. 4. Steady-state performance as a measure of the voltage THD for Np=6. a) fs= 20 kHz and Nmax nod =450. b) fs= 25 kHz and Nmax nod =280. and the same laboratory prototype presented in [9] is used for direct experimental comparison1. To evaluate performance, the main metrics of merit selected for the study will be: Optimality Op(%), defined as the percentage of successfully found optimal solutions in the total amount of optimization problems computed during simulation, average final solution cost, dµ, which is computed for the totality of the simulation time and output voltage total harmonic distortion, THD (%). In the first test, Npis set as 6. To assess the behavior of each search strategy under the SDA constrained operation, results are depicted in function of the maximum number of explored nodes per block Nmax nod in Fig. 3. The evaluated range of Nmax nod values is selected according to the computational characterization of the real-time implementation. Each parallel block in the design takes 5 clock cycles to carry out all the necessary operations to explore one node. For a 100 MHz clock, Nmax nod = 500 is equivalent to allotting 25 µs for the optimization phase. As the computational limit is lowered, all strategies provide worse optimality and solutions with larger cost. However, different search strategies can render better 1Lf= 2 mH, Cf= 50 µF, Load (resistor, inductor) (30 Ω, 20 mH), vdc = 700 V, fs= 20 kHz. Output voltage sinusoidal reference with fundamental frequency 50 Hz and 230 V RMS. This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2023.3312421 © 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS -400 -200 0 200 400 Three-phase output voltage and reference 100102 -20 0 20 IEC 62040-3 dynamic performance Class 1 -10 0 10 Three-phase output current IEC 62040-3 Levels for Individual Harmonics 5101520253035 0 2 4 6 IEC 62040-3 THDvo = 2.219 % -400 -200 0 200 400 Three-phase output voltage and reference 100102 -20 0 20 IEC 62040-3 dynamic performance Class 1 -10 0 10 Three-phase output current IEC 62040-3 Levels for Individual Harmonics 5101520253035 0 2 4 6 IEC 62040-3 THDvo = 1.895 % 0 10 20 30 40 0 10 20 30 40 0 10 20 30 40 0 10 20 30 40 ab Fig. 5. Experimental results for Np= 7 and fs= 20 kHz. Parameter λis selected to fix ¯ Fsw = 1.5 kHz and Nmax nod =400. Top figures show the threephase output voltage and reference. Bottom figures show the three-phase output current. a) 8 SDA. b) 8 alternate SDA. performance under constrained operation. As can be seen in Fig. 3-a) and b), the alternate SDA provides noticeable improvements in both optimality and cost. It is possible to achieve better results with the same amount of parallel blocks, or obtain similar results with an inferior amount. Thus, the alternate SDA can be used to lower resource consumption or increase performance. In Fig. 3-c) and d), several dispositions for the alternate SDA are evaluated. As can be seen, the results are generally similar. However, search pattern ‘ccccrrrr’ tends to provide slightly better optimality. For this reason, this disposition will be selected for the experiments. Other operating points are evaluated in Fig. 3-e) and f). In these simulations, Nmax nod is selected as 300, and λis tuned to achieve several different ¯ Fsw. Similarly, the alternate SDA improves efficiency as it consistently yields better optimality and lower cost in comparison to parallel SDA. Secondly, the computational aspect will be evaluated. A benchmark in the Xilinx Vivado simulation tool is established, where the different algorithms are allowed to explore as many nodes as required to complete the search process. For this test, 1000 optimization problems of size Np= 7 are randomly generated. The initial solution is selected as a null vector in all cases. Through this approach, it can be measured how many nodes and how much time each algorithm will take to successfully complete all the problems. Results are represented in Table I. As can be seen, the alternate SDA overall reduction in calculation time and explored nodes per parallel block is around 10 %. In the third test, experiments are carried out with a laboratory UPS prototype. Steady-state output voltage THD is measured and represented in Fig. 4 for different ¯ Fsw. As can be seen, optimality and cost improvements translate into better THD. Transient-state waveforms are illustrated in Fig. 5. Parameter λhas been chosen heuristically to achieve the desired ¯ Fsw. Additionally, validation is offered in terms of the IEC 62040-3 standard for UPS. As can be seen, alternate SDA strategies can achieve better THD and slightly better deviation metrics, making it easier to meet the standard requirement for a given switching frequency. This fact can be observed in the summary of the IEC standard assessment of the alternate SDA method for different Npand ¯ Fsw values shown in Table II. TABLE II IEC 62040-3 ASSESSMENT FOR DIFFERENT NP Dyn. Class 1 (Y/N) Harm. levels (Y/N) THD (%) ¯ Fsw (kHz) 1.8 / 2 1.8 / 2 1.8 / 2 Np= 1 NO / NO NO / NO 2.64 / 2.30 Np= 2 NO / NO NO / NO 2.00 / 1.72 Np= 3 NO / YES NO / NO 2.13 / 1.78 Np= 4 YES / YES NO / NO 1.70 / 1.47 Np= 5 YES / YES NO / YES 1.59 / 1.39 Np= 6 YES / YES YES / YES 1.47 / 1.31 Np= 7 YES / YES YES / YES 1.58 / 1.37 In this table, each Np-¯ Fsw pair is evaluated favorably or negatively for the specific dynamic performance or harmonic levels criteria in the standard. As can be observed, a prediction horizon of 5 or 6 can be necessary to meet the standard requirements for ¯ Fsw ≤2. Performance for such horizons can be largely boosted by an alternate SDA as has been shown in the previous results. V. CONCLUSION In this work, an alternate SDA is proposed to solve the LPHFCS-MPC problem. The parallel SDA design is improved by imposing parallel blocks with different search patterns. This allows one to explore a greater diversity of lattice points. Simulation and experimental results confirm the performance benefits of the proposed strategy. Optimality improvements are shown to translate into better control performance, as demonstrated by simulation and experimental results carried out in an UPS. REFERENCES [1] S. Vazquez, J. Rodriguez, M. Rivera, L. G. Franquelo, and M. Norambuena, “Model predictive control for power converters and drives: Advances and trends,” IEEE Trans. Ind. Electron., vol. 64, no. 2, pp. 935–947, Feb. 2017. [2] P. Karamanakos and T. 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Citation information: DOI 10.1109/TIE.2023.3312421 © 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.