A modular CMOS analog fuzzy controller

A Modular CMOS Analog Fuzzy Controller Fernando Vidal-Verd6 **, Rafael Navas ** **Dto. de Electr6nica Universidad de Milaga Complejo Tecnol6gic0, Campus de Teatinos, MBlaga. 2907 I-Milaga. SPAIN email: vidal@ ctima.uma.es Abstract The low/medium precision required for many fuuy applications makes analog circuits natural candidates to design @zzy chips with optimum spee&power figures. This paper presents a sixteen rules - two inputs analog fizzy coniroller in a CMOS Ipm single-poly technology based on /milding blocks implementations previously proposed by the authors [I]. However, such building blocks are rearranged here to get a highly modular architecture organized from two high level blocks: the label block and the rule block. In addition, sharing of membership function circuits allows a rompact design with low area and power consumption and its highly modular architecture will permit to increase the tv!umber of inputs and rules in future chips with hardly design effort. The paper includes measurements from a sil- ,icon prototype of the controller. Jl. Introduction There are numerous applications where an input vector x = (xl, x2, ... x~)~ has to be non-linearly mapped onto a scalar variable y = f(x)’. For instance, this problem is found in associative memories and pattern recognition, in control, or behind the modeling of knowledge in intelligent decisionmaking systems. In many of these applications the mathematical structure of the function is unknown or ill-defined and the nonlinear mapping must be obtained from a collection of input-output data pairs and/or based on the observation of some local features of the system operation. This is intrinsic to the very operation of fuzzy logic systems [2] which employs fuzzy inference to obtain a multidimensiional function (called response map, or response surjace) that maps x = (xl, x2> ... x,,,)~ into a scalar output y. This response map can be represented as an expansion in terms of fizzy basis function. each corresponding to one of the 1. Each component of an output vector y = (y1, y2, .__ yQ)Tis treated in this paper as a different single-output systems, that is, y, = J(x), 1 SjSQ. Angel Rodriguez-VAzquez * *Dept. of Analog and Mixed-Signal Circuit Design Centro Nacional de Microelectr6nica-Universidad de Sevilla Edificio CICA, C/Tarfia s/n, 41012-Sevilla, SPAIN email: [email protected] local pieces of knowledge from which the global operation of the system is built. This resembles the process of creating a function that fits a set of interpolation data -- a wellknown problem in approximation theory. Local pieces of knowledge in fuzzy systems are expressed by mean of logic rules in natural language like, IF x1 is Ail AND x2 is Ai2 AND ... xM is AiM THEN Consequent Action The particular case of fuzzy inference that uses constant terms (singletons) at the consequent of each rule.is very suitable for hardware implementations because of its simplicity [3]. This procedure obtains y = f(x) as, y(x) = c Wi*(X)Yi*, i= l,N min{sjl (x1)’si2(x2j;...,siM(x~) 1 (1) W.*(X) = - mzn (Si] (x,) 3 Si? (X?) > ...> SjM (x,) 3 i := 1,N where wi*(x) are the normalized multidimensional fuzzy basis functions which corresponds to normalized rule antecedent outputs, sii(xj> are the membership functions associated to linguistic labels A& and yi* are the singleton values at the consequent of each rule. A conceptual architecture to perform (1) is depicted in Fig.1 where processing is realized through five layers associated to operators in (1). When high speed/power ratios are required, the use of special ASICs is recommended [4]. Digital implementa tions of special purpose ASICs achieve higher resolution than their analog counterparts, and many developing tools make them attractive for fast design and prototyping. Analog implementations are usually more costly in design time, and they achieve lower resolution, up to 9 bits in digital standard technologies [5], but get better speedpower ratios and their input-output delay, which is actually the most important parameter in real time control, is usually smaller. Moreover, the electronic devices versatility when the differ- 0-7803-3796-4/97/$10.0001997IEEE 647 FUZZ-IEEE'97 Fig. 1 : Neuro-Fuzzy Controller Chip Conceptual Architecture; inset: bell-shaped membership function. ent operating regions are exploited, allows to get a higher efficiency from them in analog than in digital implementations, thus saving area. The main handicap for the analog implementations, their limited resolution, does not seem a major problem in fuzzy control applications, which often do not need more than 4 bits of resolution [3]. Finally, analog implementations save the A/D and D/A converters used in the interfaces to sensors and actuators, which implies lower delay and cost in area than digital implementations. An implementation of Fig. linto silicon was presented by the authors in [l]. Such circuit does not share membership function circuits among rules, thus it allows flexible partitions of the input space. Here, instead of a direct translation of Fig.1 into silicon, circuitry is distributed in order to achieve a high modularity. Thus, minimum and normalization circuits have been split into cells, which ape further grouped into two blocks named label block and rule block. On the other hand, membership functions are shared among different rules, thus there is only one membership function for each label in the rule set, and there is only a set of labels per input that determines its partition. This strategy has two consequences: We can generate only grid partitions of the universe of discourse, that is, the partition in each separate dimension or input determine the partition in the overall multidimensional input space. Therefore, scatter and tree partitions [6] are not allowed. Membership function circuits can be shared among different rules and do not have to be replicated, thus we save area and power consumption. 0 In the following, we describe the label and rule high level building blocks as regard to the operators in Fig. 1 and their implementation. Then we will see how to interconnect these building blocks to build a highly modular controller and will discuss some performance aspects. Finally, we present some results from a prototype of a sixteen-rules two-inputs controller. 2. Label Block The tasks realized in the label block are related to the computation of the rule antecedent output from the system input, which corresponds to the operators involved in the numerator of the right part of equation (l), or to the first and second processing layers in the Fig.1. The rule antecedent defines a fuzzy set over the multidimensional input space, thus it provides a membership value to the multidimensional input vector. Such membership value is obtained by selecting the minimum membership value among those associated to each input vector component. The latter membership values are obtained by the membership function circuits, while we need a minimum circuit to compute the minimum of them. Each label block implements one membership function circuit, and the input stages of the minimum circuit for each rule that contains such label. 2.1. Membership function circuitry The circuit labeled as membership function circuit in Fig.2 obtains a bell shaped curve by adding the outputs from two cross-coupled differential pairs, thus by adding two outputs like, complement circuit maximum circuit unit cell membership function circuit Fig. 2: Label Block. 648 FUZZ- I EEE’9 7 =i,+i,, where vl=Ejl-xl and v2=xJ-E> in (2), and [3 is the larg tance factor of the tran ated to the shape and location of n (see inset of Fig.l)are the wid 2A = E,-E, 2E = EP+E, (3) at the crossover points S, S=J27;;iT (4) just a few transistors. 2.2. Minimum circuit input stage provide copies of th output to be used by but only the input U 3. Rule Block This block performs tasks to tation of the rule consequients and the YS through the center of gravity method, thus the third and fourth layers in Fig. 1. However, its input stage corresponds to the output cedent output current to be n 3.1. Minimum circuit output stage minimum circuit into an ou circuit, works in saturatio than that transistor in the input unit cells. minimum circuif output stage I ,- ,normalization unit cell Fig. 3: Rule Block. 649 FUZZ-IEEE'97 3.2. Normalization circuit unit cell An open chain CMOS normalizer circuit based on a bipolar circuit by Gilbert [SI was proposed by the authors in [ 11 to perform the normalization at the third layer of Fig. 1. Such circuit can be split into unit cells, one per rule, and a common part which consists only of a diode connected transistor and a current source. The unit cell is depicted in Fig.3 as well as this common part, which is connected in the figure with a dashed line to indicate that it is not part of the rule block, but it is implemented in a global bias box. Since normalizing operation of Gilbert's proposal lies on the translinear principle, and the circuit in [l] works above threshold, it actually realizes a non-linear transformation, where which ensures that the sum of all output currents is constant. In addition, it is a soft monotonic transformation, thus the higher the current value at an specific input, the higher its corresponding output current is. Since both previous points are the essence of defuzzyfication, whose purpose is preserving the relative strengths of the rule antecedents at output, thus the meaning of these antecedents as multidimensional fuzzy sets, and non-linear transformations are already accepted in the membership function generation, we can use the circuit in Fig3 to realize the normalization without feedback nor division, thus with better dynamic response. 3.3. Singleton weighting circuit Once the antecedent outputs are normalized, a scaling circuit is necessary to perform the weighting in (1). Since the normalization circuit provides currents, the simplest way to perform weighting is through asymmetrical current mirrors, that is through current mirrors whose input and output transistors have different sizes. Digital programmability of the singleton values is got by spliting the output transistors into binary weighted ones, and adding current switches, as depicted in Fig.3, where switches are implemented by simple MOS transistors. Then the output current is, y. I = w. inor x 2kski (7) where winor is the output current of the normalization circuit unit cell in (5) and ski are the digital signals at the current switches gates. k=O,3 4. Global controller performance and design issues The last layer in Fig.1 performs the aggregation of all rule consequent outputs. Such task can be realized in current mode just by wiring up all the rule outputs, thus the outputs of the rule blocks, by taking advantage from the Kirchhoff Current Law. In addition, a current source must be attached sometimes to this node to remove a current offset that can be introduced in the normalization circuit to improve the dynamic response. Thus, a complete controller can be obtained by proper connection of a set of rule and label blocks, as Fig4illustrates for a sixteen-rules two-inputs controller. In the following, some design considerations are made which concern to the main aspects involved in the analog design of such controller: errors, dynamic behavior, power consumption, range, and dependence on the temperature. The above presented building blocks must be designed to reduce the errors due to systematic and random causes. The first are mainly avoided by introducing cascode transistors, thus current mirrors that replicate the current sources IQ, I, and I,, are cascode current mirrors. The high output impedance that these mirrors provide improves the common mode rejection factor in the input differential pair of the membership function circuit, while the same applies for the normalization circuit. In addition to these cascode current mirrors, cascode transistors and bias voltages in the maximum circuit, the complement unit cell and the normalization unit cell are chosen to improve the dc input-output voltage matching. Singleton weighting current mirror in Fig.3 is also a cascode mirror and output branches are built x2 4 rule blocks label blocks Fig. 4: Conceptual label and rule blocks interconnection. 650 FUZZ-I EEE'9 7 with unit transistors of the same size than those in the input branch. Finally, in addition to errors due to systematic causes, there are errors due to mismatching between transistors. Large transistors and high current values are required for a good transistor matching, thus trade-offs with speed and power consumption appear. The common mode input range, closely related to the universe of discourse, of the circuit in Fig.2, thus of the whole controller is, To improve the common mode range by circuit design strategies, we have to implement the source IQ with high output voltage swing cascode current mirrors, like that depicted in the left bottom corner of Fig.2. The dynamic behavior of the controller, since there is not feedback between different blocks, is determined by the time constants associated to such blocks, thus their improvement will provide a good global dynamic response. General dynamic considerations apply to Fig.2 and Fig.3, thus better behavior for higher current values and smaller eransistors. Bias current IB is added to improve the dynamic behavior of the maximum circuit. This current is removed at maximum circuit output, which is realized without any cost because we can take advantage from the complement implementation at output. In addition, the current source IC is used to introduce another offset at the input of the normalization circuit unit cell, which is further removed at system output. Finally, current offsets can also be added in the sinzleton weighting circuit, as Fig.3 depicts with dashed current sources. With respect to the controller consumption, let us consider a controller with M inputs, N rules and L fuzzy labels whose maximum singleton value in the associated rule base is ylmax*, and is loaded with a voltage source Vload. The maximum static power consumption is featured by the previous items as, \- , + N x (IC + Ib) + 21ss I VDD + V Issyi,,,* load where Iu=21Q and VDD is the voltage supply source. Finally, as regard to the dependence on the temperature. all the building blocks except the membership function circuit have temperature independent transfer functions. The membership function circuit has a temperature dependent transfer function because of the dependence on the temperature that the differential pair has, which is caused by the large signal transconductance p in (2). However, due to the differential pair symmetry, the location and width defined in (3) are not affected by temperature changes. Electrical values associated to the logical zero and one are neither affected, because such values are given by the conditions of cut-off or full IQ current driving in the transistors of the differential pairs, and such references do not depend on the temperature. Thus, the only parameter which is affected by temperature changes is the membership function slope, which depends on p (see eq.(4)). From a global point of view, this means that the slope of the generated function between interpolation points will vary when temperature does, as Fig.5 illustrates for a controller with four rules, where errors below 7.5% are measured in a temperature range of 100 Celsius degrees. As a consequence, the interpolation smoothness will vary when the temperature changes, but the interpola.tion points are not affected if the membership functions are wide enough to saturate in the whole temperature range. c--\ ' ' , , ' ' 60.0"~ t Fig. 5: Illus1:ration of dependence on temperature 5. Chip description and experimental results Fig.6(a) shows a microphotography of a sixteen-rule two-inputs fuzzy controller based on the previously presented high level building blocks, while Fig.6(b) depicts its physical architecture. The label blocks outputs are connected to inputs of rule blocks through a ring bus. Digital values to program the output current mirror and then the singleton values are stored in a shift register which is the chip internal memory element and is serially programmed through two pads. Apart from digital programmability of singleton values, width and location of membership func- Fig. 6: Chip rnlcrophotography (a) and architecture (b). 65 1 FUZZ-IEEE‘97 cally programmable by setting two and E,2 in Fig.2, associated to membership value 0.5 (crossover points) in the membership cuit related to each label. Finally, bias signals generated internally and shared by different y are implemented in a biasing box together with the shared parts of the normalization circuit. The figures Fig.7(a) and Fig.7(b) show two output surfaces generated by the presented chip. The bias signals are Is,=37pA, while the voltages E, associated to were fixed to obtain a uniform lattice partition of pace. The circuit was loaded with a constant voltzation circuit. Singletons are set to V,,=SV, V,,=OV, IQ=ISpA, IB=IOpA, I&l.5pA, introduced in the decimal values 1 obtained with different ut, while power consumption is imulations (30 iterations) eter mismatching among ly, input voltage range is p without pads is 1 .6mm2. s of the current mirror output, and in the outby inserting the chip efesences Engine In Nonlinear Ana- a Fuzzy Logic Control”. g Properties of MOS Tran- State Circuits, Vol. 39, pp 1433-1440, June 1 1989. a translinear view 652