Rectification, amplification and switching capabilities for energy harvesting systems: power management circuit for piezoelectric energy harvester

Universidade do Minho Escola de Engenharia Departamento de Eletrónica Ana Cláudia Rodrigues Ferreira Rectification, amplification and switching capabilities for energy harvesting systems Power management circuit for piezoelectric energy harvester July 2020 Universidade do Minho Escola de Engenharia Departamento de Eletrónica Ana Cláudia Rodrigues Ferreira Rectification, amplification and switching capabilities for energy harvesting systems Power management circuit for piezoelectric energy harvester Master dissertation Master Degree in Biomedical Engineering Dissertation supervised by Tao Dong José Correia July 2020 DIREITOS DE AUTOR E CONDIÇÕES DE UTILIZAÇÃO DO TRABALHO POR TERCEIROS Este é um trabalho académico que pode ser utilizado por terceiros desde que respeitadas as regras e boas práticas internacionalmente aceites, no que concerne aos direitos de autor e direitos conexos. Assim, o presente trabalho pode ser utilizado nos termos previstos na licença abaixo indicada. Caso o utilizador necessite de permissão para poder fazer um uso do trabalho em condições não previstas no licenciamento indicado, deverá contactar o autor, através do RepositóriUM da Universidade do Minho. Licença concedida aos utilizadores deste trabalho ii ACKNOWLEDGEMENTS First of all, I want to thank my project supervisor at the University of South-Eastern Norway, Professor Tao Dong, for all the support, supervision and motivational speeches. Those were imperative to the progress of my master’s thesis. My appreciation goes to my supervisor at the University of Minho, Professor José Correia, throughout my academic period, his lectures, the relationship with his students and always being available for me. I am grateful for the contact with Professor Zhaochu Yang from Chongqing Technology and Business University (CTBU), and Ph.D. Haakon Karlsen from Sensovann AS, whose wise advice and contact with the industry sector gave me skills regarding project management and proposal writing. I also would like to thank Ph.D. student Rui Carvalho, whose cooperation in the project was valuable to its development through interdisciplinary discussions and motivation. Acknowledgment also goes to Ph.D. Marino Maciel for the thorough manuscript review. I want to thank all my research colleagues at the University of South-Eastern Norway for the assistance and support throughout my studies. Likewise, I have to thank all my fellow course colleagues and friends at the University of Minho. Together we overcame all the adversities through our academic years. My friends should also be mentioned here since their support and motivation helped me to get where I am today. Finally, a special thanks to my parents and sister, who were always by my side, encouraging me to pursue my dreams. Further thanks to all my family. Thank you! Tusen takk! Obrigada! iii STATEMENT OF INTEGRITY I hereby declare having conducted this academic work with integrity. I confirm that I have not used plagiarism or any form of undue use of information or falsification of results along the process leading to its elaboration. I further declare that I have fully acknowledged the Code of Ethical Conduct of the University of Minho. iv RESUMO Para combater a dependência dos dispositivos eletrónicos relativamente ás baterias é necessário um novo sistema energético, que permita prolongar o tempo de vida útil dos mesmos. Energy Harvesting é uma tecnologia promissora utilizada para alimentar dispositivos sem bateria. Este trabalho consiste na realização de componentes empregáveis num circuito global para extrair energia a partir ds vibrações de um piezoelétricos com baixo consumo de energia e alta eficiência. Os níveis de potência e voltagem gerados pelo transdutor piezoelétrico são relativamente baixos, especialmente em sistemas de pequena escala, por isso requerem cuidado extra relativamente ao consumo de energia e eficiência dos circuitos. A principal contribuição deste trabalho é um sistema apropriado para amplificar, retificar e alternar o sinal instável proveniente de uma fonte de energy harvesting. Os componentes do sistema são implementados com base na tecnologia CMOS com 0.13𝜇𝑚. Um interruptor analógico capaz de modelar a frequência do sinal entre 1𝐻𝑧e1𝑀𝐻𝑧e estável perante variações de temperatura, é implementado. O circuito tem um excelente isolamento de −111.24𝑑𝐵, devido a uma resistência OFF de 520.6𝑀Ω. O amplificador implementado é apto a amplificar um pequeno sinal com um ganho de 42.56𝑑𝐵e baixo consumo. O sinal de saída é satisfatoriamente amplificado com uma voltagem de offset de 8𝜇𝑉. Um retificador ativo de dois estágios com uma nova arquitetura é proposto. A eficiência de conversão de energia atinge os 40.4%, com uma eficiência de voltagem até 90%. O retificador consome pouca energia, apenas 17.7𝜇𝑊, incorporando um comparador de 113.9𝑛𝑊. Os resultados validam as exigências energéticas do circuito, que pode ser usado para outras aplicações similares no campo biomédico, industrial e comercial. Palavras-chave: Interruptor analógico, CMOS, Energy Harvesting, Rectificador, Amplificador. v ABSTRACT A new energy mechanism needs to be addressed to overcome the battery dependency, and consequently extend Wireless Sensor Nodes (WSN) lifetime effectively. Energy Harvesting is a promising technology that can fulfill that premise. This work consists of the realization of circuit components employable in a management system for a piezoelectric-based energy harvester, with low power consumption and high efficiency. The implementation of energy harvesting systems is necessary to power-up front-end applications without any battery. The input power and voltage levels generated by the piezoelectric transducer are relatively low, especially in small-scale systems, as such extra care has to be taken in power consumption and efficiency of the circuits. The main contribution of this work is a system capable of amplifying, rectifying and switching the unstable signal from an energy harvester source. The circuit components are designed based on 0.13𝜇𝑚Complementary Metal-Oxide-Semiconductor (CMOS) technology. An analog switch, capable of driving the harvesting circuit at a frequency between 1𝐻𝑧and 1𝑀𝐻𝑧, with proper temperature behaviour, is designed and verified. An OFF resistance of 520.6𝑀Ωand isolation of −111.24𝑑𝐵, grant excellent isolation to the circuit. The designed voltage amplifier is capable of amplifying a minor signal with a gain of 42.56𝑑𝐵, while requiring low power consumption. The output signal is satisfactorily amplified with a reduced offset voltage of 8𝜇𝑉. A new architecture of a two-stage active rectifier is proposed. The power conversion efficiency is 40.4%, with a voltage efficiency of up to 90%. Low power consumption of 17.7𝜇𝑊is achieved by the rectifier, with the embedded comparator consuming 113.9𝑛𝑊. The outcomes validate the circuit’s power demands, which can be used for other similar applications in biomedical, industrial, and commercial fields. Keywords: Analog Switch, CMOS, Energy Harvesting, Rectifier, Voltage Amplifier. vi CONTENTS 1Introduction 1 1.1 Motivation and Applications 1 1.2 Energy Harvesting 3 1.3 Piezoelectric Transducer 6 1.4 Project Implementation 7 1.5 Thesis Organization 9 2State of the art 11 2.1 Analog Switch 11 2.1.1 Direct Energy Transfer 12 2.1.2 Load Decoupling Interfaces 16 2.1.3 Switching Techniques Summary 20 2.2 Voltage Amplifier 21 2.2.1 Amplifier Modes 21 2.2.2 Piezoelectric Amplification Patents 23 2.2.3 Amplifier Topologies 24 2.3 Rectifier 27 2.3.1 Conventional Rectifier 28 2.3.2 CMOS Rectifier 32 3Development and Results 46 3.1 Analog Switch 46 vii viii 3.1.1 Up-conversion Technique 47 3.1.2 Management System 48 3.1.3 Features 51 3.1.4 Results 54 3.1.5 Discussion 60 3.1.6 Summary 61 3.2 Voltage Amplifier 62 3.2.1 Design and Modeling 62 3.2.2 Features 63 3.2.3 Results 64 3.2.4 Discussion 67 3.2.5 Summary 68 3.3 Rectifier 69 3.3.1 Design and Modeling 70 3.3.2 Proposed Rectifier 78 3.3.3 Results 83 3.3.4 Discussion 87 3.3.5 Summary 89 3.4 Layout Design and Fabrication 89 3.4.1 Layout Design 92 3.4.2 Chip Fabrication 93 4Conclusion 97 4.1 Conclusions 97 4.2 Future Work 98 ASupport material 110 ACRONYMS A AC Alternating Current. ADC Analog-to-Digital Converters. ASIC Application-Specific Integrated Circuit. ASSH Adaptive Synchronized Switch Harvesting. B BBM Break-Before-Make. BICMOS Bipolar CMOS. BJT Bipolar Junction Transistor. BR Bulk Regulation. C CMOS Complementary Metal-Oxide-Semiconductor. CPU Central Processing Unit. D DC Direct Current. DRC Design Rule Check. DSSH Double Synchronized Switch Harvesting. DTMOS Dynamic Threshold Voltage MOSFET. xv Acronyms xvi E EDA Electronic Design Automation. ESD Electrostatic Discharge. ESSH Enhanced Synchronized Switch Harvesting. EU European Union. EVC External 𝑉𝑡ℎCancellation. F FET Field Efect Transistor. G GBW Gain Bandwidth. I IC Integrated Circuit. IO Input and Output. IVC Internal 𝑉𝑡ℎCancellation. J JFET Junction gate Field-Effect Transistor. L LVS Layout Versus Schematic. M MBB Make-Before-Break. MBPD MOSFET Bypass PMOS Diode. Acronyms xvii MEMS Microelectromechanical Systems. MIM Metal-Insulator-Metal. MOS Metal-Oxide-Semiconductor. MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor. MR-SSHI Synchronized Switch Harvesting on Inductor using Magnetic Rectifier. N NVC Negative Voltage Converter. O OP-AMP Operational Amplifier. P P-SSHI Parallel Synchronized Switch Harvesting on Inductor. PCE Power Conversion Efficiency. PEG Piezoelectric Electrical Generator. PS-SECE Phase Shift Synchronous Electric Charge Extraction. PSRR Power Supply Rejection Ratio. PWL Piecewise Linear. R R&D Research and Development. RF Radio-Frequency. S S-SSHI Series Synchronized Switch Harvesting on Inductor. Acronyms xviii SECE Synchronous Electric Charge Extraction. SMPS Switch Mode Power Supply. SPICE Simulation Program with Integrated Circuit Emphasis. SSD Synchronized Switch Damping. SSDCI Synchronized Switching and Discharging to a storage Capacitor through an Inductor. SSHI Synchronized Switch Harvesting on Inductor. SVC Self-𝑉𝑡ℎCancellation. U ULP Ultra-Low Power. W WSN Wireless Sensor Nodes. 1 INTRODUCTION The increasing demands for powering electronic devices, such as wearable, wireless sensor networks, biomedical implants, and so forth, have led to the current extensive exploration of power harvesting devices. The goal of electronic energy harvesting interfaces is to efficiently manage the scavenged energy to enable battery-free, lowmaintenance and more eco-friendly devices, consequently allowing for more portable and lightweight electronic devices. 1.1 Motivation and Applications Microsensor networks have an energy constraint on the sensor nodes imposed by the capacity of the nodes’ battery. In order to extend the sensor lifetime, most microsensors work through a duty cycle, alternating between an active and a sleep mode, and shutdown unused components whenever possible. However, this does not remove the energy constraint by the battery. For some applications, a pure Lithium battery of 1𝑐𝑚3, capable of continuously supplying 1𝜇𝑊for five years, is enough (Calhoun et al.,2005). Nonetheless, nowadays batteries are a handicap for higher peak power and extended lifespan applications due to their low energy density and high costs (Bawa and Ghovanloo,2008), raising maintenance, complexity, and recycling issues (Guyomar,2011). In some situations, it is impractical or even impossible to change batteries. Therefore, a new approach to solve this problem involves using energy from the environment to supply devices, overcoming the previous issue, and making them self-powered and self-sufficient (Guyomar,2011). The recent increase of autonomous and efficient devices encouraged by industrial fields and personal applications has raised powering issues (Guyomar,2011). There is a need for reduced power consumption, depending on the kind of use, e.g. low power sensors consumption is around 10𝜇𝑊to 100𝜇𝑊. 1 1.1. Motivation and Applications 2 Energy harvesting has become a significant research and development topic. This technology has a massive impact on people’s life since it extends its applications in many fields, such as aeronautics, transports, civil engineering, biomedical engineer, Radio-Frequency (RF), home automation, nomad devices, and so on (Dai et al., 2015;Guyomar,2011). Its impact on the deployment of WSN and wearable electronic devices is crucial (Dai et al.,2015), allowing the information collected from the systems to be transferred to the outside world in realtime (Bawa and Ghovanloo,2008). Theoretically, those devices can have an infinite lifespan, being only limited by the lifetimes of their components. Regarding the innovations above, the biomedical field benefits extensively from this technology progress through implantable sensors (Deterre et al.,2013), sending data from inside the human body (Peters et al.,2007) and allowing monitoring patient’s health anywhere in real-time (Wong et al.,2016). Through these developments, patients can have a comfortable lifestyle, thanks to the freedom of movements due to wireless devices. Contrary to previous methods, which need for invasive procedures to replace batteries, these innovations reduce infection risk. Besides, they do not cause any discomfort or health risks to the patients (Peters et al.,2007). In this domain, the applications are widely explored, enabling the detection and treatment of diseases such as muscle paralysis and deafness (Cha et al.,2012). It can also be used to measure the physiological signals as heartbeat or blood flow sensing. Furthermore, it can record neuronal activity in patients with Parkinson or retinal prosthesis (Vakili and Golmakani,2013). Figure 1shows some of the aforementioned applications. The implementation of these technologies has notably prompted a shift in the design approach of electronic systems, introducing new challenges for system designers. It is expected that by 2024, the global market of devices powered by ambient energy accomplish a total of 2.6 billion units (Chetto and Queudet,2016). The European Commission presented the European Green Deal, the most ambitious package of measures aiming to become the world’s first climate-neutral continent by 2050. That should enable European citizens and businesses to benefit from sustainable green transition (European Commission,2019). A recent statistic on renewable energy sources in the European Union (EU) is given in Figure 2(Eurostat Statistic Explained,2020). It can be observed that the majority of countries increased the percentage of renewable sources from 2016 to 2018. For this year, 2020, most of the countries already achieve the expected goals in 2018, like Norway and Germany. Therefore, Europe is rapidly developing for a more sustainable continent. 1.2. Energy Harvesting 3 (a) (b) (c) (d) Figure 1: Biomedical applications requiring energy harvesting: (a) intra-cardiac implant placed in the heart cavity scavenging energy from regular blood pressure (Deterre et al.,2013); (b) a polyvinylidene fluoride harvester that extract energy from the arterial wall deformation (Yang et al.,2018); (c) implanted arterial cuff power source integrated into a selfpowered blood pressure sensing system (Potkay and Brooks,2008) and (d) flexible retinal implant device (Hwang et al.,2015). 1.2 Energy Harvesting Energy harvesting has long been known as the process of scavenging energy available from the surrounding environment and converts it into electrical energy. Several types of sources can be used to harvest energy (Ali et al.,2014), and those are divided into two groups according to their characteristics (Dang et al.,2012). Firstly, the natural sources that are available directly from the environment, such as RF, solar power, thermal gradients, in particular geothermal heat, and mechanical vibration (Maiorca et al.,2013). Secondly, the artificial sources that are not generated by nature and result from human or system activities, such as body motion, breathing, blood pressure, and system vibration during their operational mode (Priya,2007). A comparison of power densities from some energy harvesting mechanisms for a 10-year lifetime is given in Figure 3(Roundy et al.,2003;Roundy et al.,2005;Cao et al.,2007). The highest power density comes from solar cells in direct sunlight - Figure 3(E). However, the best conditions for extracting solar energy are not available whenever (night) and everywhere because of climate changes. In areas with cloudy weather, Figure 3(F), where the light is not maximum, or even at 1.2. Energy Harvesting 4 FI PT DK SI LT ES HR DE IT BG IE PL NL BE MT 0 10 20 30 40 50 60 Percentage (%) 2016 2018 2020 Target Figure 2: Overall share of energy from renewable sources in some the European Union member states (Eurostat Statistic Explained,2020). an indoor environment, Figure 3(G), as dim offices, the power density decreases drastically from 15000𝜇𝑊/𝑐𝑚3 to 6𝜇𝑊/𝑐𝑚3. Thermoelectric sources, Figure 3(D), scavenge power from thermal gradients with 15𝜇𝑊/𝑐𝑚3 at a 10∘𝐶gradient. Nonetheless, since there are sources more accessible to harvesting energy and with higher values, this method is considered inadequate. Nevertheless, the implemented energy transducer depends on the available ambient energy to harvest. Therefore, Table 1displays the correlation between the different ambient sources and what kind of transducer should be employed (Mateu et al.,2014). Table 1: Transducers for different ambient energy sources. Ambient Energy Source Transducer Light Photovoltaic cell Mechanical Piezoelectric, electromagnetic, electrostatic Thermal Thermoelectric generator Among the numerous sources, mechanical vibration energy is commonly explored since it is available in small-scale systems (Guyomar,2011;Maiorca et al.,2013). Common day activities, such as walking produces energy with a power density of 850𝜇𝑊, through mechanical vibrations, by applying a force of 2500𝑁on a knee (Seunghyun,2013). The best-known methods of transduction technologies for this source are piezoelectric, 1.2. Energy Harvesting 5 A B C D E F G 0 100 200 300 400 14900 15000 Power Density ( W/cm3) Power Harvesting Methods Figure 3: Comparison of energy sources with a fixed level of power generation (Roundy et al.,2003;Roundy et al.,2005; Cao et al.,2007). (A), (B) and (C) are vibration piezoelectric, electromagnetic and electrostatic, respectively; (D) is a thermoelectric source; (E), (F) and (G) are solar energy directly from sunlight on a clear weather day, on a cloudy day and indoor, correspondingly. electromagnetic, or electrostatic (Figure 3). Those are coupled to the extraction structure to convert vibrations into electrical energy (Maiorca et al.,2013). In Figure 3(C), with 50𝜇𝑊/𝑐𝑚3, is the electrostatic generation. Its operation consists of two conductors moving in relation to each other, separated by a dielectric. When the conductors move, the energy stored changes and the mechanical energy is converted into electrical energy (Roundy et al.,2003). These converters, combined with Microelectromechanical Systems (MEMS) processing technology, offer an effective method to obtain close integration with electronics and the potential to scale down to smaller sizes. These advantages are more significant for electrostatic converters than for the others. Nevertheless, the requirements of a separate voltage source to initiate the conversion process and the difficulties in their implementation constitute drawbacks for this transducer (S.P. Beepy,2006). The transducers represented by Figure 3(B) are ruled by the principle of electromagnetic induction defined by Faraday’s law (Singh,2011). A magnetic flux variation is created due to relative motion between a magnet and a coil, inducing an electromotive force across the coils. The corresponding energy to the motion damped is transduced into electrical energy (Kiziroglou and Yeatman,2012). Although the energy is usually implemented for rotational movement, in energy harvesting sources, the free motion does not often come from rotational. In 1.3. Piezoelectric Transducer 6 literature, no inherent advantage is pointed to electromagnetic transducers over the other converters (Roundy et al.,2003). 1.3 Piezoelectric Transducer Despite all the transducers above mentioned, this thesis project focuses on piezoelectric materials. A piezoelectric crystal suffers a charge separation due to a mechanical strain in the dielectric material, that is converted into electrical energy associated with the presence of electric charges. Thus, mechanical stress produces a voltage in the piezoelectric element (Roundy et al.,2003). Generally, Figure 4describes a vibration energy harvester. There is a special interest in piezoelectric elements thanks to their high energy densities and potential integration (Guyomar,2011), exhibiting better performance than others (Maiorca et al.,2013). Even though they are more difficult to integrate into a microfabrication process than the other technologies, a recently study (Roundy et al.,2003) proves it is possible to integrate a piezoelectric transducer into a MEMS package. In this way, it becomes the premium option for the design of miniaturized and self-power devices (Guyomar,2011). The efficiency of the conversion process from vibration into electric energy depends on the method of applying the oscillating stress onto the piezoelectric and material parameters (Priya, 2007). Figure 4: General schematic of a vibration piezoelectric energy harvester. The equations (1) and (2) describe the mechanical and electrical behaviour of piezoelectric materials (Roundy et al.,2003). Assuming that 𝛿is the mechanical strain, 𝜎the mechanical stress, Y is the Young’s modulus, also known as elastic modulus, used to describe stiffness of materials, D the electrical displacement, which is the charge density, E the electric field, 𝜀the dielectric constant, and d the piezoelectric strain coefficient. 𝛿=𝜎 𝑌+𝑑⋅𝐸 (1) 2.1. Analog Switch 13 Piezoelectric L Rectifier CSRL V S Figure 8: Circuit schematic of the P-SSHI rectifier. In both structures, the switch S is closed when the voltage generated by the piezoelectric transducer (V) reaches an extremum. In other words, the switch closes at the maximum and minimum of the mass displacement, and is kept close until a full voltage inversion on the piezoelectric transducer is achieved. The voltage inversion occurs if the switching period (𝑡𝑖) corresponds to half of the pseudo-period of the electrical resonant circuit (Equation 3) shaped by the capacitance of the piezoelectric (𝐶0) and the inductor (Garbuio et al.,2009). 𝑡𝑖=𝜋⋅√𝐿⋅𝐶0(3) However, this inversion is not perfect as a result of the internal inductor losses, and it is characterized by the inversion coefficient 𝛾defined by Lallart et al. (2011) as: 𝛾≈𝑒−2⋅𝜋 𝑄𝑖,(4) assuming that 𝑄𝑖is the electrical quality factor of the circuit. A coil has an inductance (L) when the current flows through the coil and changes at a rate (di/dt) (Singh,2011), inducting a voltage (𝑉𝐿) expressed according to Equation 5. 𝑉𝐿=−𝐿⋅𝑑𝑖 𝑑𝑡 (5) The relationship between self-inductance and the number of turns (N) for a single coil can be given as: 𝐿=𝑁⋅Φ 𝐼,(6) admitting that Φis the magnetic flux and I the current. The coefficient of self-inductance also depends on design features, such as length, number of turns, and size. Therefore, for a coil, the magnetic flux produced in its inner core is equal to: 2.1. Analog Switch 14 Φ=𝐵⋅𝐴, (7) where B is the flux density, and A is the cross-section area. The magnetic induction of a long solenoid coil with N number of turns per meter length in the inner core is given as (Singh,2011): 𝐵=𝜇⋅𝑁⋅𝐼 l,(8) where 𝜇is the permeability of the core material and l is the length of the coil, according to Faraday’s Law, any change in the magnetic flux linkage produces a self-induced voltage in a single-coil as described in Equation 9 (Wadhwa,2005). 𝑉𝐿=𝑁⋅𝑑Φ 𝑑𝑡 =𝜇⋅𝑁2⋅𝐴 l⋅𝑑𝑖 𝑑𝑡 (9) The operation principles of the interfaces are slightly different. In the P-SSHI, after the extraction of energy, the voltage is inverted, albeit, in S-SSHI, these two processes happen simultaneously. The Synchronized Switch Damping (SSD) is the effect of the voltage inversion, affecting the overall conversion efficiency, due to an electrical attenuation that opposes the mechanical vibration on the piezoelectric material. This is the main problem of both interfaces (Badel et al.,2006). Synchronized Switch Harvesting on Inductor using Magnetic Rectifier Synchronized Switch Harvesting on Inductor (SSHI) can also be achieved by replacing the switching inductor by a transformer, as exhibited in Figure 9, and it is called Synchronized Switch Harvesting on Inductor using Magnetic Rectifier (MR-SSHI). Piezoelectric Rectifier CSRL V S1S2 Figure 9: Circuit diagram of the MR-SSHI. The transformer has two primary windings in series with unidirectional switches, 𝑆1and 𝑆2, and one secondary winding connected to the rectifier (Garbuio et al.,2009). The two primary coils are connected with inverse polarity, to guarantee the secondary side has a proper charge flow for energy extraction. When the voltage on 2.1. Analog Switch 15 the piezoelectric transducer is at its maximum, the switch 𝑆1conducts (Lallart et al.,2011). Oppositely, the switch 𝑆2leads when the transducer voltage is at its minimum. Thereby the electrical energy flowing through the transformer is converted into magnetic energy. Owing the secondary windings, this energy is converted back to electrical energy and finally stored on the storage capacitor (𝐶𝑆) and the load resistor (𝑅𝐿) (Lallart et al.,2011). The set-up transformer allows an artificial change in the load seen by the piezoelectric element, since the coupling factor is chosen to be higher than 1, which increases the transducer voltage. Therefore, this technique is suitable to extract energy from reduced input power levels (Guyomar,2011). Hybrid Synchronized Switch Harvesting on Inductor As the name suggests, Hybrid SSHI, is the combination of two techniques, MR-SSHI and P-SSHI, as represented in Figure 10, taking advantage of their properties. Thus, it extracts energy in both the inversion and conduction phases (Lallart et al.,2011). S2 S1 V RL CSRectifier Piezoelectric D Figure 10: Schematic of the Hybrid SSHI rectifier. The switch control works accordingly to the output voltage on the piezoelectric transducer. In such a way that, when the output voltage on the piezoelectric transducer is at its maximum, 𝑆1is closed. On the contrary, if the transducer voltage is at its minimum, the switch 𝑆2is closed. The current should flow from the piezoelectric source to the storage capacitor. For this reason, a diode (D) is implemented to ensure this flow and avoiding current backflow (Anna et al.,2018). Both P-SSHI and MR-SSHI are operating when the maximum voltage across the piezoelectric transducer is higher than the output voltage from the rectifier; conversely, only MR-SSHI is operating. The MR-SSHI rectification technique is manly effective for high load values, howbeit the P-SSHI is mostly useful for middle values of the connected load (Garbuio et al.,2009). Even though this technique does not improve the conversion enhancement, it endures extracting energy four times per period, as a result of working in both the inversion and conduction phases. The scavenge energy is 2.1. Analog Switch 16 double in a period compared to the previous SSHI interfaces. Thereby, it widens the bandwidth of the load and still having relative independence from it. According to Lallart et al. (2011), regarding the maximal harvested power, this technique features the same power limit as previous approaches. Nonetheless, its performance is better than both methods that integrate it separately. Moreover, the hybrid SSHI technique leads to a significant gain in terms of harvested power. 2.1.2 Load Decoupling Interfaces Synchronized Switching and Discharging to a storage Capacitor through an Inductor The circuit depicted in Figure 11 is the Synchronized Switching and Discharging to a storage Capacitor through an Inductor (SSDCI) interface (Guyomar,2011). S Piezoelectric L Rectifier CSRL V D Figure 11: Circuit diagram of the SSDCI rectifier. In this approach, the rectifier is directly connected to the piezoelectric element to prevent an electrical attenuation from the current flow. The principle of this method consists of transferring the energy available on the piezoelectric element to a storage capacitor (𝐶𝑠) through an inductor (L). In this case, the switch S is closed anytime the voltage generated by the piezoelectric transducer reaches the maximum and minimum values. When the piezo-voltage equals zero, the rectifier stops the switching process. However, there is still energy in L, which is conveyed to 𝐶𝑠. Nevertheless, the circuits can also perform as a S-SSHI for high load values, since the piezoelectric voltage does not reach zero. Synchronous Electric Charge Extraction The Synchronous Electric Charge Extraction (SECE) technique is illustrated in Figure 12. Identical to the previous methods, the switch S remains open for most of the vibration period excepted if the piezoelectric voltage is at its maximum or minimum value. During the time the switch is closed, it is charging the inductor (L). Howbeit, while the switch is open, the inductor’s energy accumulated is conveyed to the load stage (Tang and Yang,2011). 2.1. Analog Switch 17 D V RL CS Rectifier L Piezoelectric S Figure 12: Schematic of the SECE and the PS-SECE recifiers. The SECE technique is independent of changes in the load. Besides, this method is intrinsically self-adaptive to the environment, even in the case of random vibrations. The switch S prevents a direct connection between the output load and the piezoelectric device for most of the period. Thereby, the impedance seen by the piezoelectric element is almost constant (Guyomar,2011). The critical value given by the product of the squared coupling coefficient (𝑘2) by the mechanical quality factor (𝑄𝑀) works as a threshold value. Above 𝑘2⋅𝑄𝑀, the maximum energy that can be extracted starts to decrease. Moreover, using the SECE technique, it is beyond to control the trade-off among energy extraction and the damping effect (Tang and Yang,2011). As reported by Lefeuvre et al. (2017), the amount of energy given by the SECE rectifier (𝑊𝑆𝐸𝐶𝐸), at each closing of the switch is described in accordance to Equation 10. 𝑊𝑆𝐸𝐶𝐸=1 2⋅𝐶𝑜⋅𝑉2(10) To improve the drawback aforementioned, Lefeuvre et al. (2017) proposed the Phase Shift Synchronous Electric Charge Extraction (PS-SECE) technique, also represented in Figure 12. The PS-SECE differs from the SECE approach in the switch control process, closing the switch triggered by the phase-shift (𝜙). Equation 11 describes the energy extracted from the piezoelectric element, 𝑊𝑃𝑆−𝑆𝐸𝐶𝐸, at each time the switch is closed. 𝑊𝑃𝑆−𝑆𝐸𝐶𝐸=1 2⋅𝐶𝑜⋅𝑉2 𝜙(11) As a result, the damping effect is controlled by varying the phase shift of the switching signal. This indicates the phaseshift can be used as a tuning parameter to control the converted power (Lefeuvre et al.,2017). Related to Equation 10, in Equation 11 the circuit losses are neglected. 2.1. Analog Switch 18 Double Synchronized Switch Harvesting The Double Synchronized Switch Harvesting (DSSH) technique is a result of combining the S-SSHI and SECE rectifiers, as depicted in Figure 13 (Lallart et al.,2008). S1 V RL Cint Rectifier L1 Piezoelectric CS S2 L2 D Figure 13: Circuit schematic of the DSSH, ESSH and ASSH rectifiers. Analogous to SECE, the harvested power is almost independent of the connected load. In order to control the energy flow, two switches, 𝑆1and 𝑆2, and a diode D, are implemented on the circuit. The energy available on the piezoelectric is driven to the inductor 𝐿1and the intermediate capacitor 𝐶𝑖𝑛𝑡, using the remaining energy for the inversion process, while 𝑆1is closed and 𝑆2opened. Then, the operating mode goes inversely, opening 𝑆1 and closing 𝑆2, and the energy is transferred from 𝐶𝑖𝑛𝑡 to the inductor 𝐿2. Finally, the energy is passed from the 𝐿2to the storage capacitor 𝐶𝑠and the load resistor, 𝑅𝐿. Tuning the ratio between 𝐶𝑖𝑛𝑡 and the piezoelectric element capacitance is an advantage of the DSSH technique over the SECE. This allows controlling the trade-off set by the amount of harvested energy and the damping effect. Enhanced Synchronized Switch Harvesting The DSSH can be further enhanced by the Enhanced Synchronized Switch Harvesting (ESSH) technique, which circuit schematic is represent in Figure 13. Since the circuit topology is the same, the difference between ESSH and DSSH is at the small amount of energy leaved on 𝐶𝑖𝑛𝑡by ESSH (Shen et al.,2010). Usually, the switch 𝑆1is opened and is only closed for a brief time when the voltage generated by the piezoelectric element reaches its maximum or minimum, charging 𝐶𝑖𝑛𝑡. Differently, the switch 𝑆2is periodically closed, when the voltage drop across 𝐶𝑖𝑛𝑡exceeds a pre-set value, charging the inductor 𝐿2. Otherwise, if the voltage drop across 𝐶𝑖𝑛𝑡is below the pre-set value, the switch 𝑆2opens, and the energy stored in 𝐿2is conveyed to the storage stage (Shen et al.,2010). Comparing to the DSSH,ESSH technique has better control of the abovementioned trade-off and lower sensitivity to a mismatch in the capacitance ratio (Anna et al.,2018). 2.1. Analog Switch 19 Adaptive Synchronized Switch Harvesting Another approach to optimize the ESSH technique is the Adaptive Synchronized Switch Harvesting (ASSH), also represented in Figure 13, that is designed for multi-mode vibrations (Shen et al.,2010). In the ASSH control technique, the switch 𝑆1is closed at least four times in a period, and an adjustable threshold coefficient controls it. While in ESSH, the switch 𝑆1closes twice in a period, every time the piezoelectric mechanical structure is at its maximum displacement. Therefore, for a single frequency excitation, the control law of ESSH is optimal (Anna et al.,2018). Energy Injection The energy injection technique, shown in Figure 14, is based on the SECE with an energy feedback loop from the storage stage to the piezoelectric element. The operation of this approach can be divided into three phases: harvesting, injection, and open circuit (Lallart and Guyomar,2010). D L2 S CS Piezoelectric L1 Rectifier Cint RL V Sinj1 Sinj2 Figure 14: Circuit schematic of the energy injection technique. Firstly, at the same time the piezo voltage modulus is at its maximum value, the switch S starts the harvesting phase, extracting energy from the piezoelectric element to the switch S and the inductor 𝐿2. Afterwards, the two switches 𝑆𝑖𝑛𝑗1and 𝑆𝑖𝑛𝑗2control the energy injection process (Guyomar,2011). Contrary to the prior methods, this technique allows a bidirectional energy flow. Thereby, the forward energy, which goes from the piezoelectric transducer to the storage capacitor, is controlled by the switch. During this time, 𝑆𝑖𝑛𝑗1and 𝑆𝑖𝑛𝑗2are used to manage the reverse energy flow. This causes a power resonance phenomenon occurring at the optimal value of 𝑘2⋅𝑄𝑀. Thanks to the bidirectional energy flow, this technique accomplishes higher outputs for different load values, leading to a more significant performance (Anna et al.,2018). 2.1. Analog Switch 20 2.1.3 Switching Techniques Summary The electronic interfaces can be divided into two classes. The first class to enhance the conversion establishes a direct connection between the piezoelectric element and the storage stage, named, Direct Energy Transfer. Due to this connection, the harvested power is strictly dependent on the connected load and, consequently, the extracted energy. In real-world applications, the load can suffer changes with time, according to the connected system state, and may not be fixed in advance. Therefore, to overcome this handicap, a second class was proposed using the same switching concept but applied differently. The second class is the Load Decoupling Interfaces, where the inductance concept is used through an inductor as an energy storage element. This component is used to take advantage of magnetism and electricity’s relationship when an electric current passes through the coil. The general operation of this category can be briefly described, starting with the piezoelectric element, through which, its energy is conveyed to the inductor. It is disconnected from the circuit, and the energy once provided to the inductor goes to the storage capacitor. As the name suggests, this interface category keeps the piezoelectric element from being straightly connected to the load stage. Hence, this leads to a process of accumulating energy independent of the connected system. The following Table 2organizes the literature architectures according to its class. Table 2: State-of-the-art piezoelectric harvesting interfaces. Direct Energy Transfer Load Decoupling Interfaces P-SSHI SSDCI S-SSHI SECE MR-SSHI PS-SECE Hybrid SSHI DSSH ESSH ASSH Enegy Injection For being part of the direct energy transfer category, all SSHI techniques are strongly dependent on the connected load. As an advantage, these approaches are self-powered, using off-the-shelf components and operating in a wide frequency range. In contrast, for the other techniques in the load decoupling interfaces category, implement a self-powered system is more challenging and complex due to the digital switch. 2.2. Voltage Amplifier 21 In microsystems, it is crucial to be careful about the design and implementation of the control system. Regarding the miniaturization of the device, the inductor and transformer can be seen as a limitation. 2.2 Voltage Amplifier The piezoelectric transducers can be used on low power electronic devices to convert vibrations into electrical energy. The voltage generated by the piezoelectric element is quite small and proportional to the variation of pressure applied. Typically the amplitude is comprised in a range of a few 10𝑚𝑉to 10𝑉, depending on the structure construction. Additionally, it has a very high impedance. Piezoelectric transducers generate little charge. As a result, it is not capable of providing voltage output levels that are high enough to be recognized by the rest of the circuit. Due to this problem, a voltage amplifier is required to amplify the signal to the desired level. Ideally, the amplifier features are infinite input impedance, zero output impedance, and gain independent of frequency (Gatti,2014). Thereby, the piezo-voltage is increased and can be converted into a usable signal for the rest of the circuit. 2.2.1 Amplifier Modes In response to mechanical stress, the piezoelectric material produces a charge compressed in the tens or hundreds of pico-coulombs per newton (𝑝𝐶/𝑁). Although 1𝑁is a relative amount of force, 100𝑝𝐶is a small amount of charge. Therefore, an amplifier is crucial. Typically, the high impedance of the piezoelectric sensor requires an amplifier with high input impedance, such as Junction gate Field-Effect Transistor (JFET) or CMOS input operational amplifiers. On the report of Karki (2000) two circuits are used for signal conditioning. If the amplifier is too close to the sensor, it is a voltage mode amplifier, as the one illustrated in Figure 15. Under other conditions, when the amplifier is remote to the sensor it is named a charge mode amplifier, illustrated in Figure 16. In both cases, the signal levels are set between 3𝑉to 5𝑉. Voltage Mode Amplifier The output of a voltage mode amplifier depends on the amount of capacitance seen by the piezoelectric, which is associated with the interface cable. Any capacitance that is in parallel with the piezoelectric device change the relationship between the applied force and the output voltage. Thus, small changes in cable capacitance can 2.2. Voltage Amplifier 22 Figure 15: Circuit of a voltage mode amplifier.(Karki,2000) Figure 16: Circuit of a charge mode amplifier. (Karki,2000) have a massive impact on the system. For that reason, the voltage-mode amplifiers should be considered only when it is placed close to the sensor. The equation to measure the output voltage is depicted in Figure 15, and the maximum output gain is given by the factor [1+𝑅𝑓 𝑅𝑔]. The upper (𝑓𝐻) and lower (𝑓𝐿) cut-off frequencies are expressed in Equations 12 and 13, respectively. 𝑓𝐻=1 2⋅𝜋⋅(𝑅𝑝∥𝑅𝑏)⋅(𝐶𝑝)∥𝐶𝑐(12) 𝑓𝐿=1 2⋅𝜋⋅𝑅𝑓⋅𝐶𝑓(13) Assuming that 𝑅𝑓and 𝐶𝑓are the feedback resistor and capacitor, respectively, 𝐶𝑝and 𝑅𝑝are the piezoelectric capacitor and resistor, correspondingly, 𝑅𝑏is the bias resistor, 𝐶𝑐the sensor capacitance, and 𝑅𝑖the isolator resistor. Charge Mode Amplifier A charge-mode amplifier (Figure 16) transfers the charge injected into the negative input terminal of the amplifier by changing the feedback capacitor. Fundamentally, it converts the charge into voltage with high input 2.3. Rectifier 29 Figure 23: Half-wave rectifier: (a) input waveform and (b) output waveform rectified. (Sedra and Smith,2014) The rectifier operates ineffectively when the input voltage peak is approximate from the 𝑉𝐷value. These rectifiers have very low efficiency. However, its simplicity is an advantage over more complex schematics. Full-wave Rectifier When it is necessary to rectify both half-cycles of the input waveform, a full-wave rectifier configuration must be employed. A simple schematic to implement this concept is a full-wave bridge rectifier as suggested by Jain and Joshi (2018) and illustrated in Figure 24. This circuit consists of four diodes (𝐷1,𝐷2,𝐷3,𝐷4) and stands out for giving a small output ripple voltage, commonly used in high voltage applications, where the diode forward voltage drop of 0.7𝑉to 1𝑉. For low-voltage applications, these values result in a large number of voltage losses, reducing the PCE significantly (Lam et al.,2006). Vin GND RL D1 D2D3 D4Vout Figure 24: Schematic circuit of the full-wave rectifier. The positive half-cycle is driven by 𝐷1and 𝐷2, while the negative half-cycles flows via 𝐷3and 𝐷4. The current flows up to the load, regardless of the polarity of the input. Due to this, it has twice the voltage drop than rectifier mentioned above and highly reduces the available output voltage (Figure 25). Nevertheless, this is an advantage in low voltage power supplies. 2.3. Rectifier 30 v v out V D t v in Figure 25: Input and output waveforms of a full-wave rectifier. (Sedra and Smith,2014) Diodes A crucial phase when designing a convectional rectifier is to choose the diode to implement. There are some essential things to take into consideration. Firstly, the amount of current the diode can operate with is based on the maximum current that is expected to pass through the rectifier. Furthermore, afterwards, the peak inverse voltage, which should be as higher as possible to avoid reverse current across the diode. Standard pn-junctions diodes suffer latch-up and low switching speed, both features not suitable for frequencies in MHz range (Peters et al.,2011). When the signal amplitude becomes less than the threshold voltage (𝑉𝑡ℎ), diodes cannot play a rectifier role (Babacan,2018). Schottky diodes are a semiconductor that can be utilized for detecting and rectifying sinusoidal waves with a low forward voltage drop between 150 and 450 mV, suitable for the low power application (Partal and Belen, 2019). This diode is made by a metal-semiconductor junction named the Schottky barrier (Brezeanu et al.,2001) and is represented in Figure 26. Usually, the cathode is n-type silicon, while the anode is metal like platinum, chromium or tungsten. Therefore, the forward voltage depends on the choice of material used for the junction. This diode can be employed to enhance efficiency and replace the standard diode, due to its excellent highfrequency behaviour, low forward voltage, fast switching speed and independence from the recovery time (Lam et al.,2006;Akkermans et al.,2005). One of the little limitations of the Schottky diodes is the breakdown voltage (Milanovic et al.,1996;Banu et al.,2012). The diode needs to be modeled by the electric circuit shown in Figure 27 using Simulation Program with Integrated Circuit Emphasis (SPICE) parameters (Cadence,2016). The model consists of a substrate resistance 𝑅𝑠, a junction capacitance 𝐶𝑗and a junction resistance 𝑅𝑗. 2.3. Rectifier 31 Figure 26: Schottky diode: (a) layout, (b) cross-section and (c) symbol. (Baker,2010) Rs Cj Rj Figure 27: Schottky diode equivalent linear circuit model. The total impedance of the linear model, 𝑍𝑇, is given by Equation 19 as suggested by Kasi et al. (2012). In this equation, the values of 𝑅𝑗and 𝐶𝑗are constants, and the operation frequency, w, is the only variable parameter. 𝑍𝑇=𝑅𝑠+𝑅𝑗 1+𝑗⋅𝑤⋅𝑅𝑗⋅𝐶𝑗(19) The 𝑅𝑗is expressed in Equation 20, where 𝐼𝑏is the bias current, 𝐼𝑠is the saturation current, T corresponds to the temperature in kelvin and N is the ideality factor (Ali et al.,2014). At low bias levels, the voltage drop across 𝑅𝑠is insignificant, and the Schottky barrier dominates the diode behaviour. Contrarily, at higher bias levels, the ohmic resistance 𝑅𝑠dominates. 𝑅𝑗=8.33⋅10−5⋅𝑁⋅𝑇 𝐼𝑏+𝐼𝑠(20) 2.3. Rectifier 32 For energy harvesting applications, the most common is a zero bias Schottky diode model, such as HSMS2850 in Devi et al. (2012); Kasi et al. (2012) fabricated by Agilent (2005). Albeit its advantages, the expensive production cost and high reverse leakage current are not rewarding compared to a standard CMOS process. A significant voltage drop is not tolerated for the vibrational energy harvesters. Thereby, the implementation of common and Schottky diodes should be avoided in conventional rectifiers (Raisigel et al.,2007). For some applications, the diodes’ voltage drop can be an issue. It is considering that a diode only starts to conduct when the voltage across its terminals reaches a threshold, meaning that the diode is not capable of emulating the entire positive half of the input signal. Besides, the use of diodes results in high power dissipation. Summary Table 3gives an overall view of some conventional rectifiers previously mentioned. Table 3: Comparison of the state-of-the-art of convencional rectifier topologies. Topology Features Comments Half-wave (Li et al., 2014) Only allows an half of the AC input waveform to pass through to the storage stage. ⊙Simple schematic; High voltage applications. ⊗Low efficiency. Full-wave bridge (Jain and Joshi,2018) It is four diode bridge configuration that full uses both half-cycles of the sinusoidal input signal. ⊙Small output ripple voltage; High voltage applications. ⊗Reduced PCE in low voltage applications. Standard diodes (Peters et al.,2011)Forward voltage ≈0.7𝑉 ⊗Latch-up; Slow switching; Small frequency range. Schottky diode (Raisigel et al.,2007) Forward voltage ≈150𝑚𝑉to 45𝑚𝑉; Made by a metal semiconductor junction. ⊙Wide frequency range; Low forward drop; Replace the standard diodes. ⊗Expensive production; Reverse leakage current. ⊙Advantage, ⊗Disadvantage. 2.3.2 CMOS Rectifier Rectifiers implemented on CMOS technology have been proposed to replace the conventional rectifiers above mentioned (Raop et al.,2012). In CMOS implementation circuits, Metal-Oxide-Semiconductor (MOS) transistors 2.3. Rectifier 33 in a diode configuration, meaning gate terminal connected to the drain terminal, are widely exploited (Li et al., 2014). The transistors conduct current if the forward voltage exceeds the Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) 𝑉𝑡ℎ. The PMOS transistors’ bulks must be connected to the highest potential and the NMOS to the lowest (Peters et al.,2007). These connections are helpful to avoid leakage currents and latch-up and were used in the past in many studies (Peters et al.,2011). The voltage drop over a MOS diode is related to transistor’s 𝑉𝑡ℎ, which depends on the process and temperature used during fabrication (Peters et al.,2008). In Peters et al. (2007), one transistor connected as a diode in each path is replaced with a switch driven by the alternating input voltage. Due to this, every half-wave rectifier is used, and only one voltage drop occurs as a result of its conduction that takes place in pairs. However, four switches can not be applied in this way; otherwise, current backflow occurs. ADynamic Threshold Voltage MOSFET (DTMOS) is a technique to reduce 𝑉𝑡ℎand power dissipation proposed by Bokor et al. (1997). It takes over from the conventional MOS diode, thanks to escaping reverse current. This technique is based on having the gate tied to the bulk terminal, as shown in Figure 28. Due to this, 𝑉𝑡ℎ becomes lower, and when implemented in a rectifier circuit provides less power consumption and, consequently, reduces power dissipation (Babacan,2018). A PMOS can implement this connection in an n-well process or an NMOS in triple-well processes (Cardoso,2010), although it is more expensive than a p-channel. With lower power consumption and dissipation, the prior techniques can allow the DTMOS to perform as an ideal diode for low voltage operation (Babacan,2018). Figure 28: DTMOS configuration. (Babacan,2018) CMOS integrated rectifiers are roughly divided into two main groups: passive and active rectifiers. Despite advances in CMOS technologies, there is still an issue with high 𝑉𝑡ℎ. Research has been done, and many solutions intend to increase the efficiency of these circuits (Herbawi et al.,2013). A few configuration techniques can optimize the PCE and decrease the 𝑉𝑡ℎ:𝑉𝑡ℎ cancellation techniques, since the voltage drop depends on the 𝑉𝑡ℎ(Junior et al.,2018;Lam et al.,2006;Kotani and Ito,2009), circuits with active diode using Operational 2.3. Rectifier 34 Amplifier (op-amp) (Junior et al.,2018;Safari et al.,2018;Sun et al.,2012;Kakoty,2011), bridgeless AC-DC converters (Junior et al.,2018) and Dickson charge pump (Wong et al.,2016). Configuration Techniques Rectifier topologies based on the 𝑉𝑡ℎ cancellation techniques aim to decrease the voltage drop through the rectifier to obtain more significant output voltage levels across the load (Junior et al.,2018). Application in standard CMOS processes could reduce the turn ON threshold by adding biasing circuits. This implies that the gate-to-drain voltages are fixed, and the gate drive voltages are controlled by the drain-to-source voltages that change slightly depending on the conduction. Therefore, the switches do not turn ON and OFF entirely, leading to inefficient rectification (Lam et al.,2006). Usually, the transistors are in the cut-off region, operating near the linear region. As a consequence, there is a reduction of the PCE, once the leakage current is increased (Junior et al.,2018). The 𝑉𝑡ℎtechniques can be divided into three, as proposed by Kotani and Ito (2009): External 𝑉𝑡ℎCancellation (EVC),Internal 𝑉𝑡ℎCancellation (IVC) and Self-𝑉𝑡ℎCancellation (SVC). In EVC, sown in Figure 29(a), the bias is generated with a switched capacitor circuit between the gate and the drain of the NMOS, requiring an external power supply and clock. The output voltage is given by Equation 21. 𝑉𝑜𝑢𝑡=2⋅(𝑉𝑖𝑛−𝑉𝑡ℎ+𝑉𝑝𝑜𝑙𝑎𝑟𝑖𝑧𝑎𝑡𝑖𝑜𝑛)(21) In IVC, illustrated in Figure 29(b), the gate bias voltage came internally from the output DC voltage by a bias generation circuit (Raben et al.,2012). There is a degradation of the PCE to the passage of DC, due to power dissipation. It works in a large input power current, but not under small input power conditions. In SVC, depicted in Figure 29(c), the gate electrodes of the NMOS and PMOS transistors are connected to the output and ground terminals, respectively. This connection boosts the gate-source voltage of the transistors as much as possible, reducing 𝑉𝑡ℎ. The 𝑉𝑡ℎof the transistors is proportional to the output voltage, so equivalently decreases the same amount to both. SVC is the simplest technique and requires no additional power supply, resulting in a possible better PCE. Nguyen et al. (2014) proposed enhanced IVC technique as shown in Figure 30 that consists of combine the conventional IVC and switches to improve PCE and voltage efficiency. The switching systems were implemented to create a pulse signal, that applied to the gates of 𝑀1and 𝑀2results in a better control of their operation state, reducing the reverse leakage current. These switches are carried out by PMOS and NMOS (SP1, SP2, SN1 2.3. Rectifier 35 (c) Figure 29: Circuit of the (a) EVC, (b) IVC and (c) SVC techniques. (Kotani and Ito,2009) and SN2), and their switch speed is not fast enough to avoid reverse current. Therefore, the body effect reduces the threshold voltage and consequently improve the switching time of SN1. Further, also the switching time of SP2 in improved by decreasing its gate voltage. As a result, no reverse current flows through 𝑀1and 𝑀2in OFF period, resulting in a raising of PCE, up to 80%. Figure 30: Schematic of the IVC technique combined with switches. (Nguyen et al.,2014) Rectifiers with active diode based on op-amp are adopted for applications that require high accuracy in the range of 𝑉𝑡ℎ. A disadvantage of this technique is the high distortion during the zero-crossing of the input signal. This happens when diodes switch between ON and OFF states (Safari et al.,2018). Besides, the performance of the rectifier is restrained by the gain-bandwidth of the op-amp (Virattiya and Knobnob,2011). This topology is not feasible for energy harvesting since, according to Junior et al. (2018), it increases energy consumption due to external supply voltage. 2.3. Rectifier 36 Figure 31: Schematic of a rectifier combining an active diode with an op-amp. (Sun et al.,2012) In Sun et al. (2012), an active full-bridge rectifier is presented and exhibited in Figure 31. The dc-offset problem of the comparator based on an active diode is solved by replacing the passive diodes with an op-amp and adding a switch in parallel with the transducer. The NMOS transistor is combined with the op-amp, while the PMOS are configured in cross-coupling. Due to this, the voltage drop reduces and extracts more power from the transducer, leading to better efficiency. The rectifier operation can be divided into three states. Firstly, no current flows through 𝑀𝑃1and 𝑀𝑃2, since 𝐼𝑝is charging 𝐶𝑝. When the voltage on the transducer is higher than the 𝑉𝑡ℎ,𝑀𝑃1turns ON. In state 2, although 𝑀𝑃1works as a closed switch, 𝑀𝑁2remains OFF, and there is no current flowing to the output. As 𝐼𝑝keeps charging 𝐶𝑝, the voltage on the transducer is increasing and the op-amp turns ON 𝑀𝑁2. Finally, in state 3, the current flows to the output charging 𝐶𝐿, since both transistors 𝑀𝑃1and 𝑀𝑁2are ON. In Kakoty (2011), a standard CMOS op-amp with three subsections stages followed by an output buffer is reported (Figure 32). It employs a Miller capacitor and is balanced with a current buffer compensation technique. The first sub-circuit is a differential gain stage that incorporates a current mirror active load with three distinct advantages. Primary, the use of active load devices creates a significant output resistance in a relatively small amount of die area. Secondly, the current mirror topology performs the differential to the single-ended conversion of the input signal. Finally, the load also helps with the common-mode rejection ratio. The maximum and minimum output voltage of this stage is limited by keeping a PMOS in saturation and the voltage of an NMOS gate, respectively (Baker,2010). The purpose of the second gain stage is to provide an additional gain for the output amplifier. The third stage is a bias string, which makes uses of three transistors and a current source. 2.3. Rectifier 37 Figure 32: Circuit of an op-amp with a compensation block. (Kakoty,2011) Figure 33: Circuit of a bridgeless rectifier. (Wang et al.,2013) Bridgeless AC-DC converters use inductors to increasing the PCE specially for low-voltage applications (Junior et al.,2018). A bridgeless rectifier was suggested by Wang et al. (2013), as represented in Figure 33, integrating a boost and a buck-boost converters. The circuit operates in the boost mode when the input voltage, 𝑉𝑖𝑛, is positive, turning On the transistor 𝑆1and the diode 𝐷1is reverse biased. When the input waveform becomes negative, the switch 𝑆2turns ON and 𝐷2is reverse biased. Thus the circuit operated under the buck-boost mode. Dickson charge pump is known as a switched capacitor with a voltage gain higher than one, also commonly called voltage multiplier. It is responsible for amplifying the signal without distortion of the input waveform. This technique is a DC to DC converter and is not a rectifier since it is not capable of separate the input signal between positive and negative cycles. However, with some modification, it could be transformed into a rectifier. The aim is to optimize features as leakage current, output voltage and rise time to improve the PCE (Ballo et al.,2019). In Dickson (1980), a solution was patented, reported in Figure 34. The Dickson charge pump is made up of NMOS transistors, with the bulk connected to the ground, and the gate coupled to a forward node, avoiding 2.3. Rectifier 38 Figure 34: Dickson charge pump with NMOS transistors. (Ballo et al.,2019) voltage losses due to the transistor threshold voltage. Its main handicap is the reverse current that follows anytime the charge transfer switch is turned off, resulting in a reduction of PCE. The topology presented in Figure 35 is a general block scheme proposed by Wong et al. (2016), where the Dickson charge pump is connected in parallel with the voltage doubler. Focusing on the first stage, during the negative half-cycle, the first diode is activated and charges the first capacitor while the other diode is in the cut-off. Otherwise, the second diode is activated, charging the second capacitor, while the first diode is cut-off. To enhance the performance, instead of using a diode-connected MOSFET, a Ultra-Low Power (ULP) diode was implemented, since those have lower leakage current and higher output voltage. Consequently, the efficiency achieved increased from approximately 8% using MOSFETs to around 17%. Figure 35: Dickson charge pump rectifier. (Wong et al.,2016) Passive Rectifiers Passive rectifiers implemented in a conventional IC process using diodes are discussed previously. As a result of the power losses, the forward voltage drop and the leakage current within full-wave rectifiers using diodes, MOSFETs replace them in a diode tied configuration. The efficiency of the circuit strongly depends on the transistor’s threshold voltage, especially if the MOSFET is not completely turned ON or OFF. 2.3. Rectifier 45 Table 4: Comparison of the state-of-the-art of CMOS rectifier topologies. Topology Features Comments DTMOS (Bokor et al., 1997;Cardoso, 2010;Babacan, 2018) The MOSFETs has the gate tied to the bulk terminal. ⊙Reduce 𝑉𝑡ℎ; Low power dissipation and consumption; Wide voltage operation; No reverse current; Replace the conventional MOS diodes. ⊗Expensive if it uses NMOS. Passive rectifier (Peters et al.,2011; Junior et al.,2018; Kotani and Ito,2009) Composed by conventional rectifiers and configurations with MOSFETs connected as a diode. ⊙Simple structures; Configuration techniques to reduce 𝑉𝑡ℎand increase PCE; High input frequency applications. ⊗Weak performance; Large chip area. Active rectifier (Lam et al.,2006) Full CMOS active rectifier employing a four input comparator with common gate input stages. ⊙Performance matches a zero-threshold diode. ⊗Offset current; High schematic complexity. Two-stage active rectifier (Peters et al., 2010) System composed by a NVC and an active diode controlled by a three stage comparator. ⊙Low input voltage applications. ⊗Limited voltage range; High schematic complexity. Two-stage active rectifier (Li et al., 2014) Two-stage structure that includes a three-stage comparator with a resistor. ⊙Simple schematic. ⊗High power consumption; Large chip area. Active rectifier (Cha et al.,2012) Active NMOS and PMOS diodes composed by a four-input common-gate-type cross-coupled comparator. ⊙Speed-up technique. ⊗High power consumption; Large chip area. Two-stage active rectifier (Peters et al., 2008) Fully CMOS two stage active rectifier controlled by a three stage comparator. ⊙Fully CMOS architecture. ⊗High minimum input voltage. ⊙Advantage, ⊗Disadvantage. 3 DEVELOPMENT AND RESULTS Electronic devices consume energy in order to generate the desired output and in unwanted behavior such as waste heat. When energy is harvested from small environment sources, the energy consumption must be kept to a minimum, to maximize the device efficiency. Using CMOS technology, custom transistors are used for constructing an IC. This fabrication processes are able to form symmetric pand n-type transistor pairs. The possibility of this symmetry is beneficial to design accurately mixed-signal systems. Another essential feature is the CMOS low static power consumption compared to other IC technologies. Additionally, CMOS technology can reduce the energy consumption to an absolute minimum during the OFF state of the system. For these reasons and the ability to integrate complex systems on the same chip, CMOS was chosen as the main technology used for the development of the proposed system. Although CMOS devices fabrication is cumbersome and expensive, the use of Electronic Design Automation (EDA) tools is needed. Thereby, the design can be tested through simulation, allowing an increased reliability and a faster prototyping on new iterations. 3.1 Analog Switch Per the research described in section 2.1, an original design is developed. Several improvements are made to increase the switching speed and efficiency, keeping a wide frequency range. 46 3.1. Analog Switch 47 3.1.1 Up-conversion Technique The main limitation in standard energy transfer approaches is the high inductance value needed to properly match the impedance of the piezoelectric element, due to the low operating frequency of conventional piezoelectric transducers. An automatic frequency up-conversion technique based in Li et al. (2014), as represent in Figure 41, overcomes this drawback, shifting the working operational frequency to higher values. This harvesting architecture is designed to match the output impedance of the piezoelectric transducer dynamically, by shifting the vibrational frequency of the piezoelectric element up to the resonant frequency of the harvesting interface. L2 L1 S V RL CS Rectifier Piezoelectric C1 Figure 41: Schematic of the frequency up-conversion rectifier. The circuit illustrated in Figure 41 is composed of a transformer, a bilateral switch S, and a tuning capacitor 𝐶1. 𝐿1and 𝐿2are the inductances of the primary and secondary coils in the transformer, respectively. Therefore, the switched transformer is employed as an active component to implement the up-conversion technique. The current in the first loop can be expressed by Equation 25, where 𝐼1𝑚is the maximum current and 𝜔0is the angular frequency of the piezoelectric. 𝑖1(𝑡)=𝐼1𝑚⋅𝑠𝑖𝑛(𝜔0⋅𝑡) (25) Equation 26 describes the equivalent input resistance of the frequency modulation circuit. On the assumption that T and 𝐷1are the period and duty cycle of the switch, respectively. 𝑅1=2⋅𝐿1 𝐷2 1⋅𝑇 (26) The secondary resonance circuit also creates a resistance in the transformer (𝑅2). To simplify the analyzis, the rectifier is considered as a diode bridge. When the voltage across the inductor 𝐿2reaches the threshold voltage of the diode, energy can be transferred for the storage capacitor (𝐶𝑠;.otherwise, the capacitor 𝐶1is charged. Thus, assuming that 𝑖2(𝑡)as the current in the secondary resonant circuit, the voltage across the secondary circuit can be expressed bu Equation 27. 3.1. Analog Switch 48 𝑉𝐿2(𝑡)+𝑉𝐶1(𝑡)+𝑉𝑅2(𝑡)+𝑉𝐷=0, (27) where 𝑉𝐿2,𝑉𝐶1,𝑉𝑅2and 𝑉𝐷are the voltage across the inductor 𝐿2, the capacitor 𝐶1, the resistance 𝑅2, and the threshold voltage of the diode bridge rectifier, respectively. Moreover, for the resonant matching circuit, the efficiency is proportional to the quality value. Hence, equations 28 and 29 express the quality factor of the primary and secondary transformer loops, correspondingly. 𝑄1=1 𝑅1⋅√𝐿1 𝐶𝑝(28) 𝑄2=1 𝑅2⋅√𝐿2 𝐶1(29) 3.1.2 Management System The switching circuit for vibrational energy harvesting applications implemented in this work is exhibited in Figure 42. The management system is composed of a piezoelectric transducer, a switching circuit, a transformer, a rectifier, and lastly a storage stage. Rectifier Piezoelectric Transducer CSRL S1 L1L2 Cp Ip S2 D1D2 Switching Circuit Transformer Storage Stage Figure 42: Circuit diagram of the switching approach for vibrational energy harvesting. The resistance of the piezoelectric can be ignored in the analysis since its value is approximately 107Ω, and the equivalent capacitor (𝐶𝑝) is relatively small. The equivalent model of a capacitor is implemented by an AC 3.1. Analog Switch 49 current source in parallel with the equivalent capacitor. The equivalent capacitor can be formulated according to Equation 30. 𝐶𝑝=𝜀0⋅𝜀𝑟⋅𝑆 𝑑,(30) Where 𝜀0is the vacuum dielectric constant, 𝜀𝑟is the relative permittivity, and the term 𝑆 𝑑is the ratio between the area (S) and the thickness (d) of the piezoelectric. Transformer Two coil winding, 𝐿1and 𝐿2, around a solid core, create the transformer, which the working principle relies on the Faraday’s law of induction based on the change of magnetic field. Both coils are connecting two electrical circuits through electromagnetic induction. By mutual induction, one coil magnetically induces a voltage into another coil, located at the proximity. In this way, there is no direct electrical connection between the coils. Thanks to the transformer it is possible to either increase or decrease, or even produce the same voltage applied to the primary winding, without changing its frequency, or the amount of electrical power being transferred from one to another winding. This is accomplished by changing the number of turns in the primary coil (𝑁1) compared to the number of turns in the secondary coil (𝑁2). The ratio of transformation (n) dictates the operation of the transformer and the corresponding voltage available on the secondary winding (𝑉2), and is given by Equation 31. 𝑛=𝑁1 𝑁2=𝑉1 𝑉2(31) Switching circuit Analog switches are a common building block in analog signal processing, that when turned ON are capable of conducting both analog and digital signals from the input to the output, regardless of the signal travelling direction. The structure of a conventional analog switch connects an NMOS in parallel with a PMOS. MOSFETs make almost excellent switching devices and are often used in power applications. Those are faster, smaller, easy-to-use, and consume less power than other electrically controlled switches. While turned ON, it allows the signal to pass in either direction, during the time is turned OFF isolates the piezoelectric transducer. Nevertheless, there are some obstacles on analog switches. These circuits have a frequency response limitation due to channel capacitance, 3.1. Analog Switch 50 that can be caused, for example, by parasitic capacitance at high frequencies. The ideal switch should transmit a signal without changing the original, creating a short-circuit at OFF state and an open-circuit at ON state. However, there are some losses associated with the resistance of the conducting channel when the MOSFET is turning ON. Moreover, the analog switch generates ground bounce noise and demonstrates a propagation delay. The switching circuit works as a frequency converter or frequency changer, which converts an AC signal of a specific frequency to an AC signal with another frequency. This is achieved, as depicted in Figure 42, by two switches, 𝑆1and 𝑆2, and two diodes, 𝐷1and 𝐷2, connected in parallel to the switches. Both switches operate at a switching frequency, referring to the rate at which the switch connect and disconnect the conducting path from the piezoelectric transducer. Besides, since the switch as no preferred direction for current flow, the diodes work as a barrier to avoid the reverse current. As a result, the switching circuit turns ON and OFF at the desired frequency, the signal is modeled into that frequency. The switching frequency is a circuit parameter to take into consideration since it affects nearly every performance characteristic of the system. A high switching frequency reduces the size of associated components, such as the inductors, transformers, and capacitors, decreasing space requirements on a board or chip. However, converters operating at higher frequencies have reduced efficiency due to the increased power losses. Thus, it is necessary to equilibrate these factors. Figure 43 illustrates the CMOS analog switch implemented in this work. The transistors M1 and M2 constitute the conventional switch, an NMOS connected in parallel with a PMOS, correspondingly. The switch mechanism is controlled by an inverter or NOT gate, constituted by both p-channel and n-channel MOSFETs, M3 and M4 respectively. The working principle is simple: at the time the voltage that enables the transistors (𝑉𝐸𝑁) is high, the gate of M1 is activated, and the current can flow through it. The signal is inverted by the not gate, activating the gate of M2. Thereby, the analog switch is turned ON, or the circuit is closed. Otherwise, when 𝑉𝐸𝑁 is a low voltage, the gate of M1 is not activated and the transistor works as an open circuit. In this case, the signal is inverted by M3 and M4 and is not able to activate the transistor M2. Since both the switch transistors M1 and M2 are in open circuit, the current is not flowing to the output, and the system is isolating the input signal. Thence, if both transistors, M1 and M2, are turned OFF, the switch is opened. To enhance the performance of the switching circuit on Figure 44(a), a current starved technique is added, as shown in Figure 44(b), to reduce the current and power consumption. The transistors M3 and M4 constitute the standard CMOS inverter. M5 and M9 limit the current available to the inverter. The drain currents of M6 and M8 are the same and are fixed by M7. 3.1. Analog Switch 51 VCC GND M4 M1 M3 VEN Vin Vout M2 Figure 43: Analog switch schematic for the switching circuit. The switch is closed when 𝑉𝐸𝑁 is a high value. In this way, the n-channel MOSFET M1 is activated. Subsequently, 𝑉𝐸𝑁is inverted by the upturned into 𝑉𝑛𝐸𝑁, which is capable of turning ON the p-channel MOSFET M2. Afterwards, the analog switch is closed and the input signal is flowing to the output. On the contrary, if 𝑉𝐸𝑁 is a low signal, M1 is turned OFF along with M2 and the analog switch is open. 3.1.3 Features During the designing process is crucial to define the circuit´ specifications. There are many performance criteria to consider, due to a large number of analog switches in the market. A structure of a conventional analog switch is an NMOS connected in parallel with a PMOS. Therefore, some important parameters are described as following: • Absolute maximum supply voltage: this is the maximum voltage that may be applied to power the analog switch. • Absolute maximum input voltage: the maximum and minimum input voltage that may be applied at either the source or drain terminal and pass through the analog switch. 3.1. Analog Switch 52 VCC GND M2 M1 VEN Vin Vout M9 M4 M3 M5 M8 M7 M6 VnEN VnEN VEN (a) (b) Figure 44: Enchanced analog switch coupling the (a) conventional switch with a (b) current starved technique. • OFF isolation: the amount of coupling from input to output of a disabled channel. A measurement of OFF state switch impedance. • ON loss or insertion loss: represents the attenuation of the output signal from the respective input signal and strongly depends on the load stage. • Control system: the voltage levels of the switch need to be compatible with the switch control. • Charge injection: changing the state on the control pin causes a charge to be coupled to the channel of the transistor, introducing signal noise. • Switching speed: specifies how long it takes for the switch to actuate. This is the delay from when the logic state of the switch control change, and subsequently enables its output in response to the given input. Turn ON time (𝑡𝑂𝑁) is the maximum amount of time needed to be in the ON or in conducting state after its digital input turns it on. Nevertheless, turn OFF time (𝑡𝑂𝐹𝐹) is the maximum amount of time needed to be in the OFF or the non-conducting state after its digital input turns it off. –Break-Before-Make (BBM): If 𝑡𝑂𝑁 > 𝑡𝑂𝐹𝐹, the first set of contacts break (open) before engaging (close) the new contacts. This process is called BBM and prevents a momentary electrically connection between the old and new signal pads when the select input changes. 3.1. Analog Switch 53 –Make-Before-Break (MBB): If 𝑡𝑂𝑁 <𝑡𝑂𝐹𝐹, the signal paths are not open when the select input changes state. In other words, MBB describes a configuration to avoid opening both switches at the same time. In this way, the new connection path is settled before the previous contacts are opened. • ON resistance (𝑅𝑂𝑁): the resistance value between the drain and source of a MOSFET during operation. Ideally, this parameter should be as low as possible to keep the signal losses and propagation delays small. However, the trade-off on reducing 𝑅𝑂𝑁 is that it involves increasing the width (W) and length (L) ratio, resulting in higher parasitic capacitance and a larger silicon area. Apart from W and L, 𝑅𝑂𝑁is a function of electron and hole mobility (𝜇𝑛and 𝜇𝑝, respectively), oxide capacitance (𝐶𝑂𝑋), 𝑉𝑡ℎ, and signal voltage (𝑉𝐺𝑆) of the nand p-channel MOSFETs as formulated in equation 32. 𝑅𝑂𝑁 =𝐿 𝜇⋅𝐶𝑂𝑋⋅𝑊⋅(𝑉𝐺𝑆−𝑉𝑡ℎ)(32) • OFF resistance (𝑅𝑂𝐹𝐹): this describes the resistance of the switch in OFF state or open circuit. In this case, the higher the 𝑅𝑂𝐹𝐹, the smaller the energy losses during switch OFF state. Nonetheless, a high 𝑅𝑂𝐹𝐹is also very important for a good OFF-isolation (OFF state impedance). • Feedthrough: this characteristic is related to the ability of the switch to block signals in OFF state. Parasitic capacitance allows high frequencies to mix through the switch, making it appear to be ON or closed circuit. This parameter is directly connected with OFF isolation and OFF resistance. An important characteristic is the transistor dimensions. For low voltage design, a large width is needed to keep the voltage drop over the device low. The transistors size is chosen to keep 𝑅𝑂𝑁 low. The selected transistors size for the designed circuit in Figure 44 is pointed in Table 5. Table 5: Dimensions of the switching circuit transistors. Transistor Width (𝜇m) Length (𝜇𝑚) M1, M2 12 5 M3, M4, M5, M6, M8, M9 0.28 0.13 M7 0.15 0.13 For the proposed applications, some specifications are established to enhance the performance of the circuit. The supply system should have a voltage of 3.3𝑉and a current higher than 0.05𝜇𝐴. The OFF resistance should 3.1. Analog Switch 54 be as high as possible and the ON resistance approximately 50Ω. Additionally, the leakage current should be null, although, in a real-world application, those conditions are not possible to achieve. Thus, a leakage current with a maximum of 1𝑛𝐴, and a switching speed of 100𝑛𝑠are desired. 3.1.4 Results In order to test the proposed circuit, SPICE simulations tools were used in Cadence software with the appropriate 0.13𝜇𝑚CMOS technology. The results of the analog switch operation are presented in Figure 45, show how the analog switch operates. A sinusoidal input voltage (𝑉𝑖𝑛) with 1𝑉and an offset voltage of 1𝑉at 10𝑘𝐻𝑧was adopted. The offset voltage is applied to guarantee that the input voltage has not negative values. Due to this, the input voltage goes from 0𝑉 to 2𝑉. Besides, a supply voltage (𝑉𝑠𝑢𝑝𝑝) was set at 3.3𝑉, and a resistor load (𝑅𝐿) was added at the end of the circuit to simulate an unstable state. Furthermore, the enable signal (𝑉𝐸𝑁) was simulated as a Piecewise Linear (PWL) voltage source, which within 0𝑠until 200𝜇𝑠is zero, then from 200.1𝜇𝑠until 600𝜇𝑠is 3𝑉. Finally, up to 600.1𝜇𝑠,𝑉𝐸𝑁 is grounded again. 02468 ·10  4 0 1 2 3 Time (s) Voltage (V) Vin Vout VE N Figure 45: Operation principle representation of the designed analog switch, including the input signal (𝑉𝑖𝑛), enable signal (𝑉𝐸𝑁) and the output waveform (𝑉𝑜𝑢𝑡). As observed in Figure 45, the operation of the switching circuit is fulfilled. When 𝑉𝐸𝑁 reaches high values, the analog switch is closed, allowing current to flow and outputs a signal similar to 𝑉𝑖𝑛. Moreover, the switch is open, isolating the input from the output when 𝑉𝐸𝑁 is low and the switch output is zero. 3.1. Analog Switch 61 Table 6: Comparison of proposed analog switch with off-the-shelf components. References TS12A4514 (Tex,2009) ADG841 (Ana,2005) Proposed Work Voltage Supply (V) −0.3-13 −0.3-4.6 −0.25-19 Input Voltage (V) 𝑉𝑠𝑢𝑝𝑝±0.3 𝑉𝑠𝑢𝑝𝑝±0.3 ≤𝑉𝑠𝑢𝑝𝑝 Temperature (∘C) −40-85 −40-125 −40-150 Turn ON time (s) 100n 14n 1.88n Turn OFF time (s) 50n 7.8n 11.2n ON resistance (Ω) 50 0.28 212.5 OFF resistance (Ω) - - 520.6M ON loss (dB) - −0.02 −0.16 OFF isolation (dB) −94 −54 −111.24 3.1.6 Summary A fast and efficient analog switch, with an inverter, making use of a starved current technique, was designed. The circuit is supplied by a wide voltage range. Compared to previous research, this circuit performs in the normal range, for its purpose, especially with the chosen technology. During simulations, a sensitivity analysis was performed. The proposed design is suitable for matching the high impedance of the piezoelectric element, shifting the vibrational frequency of the piezoelectric up to the resonant frequency of the harvesting interface. Besides, the circuit is capable of supporting high frequencies up to MHz. This is also suitable for low voltage operation. Additionally, the integration of the switch cell to CMOS circuit designs should be straightforward, even with already existing designs. The circuit used CMOS technology, taking into advantage the sub-threshold region of CMOS transistors. The final layout design and fabrication steps are presented in section 3.4. The design has in mind energy harvesting interfaces and wireless sensor networks, although it has, likewise, applications for modems, audio, communication systems, and so forth. 3.2. Voltage Amplifier 62 3.2 Voltage Amplifier The energy generated by PEGs has limited power from tens of microwatts to a few milliwatts, being unsuitable to directly powering most electronic systems. In order to overcome this issue, a voltage amplifier was implemented to pre-amplify the signal is needed. Therefore, the application of MOSFETs with low power consumption is essential. 3.2.1 Design and Modeling Amplifiers must be designed according to specific design and application objectives. According to the consideration described in section 2.2, an original design is developed. For this project, the voltage amplifier is exhibited in Figure 51, and consists of a non-inverting two-stage amplifier. C1 R1 VCC GND GND VCC R2 C2 M1 M2 M3 M4 Vin Vout Figure 51: Circuit schematic of the designed voltage amplifier. The resistors, 𝑅1and 𝑅2provide DC feedback, and ensure the stability of the circuit. The capacitance 𝐶2is responsible for attenuating the offset voltage. To amplify the signal, the input has to be coupled via a capacitor, 𝐶1, and the transistor M1 should present a high width. The specifications of the components are depicted in Table 7. The voltage amplifier is implemented by two inverters or not gates in cascade. The first stage is constituted by 𝐶1,𝑅1, M1 and M2, while 𝐶2,𝑅2, M3 and M4 make up the second stage. Thus, the input signal is twice inverted, and the circuit output is a non-inverted signal. 3.2. Voltage Amplifier 63 Table 7: Specifications of the voltage amplifier circuit components. Component Specifications 𝑅1,𝑅21𝑀Ω 𝐶1,𝐶21𝑛𝐹 M1 10/0.35 (𝜇𝑚) M2, M3, M4 0.15/0.13 (𝜇𝑚) 3.2.2 Features Ideally, an amplifier would have infinite voltage gain, input resistance (𝑅𝑖𝑛), Gain Bandwidth (GBW) range and slew rate. In opposition, it should have a null output resistance (𝑅𝑜𝑢𝑡), offset current and offset voltage. However, every single amplifier is different, distinguished by their configuration, operation principle and output. Therefore, some critical parameters to classify the amplifiers are described as following: • Offset voltage: a small offset caused by the inherent properties of the amplifier resulted from the mismatches in the input bias arrangement. This implies that even if the input signal is ground, there is a small voltage at the output. In order to solve this issue, an offset nulling method is commonly used. This consists of providing a reduced offset voltage in the input, making the output to have a zero voltage. • Unit gain frequency: corresponds to the frequency for which the gain is 0𝑑𝐵. • Open loop gain: the gain obtained when no overall feedback is used in the circuit and it is calculated by the ratio between the output voltage and the input signal. • Slew rate: in an ideal diode, regardless of the input signal frequency, no information is lost. In real-world, if the frequency of the input waveform is too high, the output can not handle, and the output signal is distorted. •Power Supply Rejection Ratio (PSRR): this is defined as the gain from the input to the output divided by the gain from the supply to the output of the amplifier, in the presence of supply noise. This parameter indicates the ability of the circuit to suppress any variation of the power supply to its output signal. • Quiescent current: is defined as the amount of current used when the circuit is operating at a null state, meaning it produces an output of zero. 3.2. Voltage Amplifier 64 • Supply voltage: the range of voltage supply for which all the presented characteristics are maintained. • Temperature behaviour: the range of temperature for which all the presented features are maintained. • Stability Specifications were settled to accomplish an efficient voltage amplifier with excellent performance. To match the piezoelectric element is essential to accomplish a simple circuit of one stage, with low power consumption, less than 10𝑚𝑊. A high gain of 1000 or more than 60𝑑𝐵to convert small amplitudes into usable signals is also required. Furthermore, a quiescent current of 1.6𝜇𝐴, a minimum supply voltage of at least 1.6𝑉, and PSRR from 0𝐻𝑧to 100𝑘𝐻𝑧of 130𝑑𝐵to 25𝑑𝐵, are requested. 3.2.3 Results Circuit simulations can be used to have a more practical understanding of an amplifier behaviour. Electronic simulations development has improved, taking into account not only ideal mathematical models, but also external factors, such as temperature, noise, or even process variations resulted from the fabrication. The amplifier basic operation is shown in Figure 52, extracted from Cadence software, using the 0.13𝜇𝑚 CMOS technology. A sinusoidal input waveform (𝑉𝑖𝑛) with 5𝑚𝑉of amplitude at a frequency of 10𝑘𝐻𝑧and voltage supply (𝑉𝑠𝑢𝑝𝑝) of 1.6𝑉is used. The maximum and minimum output voltage are 1.463𝑉and 67.77𝑚𝑉, respectively, which implies that the peak-to-peak voltage is 1.40𝑉. Thereby, the gain is 140 or 42.9𝑑𝐵, as expressed in equations 41 and 42. Due to the offset voltage, the output voltage is higher than 0𝑉. 𝐴𝜈=𝑉𝑜𝑢𝑡,𝑝𝑝 𝑉𝑖𝑛,𝑝𝑝 (41) 𝐴𝜈(𝑑𝐵)=20⋅𝑙𝑜𝑔(𝐴𝜈)(42) In Figure 53 is exhibited the output voltage variation according to the input and supply voltages. Since the circuit has an offset voltage, the output values correspond to (𝑉𝑜𝑢𝑡,𝑚𝑎𝑥-𝑉𝑜𝑢𝑡,𝑚𝑖𝑛). The purpose of this circuit is to amplify the piezoelectric signal. Herefore, the input voltage is a sinusoidal signal with an amplitude from 0𝑉to 1𝑉at 10𝑘𝐻𝑧. 3.2. Voltage Amplifier 65 0 1 2 3 4 5 6 ·10  4 0 0.5 1 1.5 Time (s) Voltage (V) Vin Vout Figure 52: Input signal (𝑉𝑖𝑛) and amplified output signal (𝑉𝑜𝑢𝑡) of the projected amplifier. 0 0.2 0.4 0.6 0.8 1 0 1 2 3 Input Voltage (V) Output Voltage (V) Vsupp = 1V Vsupp = 2V Vsupp = 3V Vsupp = 4V Figure 53: Output signal (𝑉𝑜𝑢𝑡) of the voltage amplifier through different input (𝑉𝑖𝑛) and supply (𝑉𝑠𝑢𝑝𝑝) voltages. When 𝑉𝑠𝑢𝑝𝑝increase also 𝑉𝑜𝑢𝑡is higher. Further, the gain is higher for low 𝑉𝑖𝑛, as exhibited in Figure 54, than for high input voltages. The resistance load is big enough to not affect the output - 𝑅𝐿=100𝑘Ω. The offset voltage (𝑉𝑜𝑓𝑓𝑠𝑒𝑡) is simulated by tying the input of the amplifier to the ground and measuring the output voltage. Once 𝑉𝑜𝑓𝑓𝑠𝑒𝑡 depends on the supply voltage, the lowest value measured for 𝑉𝑜𝑓𝑓𝑠𝑒𝑡 was 8.86𝜇𝑉, with a 𝑉𝑠𝑢𝑝𝑝of 2𝑉. The quiescent current (𝐼𝑄) is measured with 𝑂𝑉in the input and 𝑉𝑠𝑢𝑝𝑝=2𝑉and 𝐼𝑄=49.5𝜇𝐴 The supply current (𝐼𝑠𝑢𝑝𝑝) is the sum of the current on both stages. An input voltage of 5𝑚𝑉at 10𝑘𝐻𝑧and 𝑉𝑠𝑢𝑝𝑝 of 2𝑉is applied. The current in the first and second stage are 124.5𝜇𝐴and 57.13𝜇𝐴, respectively. Thus, 𝐼𝑠𝑢𝑝𝑝is 181.63𝜇𝐴. 3.2. Voltage Amplifier 66 0 0.2 0.4 0.6 0.8 1 0 50 100 150 Input Voltage (V) Gain Vsupp = 1V Vsupp = 2V Vsupp = 3V Vsupp = 4V Figure 54: Gain versus input voltages, according to the variation of supply voltages of the designed voltage amplifier. Through 𝐼𝑠𝑢𝑝𝑝and 𝑉𝑠𝑢𝑝𝑝, it is possible to calculate the power consumption of the amplifier as formulated in Equation 43. 𝑃=𝐼𝑠𝑢𝑝𝑝⋅𝑉𝑠𝑢𝑝𝑝 (43) Hence, the power consumption of the circuit is 363.23𝜇𝑊. To measure PSRR of the circuit, the schematic plotted in Figure 55 was used. An AC voltage of 10𝜇𝑉at 10𝑘𝐻𝑧(𝑉𝑑𝑖𝑠) was added to the supply terminal. The noise created by the power supply that is rejected by the amplifier is measured. Plus, a filtering capacitor (𝐶𝑓) of 5𝑝𝐹is added. GND GND GND GND Cf Vdis Vout + - Vsupp Figure 55: Circuit used for PSRR simulation of the amplifier. 3.2. Voltage Amplifier 67 The power supply gain (𝐴𝑝𝑠) is the ratio between the output voltage peak-to-peak and the supply voltage, as expressed in Equation 44. Since the amplitude of the output voltage is 6.505𝑚𝑉and the supply voltage is 2𝑉, 𝐴𝑝𝑠of 3.25⋅10−3was obtained. 𝐴𝑝𝑠=𝑉𝑜𝑢𝑡,𝑝𝑝 𝑉𝑠𝑢𝑝𝑝 (44) The nominal gain after a 5𝑚𝑉at 10𝑘𝐻𝑧input waveform, with 𝑉𝑠𝑢𝑝𝑝 =2𝑉was 134.2 (Equation 45). By applying the both gains in Equation 46, a PSRR of 41292was calculated, or 46.16𝑑𝐵(Equation 47). 𝐴𝜈=𝑉𝑜𝑢𝑡,𝑝𝑝 𝑉𝑖𝑛,𝑝𝑝 (45) 𝑃𝑆𝑅𝑅= 𝐴𝜈 𝐴𝑝𝑠 (46) 𝑃𝑆𝑅𝑅(𝑑𝐵)=10⋅𝑙𝑜𝑔(𝑃𝑆𝑅𝑅) (47) The temperature stability was also analyzed and the circuit behaviour changes with temperature. Figure 56 shows how the output signal changes with a temperature range from −40∘𝐶to 150∘𝐶. The output voltage peak to peak is higher for low temperatures and decreases with the increase of temperature. Using an input of 5𝑚𝑉at 10𝑘𝐻𝑧and 𝑉𝑠𝑢𝑝𝑝 =2𝑉, with −40∘𝐶, the 𝑉𝑜𝑢𝑡,𝑝𝑝is 1.48𝑉. At 150∘𝐶,𝑉𝑜𝑢𝑡,𝑝𝑝is 1.13𝑉. The difference in the outputs is reduced compared to the difference between the temperatures. Nonetheless, the circuit should work near from the environment temperature, 25∘𝐶. 3.2.4 Discussion A circuit capable of amplifying the piezoelectric signal to be further processed, with a high gain and low power consumption, was achieved in these simulations. The market offers a variety of amplifiers, more related to differential and operational amplifiers, but with the right features, those can be used for this application. Within the options are NCV952 from ON Semiconductor (ON ,2015), TLV314 from Texas Instruments (Tex,2016), and LMV321L from STMicroelectronics (STM,2014). 3.2. Voltage Amplifier 68 2.6 2.8 3 3.2 3.4 3.6 3.8 ·10  4 0 0.5 1 1.5 Input Voltage (V) Output Voltage (V)  40  C  18  C  2  C 23  C 44  C 65  C 87  C 108  C 129  C 150  C Figure 56: Output signal of the amplifier according to the variation of the temperature. A comparison between the proposed voltage amplifier and off-the-shelf components is presented in Table 8. The features of the commercial components were taken from the datasheets. These features were represented for a voltage supply of 3𝑉,2.7𝑉and 1.8𝑉for NVC95, LMV321L and TLV314, respectively. According to the specifications and goals of the systems, the proposed circuit shows an overall performance better than the commercially available components. Although the supply and input voltage range of this work are smaller than the others, for the final application only matters the reduced voltage supply and smaller input voltages. Therefore, those ranges are enough. Besides, the implemented circuit has the smallest offset voltage. Despite the gain of the proposed work being reduced, it is enough for input voltages in the range of 10−3𝑉. This was the primary purpose of the voltage amplifier, to increase the input signal into a range detectable for the other circuits. Moreover, the capacity for rejection the power supply noise in this work is average compared to the others. NVC95 has the best PSRR, but a very high power consumption. Regarding the power consumption, TLV314 has the lowest value. However, its PSRR and offset voltage are worse than the proposed amplifier. Therefore, the performance of this work is generally better than the others. 3.2.5 Summary A high gain and low power voltage amplifier, with two-stage, was designed. In comparison to commercial components, this circuit performs better for the purpose. The specifications which were not accomplished, in the worst case are reasonably good for energy harvesting applications. 3.3. Rectifier 69 Table 8: Comparison of the proposed voltage amplifier with commercial components. References NCV95 (ON , 2015) LMV321L (STM,2014) TLV314 (Tex, 2016) Proposed Amplifier Voltage Supply (V) 2.7 - 16 2.7 - 5.5 1.8 - 5.5 1 - 4 Input Voltage (V) 𝑉𝑠𝑠−0.3𝑉𝐷𝐷+0.3 𝑉𝑠𝑠−0.3𝑉𝐷𝐷+0.2 𝑉𝑠𝑠−0.5𝑉𝐷𝐷+0.5 −1-1 Offset Voltage (V) 0.6m 1m 0.75m 8𝜇 Gain (dB) 88 39 85 42.56 Power Supply Rejection Ratio (dB) 60 - 35 46.16 Quiescent Current (A) 0.7𝑚 120𝜇 122𝜇 49.5𝜇 Power consumption (W) 2.1𝑚 324𝜇 219.6𝜇 363.23𝜇 Temperature (∘C) −40-125 −40-125 −40-125 −40-150 Further improvements can be made to replace the capacitors and resistors by MOSFETs, to reduce the occupied area and proceed to the fabrication of an IC, using the 0.13𝜇𝑚CMOS technology. 3.3 Rectifier The power management circuit of an energy harvester extracts the energy generated by the transducer element, converts it into usable electric energy for a specific application and conveyes it to the requesting devices. The piezoelectric harvesters produce an AC signal that needs to be converted into a DC signal, through a rectifier, and storage to power up electronic systems (Sun et al.,2016;Herbawi et al.,2013). The vibrational energy harvesting systems have a broadband operating frequency range with low output power and voltage (Yang et al.,2013). Therefore rectifiers should be capable of handling a wide voltage operating range with low power consumption to achieve high PCE (Peters et al.,2011;Wong et al.,2016). CMOS technology is predominant in industries due to its low-cost and high-performance solution, as the major technology for fabricating IC and chips (Baker,2010). Although conventional rectifiers have simple topologies, they are not suitable for low power applications, due to its high power dissipation and leakage current, which 3.3. Rectifier 70 results in low efficiency. Rectifiers implemented in CMOS processes have been proposed as a better option for applications that require low power consumption, reduced power dissipation and present no reverse current, to achieve a high PCE. Therefore, the developed rectifier explores this technology, producing a circuit tailored to the desired requirements. This work aims to develop a CMOS rectifier with low power and high efficiency for energy harvesting applications. The specifications for this circuit are a low forward voltage, lower than 0.4𝑉, low power consumption, and a minimum reverse voltage or, in other words, a breakdown voltage, of around 30𝑉. Since the power consumption is limited by the leakage current in the subthreshold region, the circuit needs a low leakage current, from fA to pA range. Moreover, the rectifier needs to have a voltage and power efficiencies as high as possible. 3.3.1 Design and Modeling Recent literature was reviewed and described in section 2.3, making this work up to date on the newest techniques and selecting features to optimize the system. The choice was made from conventional, passive and active rectifiers, through iterative circuit implementation and consequent simulations. Diodes are basic components of passive rectifiers, thereby different Schottky diode models were simulated varying their SPICE parameters to understand which one has the best behaviour. An overview of the models is exhibited in Table 9, where 𝐼𝑆is the saturation current, N the emission coefficient, 𝑅𝑆the ohmic resistance, TT the transit time, 𝐶𝐽𝑂the zero-bias junction capacitance, 𝑉𝐽the junction potencial, M the grading coefficient, EG the activation energy, BV the breakdown voltage and 𝐼𝐵𝑉 the current at the breakdown voltage. The simulations were carried out by a sinusoidal input signal of 1.5𝑉at 50𝐻𝑧to a diode in series with a resistance of 1𝑘Ω. For each diode, its I-V characteristic curve and output signal are analysed. The Da1N4004 presented the worst performance, with a forward voltage (𝑉𝑓) of 0.3𝑉and with the output equals to the signal applied in the input terminal. The Dmurs360t3 has the best performance, thanks to its capability of partially nulling the negative half-cycles of the input signal and 𝑉𝑓=0.25𝑉. Both models, 1N5711 and HSMS2850, are capable of nulling the negative values of the input signal. However, HSMS2850 has higher gain and lower 𝑉𝑓than the 1N5711 model. The 𝑉𝑓is 0.2𝑉using the HSMS2850 diode and 0.1𝑉with the 1N5711. Therefore, the HSMS2850 Schottky diode model has the best behaviour. A full-wave rectifier was designed with four Schottky diodes, whose layout is illustrated in Figure 57. For lowvoltage IC applications, the 𝑉𝑓is responsible to reduce the PCE. Due to this, Schottky diodes with a low forward 3.3. Rectifier 77 Vdd Vout Vin + VinVss Vout Vss Vdd Vin + Vin - Vss Vout Vdd Vin M1 M2 M1 M2 M3 M4 M1 M2 M3 M4 (a) (b) (c) Figure 62: Schematic of the logic gate: (a) nand, (b) nor, and (c) not. 3.3. Rectifier 78 Table 13: Performance summary of different logic gates in a full-wave and two stage active rectifiers topologies. Features NAND⊙NOR⊙NOT⊙NAND⊗NOR⊗NOT⊗ Output Voltage (V) 997.3m 983.5m 875.6m 784.3m 780.4m 779.4m Power Conversion Efficiency (%) 6.91 31.71 31.97 25.4 38.08 40 Comparator Power Consumption (W) 193.3𝜇909n 230.1n 10.51𝜇1.11𝜇247.4n Power Consumption (W) 994.6𝜇1.26m 1.256m 12.3𝜇16.80𝜇17.71𝜇 Load Resistor (Ω)1k 1k 1k 50k 50k 50k ⊙Full-wave active rectifier topology, ⊗Two-stage active rectifier topology. 3.3.2 Proposed Rectifier This section presents the study and the design of a rectifier. A two-stage structure has been taking into consideration, along with a dynamic body bias circuit, as demonstrated in (Cha et al.,2012). The comparator implemented in this study is based on overcoming previous drawbacks and adapted to the required conditions. The impact of employing an MOSFET Bypass PMOS Diode (MBPD), as in (Peters et al.,2010;Li et al.,2014), is tested to enhance the system performance under undesirable work conditions. A simple circuit of a two-stage active rectifier, depicted in Figure 63, was designed, dismissing any resistor or capacitor. It consists of a passive stage implemented by a NVC and an active stage accomplished through an active diode, controlled by a comparator with BR, additionally in parallel a bypass PMOS diode MBPD. Under DC operating conditions, 𝐶𝐿is given by Equation 51, where 𝐼𝐷is the current flowing through the forwardbiased junction; 𝜏𝑇is the carrier lifetime; 𝑉𝑇is the thermal voltage, and n is the number of free electrons in the material (Baker,2010). Due to 𝐶𝐿, the ripple resulted from the AC-DC conversion can be reduced, smoothing the DC voltage (Peters et al.,2007). When the voltage from the rectifier is higher than that of the capacitor, 𝐶𝐿 3.3. Rectifier 79 RLCL NOT NVC Vi n + Vi n - M1 M2 M3 M4 Vout Figure 63: Projected two-stage active rectifier circuit. charges up. When the rectifier voltage drops down, 𝐶𝐿provides the required current from its stored charge, supplying the rectifier anytime it is not available. 𝐶𝐿=𝐼𝐷 𝑛⋅𝑉𝑇⋅𝜏𝑇(51) Negative Voltage Converter The NVC in Figure 64 is the first passive stage of the two-stage concept applied to the rectifier, responsible for converting the negative half-waves of the sinusoidal input into positive ones. Vin + Vin - Vout M1 M2 M3 M4 Vin + Vin - Vout M1 M2 M3 M4 (a) (b) Figure 64: Negative voltage converter circuit conducting for (a) positive and (b) negative half-cycles. 3.3. Rectifier 80 This conversion is simply accomplished by four standard MOSFETs: two NMOS and two PMOS. This stage is entirely passive. The transistors are driven by the alternating input voltage and work in an extensive frequency range, up to MHz. It eliminates the 𝑉𝑡ℎloss between the input and the output compared to a diode-connected MOS transistor. The working principle of NVC is illustrated in Figure 64. When |𝑉+ 𝑖𝑛| > |𝑉− 𝑖𝑛|the transistors M2 and M3 conduct, as depicted in Figure 64(a). Thereby, 𝑉+ 𝑖𝑛activates M2, allowing 𝑉− 𝑖𝑛to pass by and connecting to the ground, cancelling the negative half-cycle. Since M3 is turned ON by negative amplitudes on its gate, the current passes through it and 𝑉𝑜𝑢𝑡 =𝑉+ 𝑖𝑛. On the contrary, when |𝑉+ 𝑖𝑛|<|𝑉− 𝑖𝑛|, the circuits behaves as Figure 64(b). In this case, M1 and M4 are turned ON by 𝑉− 𝑖𝑛 and 𝑉+ 𝑖𝑛, respectively. M1 connects the positive half-cycles to ground, while M4 enables the current to connect to the output; therefore, 𝑉𝑜𝑢𝑡=|𝑉− 𝑖𝑛|. For low voltage design, a large width is needed to keep the voltage drop over the device low. The transistor size is chosen to keep its on-resistance (𝑅𝑂𝑁) low. Hence NVC reaches high efficiencies, even at low input voltages without overlooking the parasitic capacitances of large transistors. The trade-off on reducing 𝑅𝑂𝑁 is that it involves increasing the width (W) and length (L) ratio, resulting in higher parasitic capacitance and a larger silicon area. Apart from W and L, 𝑅𝑂𝑁is a function of electron and hole mobility (𝜇𝑛and 𝜇𝑝, respectively), oxide capacitance (𝐶𝑂𝑋), 𝑉𝑡ℎ, and signal voltage (𝑉𝐺𝑆) of the nand p-channel MOSFETs as formulated in Equation 52. The selected transistor size for this design is 10/0.13 (W/L) in 𝜇𝑚. Increase the transistor width further would result in a decrease in the voltage drop, but also a large area. No supplementary dynamic BR system is necessary on this stage, due to the bulk connections to the higher and lower voltage nodes. 𝑅𝑂𝑁 =𝐿 𝜇⋅𝐶𝑂𝑋⋅𝑊⋅(𝑉𝐺𝑆−𝑉𝑡ℎ)(52) The main advantage of this configuration is the ability to convert the input voltage up to MHz into a positive signal on the output. Otherwise, it can not charge the 𝐶𝐿and is not capable of controlling the current direction. Therefore a second stage is implemented to block the reverse current. Active Diode A second stage is added to the system since if the input voltage exceeds the 𝑉𝑡ℎ, current backflow occurs and 𝐶𝐿, directly connected, would discharge. The active diode, implemented by a PMOS switch controlled by a comparator, is represented by M1 in Figure 63. The current flows only in the output direction, preventing reverse current, which involves almost no voltage drop, working similar to an ideal diode. An active diode has a permanent 3.3. Rectifier 81 current consumption caused by the control circuit. The conduction voltage drop of the active diode is smaller than the forward-biased voltage of a standard diode. M1 drain and source terminals are equivalent to the anode and cathode of a diode, respectively, and the comparator detects the voltage between them. Furthermore, a BR circuit is established by M2 and M3 from Figure 63. Both transistors are connected to M1’s bulk to restrain latch-up. Due to this, a low-impedance path is generated between the power supply and the ground during the start-up process. As a result, M1’s bulk is switching between the higher and lower potential terminal, avoiding leakage current. M2 and M3 can have a reduced width considering only a slight current flows during the start-up phase. Comparator Active rectifiers that use comparators, the transistors have their gate voltage controlled, minimizing the reverse current that appears during operation mode changes. The purpose of this is to speed up the transistor switching process and eliminate this current. The comparator characteristics such as delay, power consumption, and output drive capability have a significant effect on the maximum achievable efficiency. A suitable comparator design with low power consumption and fast response is imperative to the rectifier. If the comparator is slow, only a portion of the available energy can be transferred to the capacitor, causing a high risk of current backflow. A high-speed comparator with high power consumption is also not desirable because the overall efficiency sharply decreases. The comparator architecture is obtained by a not gate, which is simple, quick and low power, as shown in Figure 65. The supply voltage (𝑉𝑠𝑢𝑝𝑝𝑙𝑦) is sourced from 𝐶𝐿. When the output voltage (𝑉𝑜𝑢𝑡) is higher than the NVC output voltage (𝑉𝑜𝑢𝑡,𝑁𝑉𝐶), the comparator output voltage (𝑉𝑜𝑢𝑡,𝑐𝑜𝑚𝑝) is high, turning OFF the switch and, consequently, preventing reverse current to occurs. Reversely, in the opposite condition, 𝑉𝑜𝑢𝑡,𝑐𝑜𝑚𝑝is a low signal to turn ON the switch. A current starved technique is added to reduce the current and diminish power consumption. The transistors M5 and M6 constitute the traditional not gate, working as an inverter, while M7 and M4 limit the current available to the inverter. The current is equal in each branch due to the current mirrors M1 and M4, and M3 and M7, hence 𝐼𝐷2 =𝐼𝐷4. In order to reinforce the current, M1 and M3 create p and n-type mirrors, respectively. The Equation 53 expresses the current in M2 (𝐼𝐷2), while operating in the subthreshold region, which means that the condition 𝑉𝐺𝐷 > |𝑉𝑡ℎ|is verified. Besides, since M2 has the gate tied to the drain 𝑉𝐷= 𝑉𝐺, and consequently 𝑉𝐷𝑆 =𝑉𝐺𝑆. 3.3. Rectifier 82 Vin Vdd Vout M1 M2 M3 M4 M5 M6 M7 Figure 65: Comparator circuit implemented by a not gate with starving current technique. 𝐼𝐷2=𝜇𝑝⋅𝐶𝑜𝑥⋅𝑊2 𝐿2 ⎡ ⎢ ⎣(𝑉𝐺𝑆−|𝑉𝑡ℎ|)⋅𝑉𝐺𝑆−𝑉2 𝐺𝑆 2⎤ ⎥ ⎦⋅(1+𝜆⋅𝑉𝐺𝑆)(53) The current in M2 only depends on its dimensions ratio, since the drain currents of M1 and M3 are the same and fixed by M2. Therefore M2 is smaller than the other to limit the current. Thus, the transistors’ dimensions are the same, except for M2, as shown in Table 14. Table 14: Dimensions of the transistors from the proposed comparator circuit. Transistor Width (𝜇𝑚) Length (𝜇𝑚) M1, M3, M4, M5, M6, M7 0.18 0.13 M2 0.15 0.13 Mosfet bypass PMOS diode The transistor M4 in Figure 63 is positioned in parallel with the switch, M1, ensuring a safe start-up of the active diode. It enhances the trustworthiness of the active diode under worst-case conditions, including process variation with high 𝑉𝑡ℎand extreme temperatures. Its only drawback is the increasing area, yet irrelevant when compared to the advantages. M4 stops operating and keeps a high ohmic state after the active diode starts working. 3.3. Rectifier 83 The need for a bypass depends on the process and operating conditions, thus to understand its requirement, an evaluation is presented by simulation in section 3.3.3. A width of 0.18𝜇𝑚in combination with a length of 0.13𝜇𝑚was used. 3.3.3 Results The proposed circuit is simulated using the Cadence environment and SPICE simulations tools, with the appropriate 0.13𝜇𝑚CMOS technology parameters. The most favorable dimension for M1, M2 and M3 from Figure 63 is 0.18/0.13 (W/L) 𝜇𝑚. The signals in Figure 66 show the behaviour of different sub-circuits. A sinusoidal input voltage (𝑉𝑖𝑛) with 1.5𝑉at 10𝑘𝐻𝑧is selected to perform the simulations. As expected, the 𝑉𝑜𝑢𝑡,𝑁𝑉𝐶signal only has positive values from converting the negative half-waves into positives ones. 0,0 0,1 0,2 -1,5 -1,0 -0,5 0,0 0,5 1,0 1,5 Voltage (V) Time (ms) Vin Vout, comp Vout, NVC Vout Figure 66: Operational principle of the NVC (𝑉𝑜𝑢𝑡,𝑁𝑉𝐶), the comparator (𝑉𝑜𝑢𝑡,𝑐𝑜𝑚𝑝), and the rectifier (𝑉𝑜𝑢𝑡), with 𝑉𝑖𝑛 as the input signal for each simulation. The simulated results reveal the not gate works properly and effectively as a comparator. When 𝑉𝑖𝑛is higher than half of 𝑉𝑠𝑢𝑝𝑝𝑙𝑦,𝑉𝑜𝑢𝑡,𝑐𝑜𝑚𝑝 is equal to the ground. In reverse, when 𝑉𝑖𝑛 is lower than half of 𝑉𝑠𝑢𝑝𝑝𝑙𝑦, 𝑉𝑜𝑢𝑡,𝑐𝑜𝑚𝑝is equal to 𝑉𝑠𝑢𝑝𝑝𝑙𝑦, which is a DC source of 1𝑉. An essential characteristic of the comparator is the power consumption, which the lower it is, the better. The power consumption of this comparator is 114𝑛𝑊. The output signal from the active rectifier, 𝑉𝑜𝑢𝑡, is exhibited in Figure 66. Every half-wave is applied to load up 𝐶𝐿. The input parameters for this simulation are 680𝑝𝐹and 50𝑘Ω, correlative to 𝐶𝐿and 𝑅𝐿, respectively. 3.3. Rectifier 84 As explained in the previous section, it is necessary to simulate the active rectifier with and without the MBPD. Figure 67 depicts how the maximum output voltage of the active rectifier (𝑉𝑜𝑢𝑡,𝑚𝑎𝑥) differs through the temperature variation from −20∘𝐶to 80∘𝐶, including or not the MBPD transistor. The input parameters are the same as in the previous simulation. In the absence of the MBPD,𝑉𝑜𝑢𝑡varies on an extension of 40𝑚𝑉. However, in the presence of it, 𝑉𝑜𝑢𝑡suffers a variation in a spectrum of 26𝑚𝑉. Beyond this, 𝑉𝑜𝑢𝑡,𝑚𝑎𝑥is significantly higher with the MBPD. Moreover, the rectified signal amplitude slightly decreases with the increasing of the temperature. -20 0 20 40 60 80 1,06 1,07 1,08 1,09 1,10 1,11 1,12 1,13 Circuit w/ MBPD Circuit w/o MBPD Output Voltage (V) Temperature (ºC) Fit curve circuit w/ MBPD Fit curve circuit w/o MBPD Figure 67: Output voltage according to the temperature variation, with and without the MBPD, and 2nd order polynomial fitting. The main aspects of rectifiers are the 𝑉𝑜𝑢𝑡,𝑚𝑎𝑥and its efficiency depending on the input frequency and 𝑉𝑖𝑛. The higher the efficiency, the less power is wasted. To measure the PCE is crucial to follow a few steps. Firstly, it is necessary to determine the input power (𝑃𝑖𝑛), as expressed in Equation 54. 𝑃𝑖𝑛,𝑟𝑚𝑠 =𝑟𝑚𝑠(𝐼𝑖𝑛⋅𝑉𝑖𝑛)(54) Then the power consumption of the comparator (𝑃𝑐𝑜𝑚𝑝), was calculated according to Equation 55 and the output power (𝑃𝑜𝑢𝑡) is expressed in Equation 56. 𝑃𝑐𝑜𝑚𝑝,𝑟𝑚𝑠 =𝑟𝑚𝑠(𝐼𝑑𝑑⋅𝑉𝑑𝑑)(55) 𝑃𝑜𝑢𝑡,𝑟𝑚𝑠 =𝑟𝑚𝑠⎛ ⎜ ⎝𝑉2 𝑜𝑢𝑡 𝑅𝐿⎞ ⎟ ⎠−𝑃𝑐𝑜𝑚𝑝,𝑟𝑚𝑠 (56) 3.3. Rectifier 85 Finally, it is possible to determine the PCE, dividing 𝑃𝑜𝑢𝑡by 𝑃𝑖𝑛as formulated in Equation 57 (Technologies, 2017). A particularity is the use of root mean square (rms) to obtain more reliable results instead of extrapolating. For an arbitrary periodic sinusoidal waveform, f(t), of period T, the value of rms is described in Equation 58 (Beranek and Mellow,2012). 𝑃𝐶𝐸=𝑃𝑜𝑢𝑡,𝑟𝑚𝑠 𝑃𝑖𝑛,𝑟𝑚𝑠 ⋅100 (57) 𝑟𝑚𝑠(𝑓(𝑡))=√1 𝑇⋅∫𝑇 0[𝑓(𝑡)]2⋅𝑑𝑡 (58) The PCE and the 𝑉𝑜𝑢𝑡versus frequency is illustrated in Figure 68, demonstrating that it works properly from 10𝐻𝑧to 3𝑘𝐻𝑧. At a certain point, the maximum effective frequency is achieved by the comparator, and sudden 𝑉𝑜𝑢𝑡 drops down, known as breakdown point. After this frequency, the active diode works unstable and must avoid operating under these conditions. At 1𝑘𝐻𝑧, the rectifier has the best performance with 40.4% of efficiency, while 𝑃𝑐𝑜𝑚𝑝is 113.9𝑛𝑊, and 𝑃𝑜𝑢𝑡is 17.7𝜇𝑊. This simulation uses a parametric analysis and 𝑉𝑖𝑛is 1.5𝑉. Without the BR and MBPD techniques the PCE of the respective rectifier was 3.46%. 10 100 1000 10000 1,10 1,12 1,14 1,16 1,18 1,20 1,22 1,24 Vout PCE Frequency (Hz) Output Voltage (V) 40,31 40,32 40,33 40,34 40,35 40,36 Power Conversion Efficiency (%) Figure 68: Output voltage and power conversion efficiency through different frequencies. The 𝑉𝑜𝑢𝑡,𝑚𝑎𝑥and PCE through different 𝑉𝑖𝑛are exposed in Figure 69. The simulation is performed at 1𝑘𝐻𝑧 with a 𝑉𝑖𝑛spectrum from 100𝑚𝑉to 5𝑉. Thus the working 𝑉𝑖𝑛range is measured and varies from 0.6𝑉to 4.5𝑉. The voltage efficiency (𝜂𝑣) is defined in Equation 59. The maximum voltage efficiency is 82%. 𝜂𝑣=𝑉𝑜𝑢𝑡 𝑉𝑖𝑛 ⋅100 (59) 3.3. Rectifier 86 0 1 2 3 4 5 -0,5 0,0 0,5 1,0 1,5 2,0 2,5 3,0 3,5 4,0 Vout, max PCE Input Voltage (V) Maximum Output Voltage (V) 0 10 20 30 40 50 Power Conversion Efficiency (%) Figure 69: Output voltage and power conversion efficiency values, according to input voltage variations. The simulated 𝑉𝑜𝑢𝑡and PCE versus 𝑅𝐿is plotted in Figure 70. The simulation is performed at 10𝑘𝐻𝑧with a 𝑅𝐿spectrum from 1𝑘Ωto 1𝑀Ω. The input parameters are the same as previously with an additional 𝑉𝑠𝑢𝑝𝑝𝑙𝑦 of 1𝑉. At 300𝑘Ω, the PCE reaches a maximum value of 47% with a 𝑉𝑜𝑢𝑡of 1.45𝑉, corresponding to a voltage efficiency of 96.7%. Thus, the circuit generates high amplitudes for large values of the ohmic load. Bellow 30𝑘Ω 𝑉𝑜𝑢𝑡strongly decreases, and at 9𝑘Ω, it reaches output values lower than the operational voltage. 103104105106 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 Vout PCE Load Resistor ( ) Output Voltage (V) 0 10 20 30 40 50 Power Conversion Efficiency (%) Figure 70: Simulated output voltage and power conversion efficiency through different ohmic load values. 3.4. Layout Design and Fabrication 93 Switch #1 #2 Switch #3 Diode Bridge Rectifier Two-stage Active Rectifier OpAmp + Peak Detector #1 OpAmp + Peak Detector #2 OpAmp + Oscillator Oscillator Figure 73: Complete layout of the energy harvesting system with each sub-circuit labeled. Figure 75 shows the layout design with all the sub-circuits projected in section 3.3 to construct the two-stage active rectifier. 3.4.2 Chip Fabrication The initial analysis of the die followed the protocol AN10706 from the NXP Semiconductors (POR). The guideline on how to handle bare dies, unlike packaged chips, is rigorous. The dies were delivered in two bare die containing trays, one from each wafer. Special attention has to be taken since the ICs are extremely sensitive to electric fields and over voltages, mechanical damage and surface contamination. An analysis is made to find any mechanical damages. A glass protection layer protects the circuits against mechanical influences, but the pads and bumps are exposed. Any mechanical forces in the shipping process could bend the die and generate piezo-voltages damaging the circuits or generating cracks and indents. Therefore, it is necessary to use the appropriate tools to handle bare die, avoiding damages. A class 1000 clean room is used in the process. A random choice of dies was visualized under a microscope, with magnifications from 2.5×to 100×. The dies are handled with a vacuum pick up tool, on top of a grounded 3.4. Layout Design and Fabrication 94 Inverter Switch Figure 74: Layout design of the analog circuit, including the inverter and the standard switch. workbench surface. Afterwards, the dies are stored in a secure and clean area to isolate and protect the products. The storage locker assures temperature between 8∘𝐶to 45∘𝐶, humidity between 25% to 75%, and no exposure to direct sunlight. The following figures show the die under the microscope split into several regions of interest. Figures 76 and 77 depict a micro-graph view of the proposed two-stage active rectifier and both analog switches, respectively, on a chip. The dies are wire bounded so the electrical analysis and circuit assembly can be performed. Table 17, summarizes the fabrication report of the piezoelectric energy harvester power management system on an IC die. The fabrication was a success, with 50 chips already made. Only a few quantities were fabricated to prove the concept behind the design and still be open to improvements. Section ?? gives more details concerning the chip fabrication. 3.4. Layout Design and Fabrication 95 Active Diode NVC Figure 75: Layout design of the two-stage active rectifier, including the negative voltage converter and the active diode. Table 17: Integrated circuit die fabrication report. Technology code MSGL13GE-B-48-1PAM9C04.1 Technology Limit File Q5Y0-MA.lim Wafer quantity 2 Equipment ID s600q4308 CARD ID 495 Manufacturing date 2020-02-15 18:49:00 Lot ID DPB813 Die quantity 50 pcs 3.4. Layout Design and Fabrication 96 Figure 76: Microscope view, with 50×amplification, of the two-stage active rectifier implemented on the IC chip. Figure 77: Microscope view, with 25×amplification, of the analog switch on the fabricated chip. 4 CONCLUSION 4.1 Conclusions The employment of an energy harvester to power a sensor node can make devices self-sufficient, enabling more cost-effective maintenance, and avoiding pollution, resulting in a favourable impact for the environment. This research dissertation contributes to the advance of high efficiency integrated energy extraction circuits. The main requirements for energy harvesting circuits are efficiency and autonomous operation. The circuit should operate at very low power consumption, as the energy produced by the transducer is already extremely low. As such, the circuit efficiency is of the utmost importance. The harvesting circuit should also operate independently from other devices on the final fabrication, allowing to work without the aid of external source. A physical layout was developed for fabrication purposes, 0.13𝜇𝑚CMOS technology was chosen with consideration to robustness, cost and performance. The developed work presents three main contributions. Firstly, the analog switch, based on the up-conversion technique. It was verified to be very useful for applications requiring temperature variation compensation and fast response to the input. The analog switch also has a low ON resistance and very high OFF resistance, providing an appropriated isolation during the nonconducting state. Secondly, the high gain and low power two-stage voltage amplifier was designed, outputting a significantly high voltage signal. Although this circuit is not resistor-less, it has a low power consumption. Lastly, the high efficiency and low power consumption two-stage active rectifier was designed, with ver good performance. By replacing the passive diodes by MOSFETs, the proposed active rectifier minimizes the voltage drop along the conducting path. A two-stage concept which consists of a passive stage with a negative voltage converter, and an active stage containing a not gate to drive the active diode switch, was designed. The circuit rectifies the input AC signals in a range between 0.6𝑉and 4.5𝑉, reaching a maximum 97 4.2. Future Work 98 output voltage of 3.45𝑉. The power conversion efficiency is 40.4% and a voltage efficiency of up to 90%. Low power consumption of 17.7𝜇𝑊is achieved by the rectifier, with the comparator consuming 113.9𝑛𝑊. The proposed design is suitable for the amplification, switching and rectification of low or ultra-low piezoelectric signal. Additionally, the integration of the circuits to CMOS designs should be straightforward, even with already existing designs. From this study, it is possible to observe a novel method to process an incoming signal from a scavenging energy system, using an analog switch, a voltage amplifier and an active rectifier. It is also possible to conclude that the use of this system to manipulate low power and amplitude signals, such as piezo-element voltages, is manageable. However, a more accurate technique for the voltage amplification must be developed, since the resistors and capacitors can be a problem to achieve even more accurate results. Extensive research was done in the circuit, focusing on power consumption reduction. The final layout design was conducted to fabrication, which allows for further studies and improvements. Although the system was made having in mind an integrated energy harvesting extraction interface for wireless sensor networks devices, it also has other applications in the industrial, commercial and biomedical sectors. 4.2 Fu ture Work The results of this study are promising and show the possibility of developing a harvesting interface circuit. In the future, more sub-circuits necessary for the concept will be developed. These components, analogous with the presented in this work, will follow the same baselines, such as low power consumption and high-efficiency structures. Even though simulation analysis can output very accurate results, to perform a complete circuit analysis, realworld experiments should be done, as the custom IC development is still a costly and time-consuming operation. In order to move forward, it is important to test the fabricated IC. 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