Super-Gain-Boosted AB-AB Fully Differential Miller Op-Amp With 156dB Open-Loop Gain and 174MV/V MHZ pF/µW Figure of Merit in 130nm CMOS Technology

Received March 14, 2021, accepted April 2, 2021, date of publication April 12, 2021, date of current version April 20, 2021. Digital Object Identifier 10.1109/ACCESS.2021.3072595 Super-Gain-Boosted AB-AB Fully Differential Miller Op-Amp With 156dB Open-Loop Gain and 174MV/V MHZ pF/µW Figure of Merit in 130nm CMOS Technology ANINDITA PAUL 1, (Member, IEEE), JAIME RAMÍREZ-ANGULO 2,3, (Life Fellow, IEEE), ALEJANDRO DÍAZ SÁNCHEZ3, (Member, IEEE), ANTONIO J. LÓPEZ-MARTÍN 4, (Senior Member, IEEE), RAMON GONZALEZ CARVAJAL5, (Fellow, IEEE), AND FRANK X. LI1, (Member, IEEE) 1Rayen School of Engineering, Youngstown State University, Youngstown, OH 44555, USA 2Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM 18003, USA 3Department of Electronics, National Institute of Astrophysics, Optics and Electronics, Puebla 72000, Mexico 4Institute of Smart Cities, Public University of Navarra, 31006 Pamplona, Spain 5Department of Electronic Engineering, University of Seville, 41092 Sevilla, Spain Corresponding author: Anindita Paul ([email protected]) This work was supported in part by the Spanish Government Agencia Estatal de Investigación (AEI) under Grant TEC2016-80396-C2, in part by the Consejería de Economía y Conocimiento of Junta de Andalucía under Grant P18-FR-4317 (both projects received support from the Fondo Europeo de Desarrollo Regional (FEDER)), and in part by the Consejo Nacional de Ciencia y Tecnologia (CONACyT) under Grant A1-S-43214. ABSTRACT A fully differential Miller op-amp with a composite input stage using resistive local common-mode feedback and regulated cascode transistors is presented here. High gain pseudo-differential auxiliary amplifiers are used to implement the regulated cascode transistors in order to boost the output impedance of the composite input stage and the open-loop gain of the op-amp. Both input and output stages operate in class AB mode. The proposed op-amp has been simulated in a 130nm commercial CMOS process technology. It operates from a 1.2V supply and has a close to rail-to-rail differential output swing. It has 156dB DC open-loop gain and 63MHz gain-bandwidth product with a 30pF capacitive load. The op-amp has a DC open-loop gain figure of merit FOMAOLDC of 174 (MV/V) MHz pF/µW and large-signal figure of merit FOMLSof 3(V/µs) pF/µW. INDEX TERMS Class-AB op-amp, fully differential amplifier, Miller-compensation, regulated cascode, resistive local common-mode feedback, voltage follower. I. INTRODUCTION Increasing demands for battery-operated portable electronics equipment like smartphones, wearable medical gadgets, and internet of things (IoT) devices drive the demand of IC’s operating at low voltages and low power and in some applications with high speed. It is necessary to scale down device sizes and supply voltages to introduce more functionalities and reduce power dissipation. However, scaling down of device-size and supply voltage generate negative impacts on device performances. Due to the scaling down of CMOS technology, the intrinsic gain Aiof MOS transistors has decreased continuously [1]. For example, it is typically in the order of Ai=gmro∼20-30 V/V in 130nm CMOS The associate editor coordinating the review of this manuscript and approving it for publication was Farid Boussaid. technology. Here gmis the transconductance gain and rois the output impedance of the MOS transistor. It can be shown that, as a first-order approximation, if transistors operate in strong inversion the intrinsic gain can be expressed by Ai =2/(λVDSsat ), where VDSsat =VGS-VTis the drain-source saturation voltage and λis the channel length modulation parameter (typically λ∼0.3-0.5 V−1in 130nm CMOS technology). In practice, the intrinsic gain is also strongly dependent on VDS. Transistors with low VDS have lower intrinsic gains. CMOS op-amps are indispensable for analog integrated circuits [2]–[4], such as, in switched-capacitor filters, delta-sigma modulators, A/D and D/A converters, etc. The op-amps should have a very high DC open-loop gain [5], high unity-gain frequency, high phase-margin, high slew-rate with low power dissipation to obtain high accuracy, speed, and fast settling time in a power-efficient manner. VOLUME 9, 2021 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ 57603 A. Paul et al.: Super-Gain-Boosted AB-AB Fully Differential Miller Op-Amp FIGURE 1. (a) Basic one-stage op-amp b) Conventional two-stage Miller op-amp c) Telescopic input two-stage Miller op-amp (d) Two-stage Miller op-amp with cascoded input/ output stages. One-stage and two-stage (Miller) op-amps (Figures 1(a) and (b)) have been widely used for many years in various applications. They have a DC open-loop gain AOLDC in the range of (Ai/2) <AOLDC < (Ai/2)2, FIGURE 2. Gain boosted Miller op-amp using regulated cascode technique. respectively. This gain is currently insufficient for most modern technology applications, especially for applications that require high accuracy and low distortion. It is possible to increase the Miller op-amp gain by a factor Aiusing a telescopic input stage with cascode transistors in the input stage, as shown in Figure 1(c). These cascode transistors provide higher impedance at the internal nodes Vo1, Vo1’, which increases the first stage’s gain. They do not degrade output swing since internal nodes Vo1 and Vo1’ require only a small maximum swing Vppo1,o10=VOUTM,P/AII of approximately 40mVpp,which corresponds to the rail-to-rail output swing divided by the gain AII ∼30 of the output stage. The open-loop gain can be boosted by another factor Ai by using cascode transistors in the output stage, as shown in Figure 1(d). However, due to the scaling down of technology, reduced supply voltages prevent the usage of cascoding devices in the output stage since they severely limit the output swing and do not allow resistive output loading which is required in many applications. The only choice to achieve higher open-loop gain and high output swing with low supply voltages is the utilization of two-stage or multi-stage cascaded amplifiers. The latter require complex nested Miller compensation schemes [6]–[8] and are in practice limited (for stability reasons) to a maximum of three cascaded stages, which allows to achieve only a moderate high op-amp gain AOLDC ∼(Ai/2)3. The telescopic input stage of an op-amp has a gain on the order of (Ai)2/2. It is possible to further enhance the gain of the telescopic stage using regulated-cascode technique [9]. This technique enhances the effective gain of cascode transistors by the gain AuxP, AuxN of auxiliary amplifiers used 57604 VOLUME 9, 2021 A. Paul et al.: Super-Gain-Boosted AB-AB Fully Differential Miller Op-Amp in a local negative feedback loop connected between the gate and source of the cascode transistors. Figure 2 shows an example of a fully differential Miller op-amp with a telescopic input stage that uses regulated-cascode transistors with auxiliary amplifiers AuxP, AuxN (assumed to have similar gains AAuxP =AAuxN =AAux). This increases the open-loop gain of the op-amp by the factor AAux to a value AOLDC ≈ ((Ai)3/4)AAux. Other high gain approaches based on regulated cascode transistors have been reported in [10]–[12]. Given that [10], [11] are cascoded one stage op-amps, these have very limited output swing in modern technology (50% or less of Vsupply). They cannot be loaded resistively since, in this case, their open-loop gains are severely degraded. As they are class A architectures, their slew rate is limited by the bias current. Therefore, they have very modest large-signal figures of merit like the current efficiency CE =IoutMax/ItotalQ where IoutMax is the maximum output current, and ItotalQ is the total op-amp quiescent current. In this paper, a power-efficient super-gain-boosted bandwidth enhanced fully differential class AB-AB Miller op-amp based on regulated cascode techniques with a DC open-loop gain AOLDC =(A6 i/8) (∼156dB in 130nm CMOS technology) is introduced. Very high gain pseudo-differential auxiliary amplifiers that do not require a common-mode feedback network are implemented using two novel single-ended folded double cascoded amplifiers in combination with a cascoded flipped voltage follower [13], [14] (CASFVF). The CASFVF operates as a DC floating voltage source that accurately sets the internal voltages X1, X1’ and Y1, Y1’ to convenient reference values Vref−X1 and Vref−Y1, respectively. This warrants that all transistors operate in saturation with the constraint of the low supply voltage. The CASFVF also generates a floating very low impedance node, which serves as AC ground for the pseudo-differential auxiliary amplifiers, as explained in Section-II. The utilization of a Miller architecture allows close to rail-to-rail output swing and resistive loading with minimum degradation of the open-loop gain. The input and output stages operate in class AB mode. This increases the op-amp current efficiency and the large-signal figure of merit. The circuits are explained in detail in the following section. The op-amp’s performances are measured using a) the conventional large-signal figure of merit FOMLS =(SR.CL)/PQ, b) the range figure of merit FOMR= VoutPP/Vsupply. Here PQis quiescent power dissipation, SR is the op-amp slew-rate, CLis the load capacitance,Vsupply is the supply voltage, and VoutPP is the output swing. The proposed op-amp’s small-signal figure of merit is measured using a conventional measure defined by FOMss =(GBW.CL)/PQ. Two new figures of merit related to the op-amp open-loop gain are also used in this paper. They are a) an open-loop gain figure of merit FOMAOLDC =(AOLDC .GBW. CL)/PQ and b) an area open-loop gain figure of merit AFOMAOLDC = (AOLDC .GBW. CL)/(Area. PQ). Both take into account the open-loop DC gain AOLDC of the op-amp which is not taken into account by other conventional figures of merit commonly used to measure the op-amp’s performance. The second one also takes into account the Silicon area required to implement the op-amp. The paper is organized as follows: Section-II describes the proposed op-amp designed in 130nm CMOS technology operating with ±600mV dual supplies and with a bias current IB=30µA. Section-III presents the proposed and conventional op-amps’ simulation results and comprehensive comparison with recently reported high gain op-amps. Post-layout simulations are shown in Section-IV. Section-V provides the conclusions. II. AMPLIFIER ARCHITECTURE A. TOPOLOGY OF PROPOSED OP-AMP The proposed fully differential (FD) super-gain-boosted op-amp (SGB-OPAMP) has a composite class AB input stage and a class AB differential output stage. The composite input stage is formed by a first stage (MINL1, MINL2, MINP, MINM., MTAIL) that uses resistive local common-mode feedback RLCMFB [15], [16]. The RLCMFB in the first stage boosts the gain-bandwidth product (GBW) and the open-loop gain by approximately a factor 3 and provides class AB operation at the internal nodes Vo1, Vo1’ at the output of the composite input stage. It does so by increasing the effective transconductance gmeff (by approximately the same factor 3) with respect to the transconductance gmIN of the differential pair transistors and by generating signal currents in the cascoded branch or in the second stage (MN1, MN2, MCN1, MCN2, MP1, MP2, MCP1, MCP2), which can be higher (by approximately a factor of 6) than the bias current, as explained in Section II.B. This increases the slew rate at the output nodes Vo1,Vo1’ of the composite input stage. The second stage uses regulated cascode techniques to increase the gain of the cascode transistors MCN1, MCN2, MCP1,and MCP2 by the gain AAux of auxiliary amplifiers. The combination of the first and second stages (enclosed in a red box in Figure 3(a)) is denoted here as the ‘‘composite input stage’’. The third (output) stage provides moderate gain ∼Ai/3 and close to rail-to-rail output swing. It uses a non-cascoded push-pull power-efficient and very simple free class AB [15], [17] technique to provide very large and symmetrical positive and negative output currents without additional quiescent power dissipation. This increases the current efficiency of the op-amp and the bandwidth as well. Two high gain pseudo-differential auxiliary amplifiers AuxN and AuxP are used to implement regulated cascode transistors MCP1, MCP2,and MCN1, MCN2,in the second stage, respectively. The pseudo-differential auxiliary amplifiers with gains AAuxN and AAuxP consist of two single-ended folded double cascoded amplifiers in combination with a cascoded flipped voltage follower (CASFVF) [14]. This CASFVF acts as a DC floating voltage source to set the voltages at nodes Y1, Y1’, X1, X1’ of the second stage at convenient values Vref −Y1and Vref −X1. For simplicity, it is assumed that AAuxN and AAuxP have similar values, i.e., AAuxN =AAuxP = AAux. The auxiliary amplifiers enhance the output impedance VOLUME 9, 2021 57605 A. Paul et al.: Super-Gain-Boosted AB-AB Fully Differential Miller Op-Amp FIGURE 3. (a) Proposed topology of the gain boosted op-amp (b) GBW boosted common-mode feedback network. (and open-loop DC gain of the op-amp) of the composite input stage at nodes Vo1(Vo1’) by a factor AAux∼A3 i/4. The voltages Vref−X1 and Vref−Y1 applied at the input terminals of the auxiliary amplifiers accurately set the values of the drain voltages of MN1, MN2,and MP1, MP2. This is very important in order to keep all transistors in saturation within the constraint of the low supply voltages used in modern technologies. Since the auxiliary amplifiers are pseudodifferential, they do not require a common-mode feedback network. As the op-amp is fully differential, the common-mode feedback (CMFB) network is used to set the op-amp output common-mode voltage to a mid-supply value VrefCMOUT =0 that allows maximum symmetrical peak-peak output swing. A resistive local common-mode circuit is also used in the CMFB network to achieve a similar unity gain frequency(fu) as in the differential amplifier. The CMFB loop has similar DC open-loop gain, GBW, and phase margin as the differential loop as it is required in FD op-amps. The CMFB circuit is shown in Figure 3(b). B. CLASS-AB OPERATION OF COMPOSITE INPUT STAGE All transistors in the composite input stage (except the tail transistor MTAIL which is scaled by a factor of 2) have the same W/L dimensions and the same bias current Ibias. The first stage of the op-amp uses RLCMFB. This increases the effective transconductance of the composite input stage by approximately a factor of 3 and generates signal currents in the cascoded branch which can be much higher than the bias current. This increases the current available to the compensation capacitor CCand increases the slew rate at the op-amp internal nodes Vo1,Vo1’. The maximum current in transistors MN1, MN2 can be expressed by (1). IMN1,2 max =βMN1,2(M+1)2VDS satMN 1,22 =Ibias M N 1,2(M+1)2(1) Here M=Ibias.RCMIN /VDSsatMN1,2(see Appendix A). Hence depending on the value of RCMIN and Ibias, enhanced positive and negative peak currents IpeakVo1,o10can be delivered to the compensation capacitor CCat nodes Vo1,o1’. In this design values RCMIN ≈8k,|VDSsatMN1,2| = 160mV, and Ibias =IbiasMN1Q=28µA were used. These selections result in M+1≈2.4, which leads to peak currents with values IMN1max ≈6IbiasMN 1Q≈6I bias ≈168 µA at nodes Vo1,o1. C. CLASS-AB OPERATION OF OUTPUT STAGE In order to obtain a large negative dynamic output current, a free class AB technique [17] is incorporated at the output stage using a capacitor CBAT and a large resistor Rlarge that provides a large time constant τ=RlargeCBAT . Thus, CBAT cannot discharge rapidly and acts as a floating battery for fast dynamic changes. At the quiescent condition, Rlarge provides a DC bias voltage VBN to MON1,2. The output transistors MON1 and MON2 are scaled up by factor four compared to the unit transistor sizes so that the output branches have quiescent currents with value IQMON1,2=IQMOP1,2=4Ibias. When the op-amp is slewing in the negative direction under dynamic conditions, nodes Vo1,1have large positive voltage changes. These changes are transferred to the gates of 57606 VOLUME 9, 2021 A. Paul et al.: Super-Gain-Boosted AB-AB Fully Differential Miller Op-Amp FIGURE 4. (a), (b) Block and (c) Schematic diagram of the AuxP amplifier. MON1,2through CBAT and provide large negative dynamic output currents that can be much higher than their quiescent current. These larger dynamic currents enhance the op-amp’s negative slew rate and the current efficiency CE, which is given by CE= IOutmax/IQTotal . Thus, the op-amp can achieve a higher slew rate, which improves its large-signal figure of merit FOMLS. D. GAIN OF AUXILIARY AMPLIFIERS Two high gain auxiliary amplifiers AuxN and AuxP are used to boost the gain of the op-amp with regulated cascode transistors [9] present in the second stage of the opamp. In order to provide enough headroom, an auxiliary amplifier AuxP with PMOS input stage (shown in Figure 4) is used for MCN1 and MCN2, whereas an auxiliary amplifier AuxN with NMOS input stage is used for MCP1 and MCP2. Auxiliary amplifier AuxN is not shown here, as it is a complimentary version of AuxP. The auxiliary amplifiers are pseudo-differential amplifiers. These consist of two single-ended folded double cascoded amplifiers. They share a cascoded FVF or CASFVF [13], [14] that generates an AC signal ground at node P. The CASFVF also operates as a DC level shifter. It sets accurately the voltages VX1,V0 X1and VY1, V0 Y1to the reference values VX1=V0 X1=Vref −X1and to VY1=V0 Y1=Vref −Y1in conjunction with the single-ended amplifiers using negative feedback. This is very important in order to ensure that all transistors in the composite input stage operate in saturated mode within the constraint of the 1.2V total supply used. In Figure 4 transistors, Maux1 and Maux1P implement single-ended folded double cascoded amplifiers with an AC signal ground at node P that corresponds to their source nodes. The CASFVF causes the impedance at node P to be very low (RP∼3/gm(gmr0)2∼20), and this node is used as a virtual AC ground with a quiescent voltage VP=Vref −X1+VSGQMFVF . In order to achieve a high gain, the single-ended auxiliary amplifiers use double cascoded transistors and double cascoded (high impedance) biasing current sources IB’∗∗. The bias current in the auxiliary amplifiers (Ibiasaux) is 10 times lower than the bias current used in the main op-amp, which in turn helps to reduce quiescent power dissipation. The output impedance at nodes X, X’ of the auxiliary amplifiers is given by (2). RX,X0=(roBP.gmCP1roCP1.gm CP2ro CP 2)|| ×(roaux1||roB).gmCN1roCN 1.gmCN2ro CN2(2) For simplicity, it is assumed that all transistors’ have equal gmand rovalues. Thus, RX,X0is given by RX,X0=(Ai)2ro/4. Hence, gain AAux of the auxiliary amplifiers is given by (3). AAux =gmaux1,1PRX,X0≈A3 i/4 (3) E. OPEN-LOOP GAIN ANALYSIS OF THE PROPOSED OP-AMP The proposed op-amp has three gain stages. The gain from the first stage AI=(VM0-VM)/Vid is moderate AI∼3and given by(4). AI=gmIN RM(4) The impedance at the output nodes Vo1, Vo1’ of the composite input stage (RVo1,o10) is given in (5). RVo1.o10=AAuxgmCP1roCP1roP1|| (AAuxgm CN1roCN1roN1) ≈AAuxgmr2 o/2 =AAux (Airo/2)(5) VOLUME 9, 2021 57607 A. Paul et al.: Super-Gain-Boosted AB-AB Fully Differential Miller Op-Amp The impedance of the output stage RoIII , which corresponds to the output impedance of the op-amp Rout =RoIII , is given by (6). RoIII =roON ||roOP (6) The DC open-loop gain of the op-amp AOLDC.is given by (7). AOLDC =AIAII AIII =gmIN RM.gmN1RVo1.gmOP.RoIII ≈gmIN RM.AAux A2 i/2.Ai/3≈gmRM.AAux A3 i/6 (7) In this design, a value AI=gmIN RM∼3V/V was selected. The AOLDC.obtained by combining (3) and (7)has a very high value as given in (8). AO L D C ≈A6 i/8(8) F. POLE-ZERO ANALYSIS OF THE PROPOSED OP-AMP Frequency Response of Auxiliary Amplifiers: Auxiliary amplifiers introduce negative local feedback loops that should have a gain-bandwidth GBWauxN,Pat least equal or greater than the main op-amp and sufficient phase margin (PMaux>60o). The main op-amp was designed for a unity gain frequency of 70MHz. In order to achieve stability of the local feedback loop of the auxiliary amplifiers and a GBWauxP,Ncomparable to the main op-amp, a small compensation capacitor CcauxP,N in series with a resistor RcauxP,Nare used at nodes X, X’ and Y,Y’. The Compensation capacitors in conjunction with the parasitic capacitances at nodes X, X’ and Y, Y’ provide dominant poles that determine the gain-bandwidth product of the auxiliary amplifiers GBWauxP,N. The GBWauxP of auxiliary amplifier AuxP (Figure 4) is given by GBWauxP =(1/2 π)gmaux1/Cx. Here, CXis the capacitance at node X at the output of the auxiliary amplifier. This feedback loop has a very high-frequency pole at the source terminal of the cascode transistor which is given by ωpVHFFB =gmCN1/CX1, where CX1is the parasitic capacitance at node X1. This pole does not affect the phase margin since it is essentially higher than GBWauxP. The only pole that affects the auxiliary amplifier’s phase margin is the high-frequency pole ωpHFN at the source of MCNA2 (node N). The value of resistor RcauxP is selected so that the zero that it generates, given by ωz=1/(RcauxPCcauxP ), matches approximately the high-frequency pole ωpHFN . For the proposed design, values CcauxN =130fF, RcauxN =9k , and CcauxP =60fF, RcauxP =18k were used in AuxN and AuxP, respectively which led to 93MHz open-loop unity gain frequencies in both amplifiers with a phase margin of approximately 60o. Figure 5 shows the open-loop gain and phase response of the auxiliary amplifiers AuxN and AuxP. It can be observed that both amplifiers have openloops gains of 77dB and 70dB, phase margin of 610, and unity gain frequencies of 94MHz (AuxN) and 93 MHz (AuxP), respectively. FIGURE 5. Open-loop frequency response of auxiliary amplifiers. Open-Loop Response of Op-amp: The op-amp is compensated using Miller capacitors CCin series with a resistor RC based on the conventional Miller pole splitting principle. The transfer function of the Miller compensated op-amp can be expressed approximately by (9). AOL(s) ≈AOLDC (1+s/ωz) 1+s/ωpDOM 1+s/ωpHFOUT 1+s/ωpM (9) Here AOLDC is the DC open-loop gain given by (8), ωpDOM is the dominant pole at the outputs of the composite input stage Vo1,1’ caused by Miller effect, ωpHFOUT is the high-frequency pole at the output nodes of the op-amp, ωzis a zero generated by the compensation resistor RCin series with CC,and ωpM,M0are the high-frequency poles at nodes M, M’ of stage 1. The high-frequency pole ωpM is given by (10). ωp M =1/(CMRM)(10) Here CM=CgdINP(1 +1/AI)+CgdINL +CgsMN1+CdbINL + CdbINP is the small parasitic capacitance at nodes M, M’. RM is given by (11). RM=RCMIN ||roINP||roIN L1(11) 57608 VOLUME 9, 2021 A. Paul et al.: Super-Gain-Boosted AB-AB Fully Differential Miller Op-Amp The value of RMplays a vital role in determining the gain AI=gmIN RMof the first stage and the position of the poles at nodes M, M’. There exists a tradeoff between the maximum gain of the first stage and phase margin of the op-amp. RCMIN should be smaller than roINP,Mand roINL1,2in that case, RM≈ RCMIN . The maximum value of RCMIN has to be selected in such a way so that the poles ωpM at nodes M, M’ satisfy the conditions: a) ωpM,M0ωpHFOUT and b) ωpM,M0 GBW. In that case poles ωpM,M0cause negligible degradation in the phase margin of the op-amp. Thus, the transfer function of the proposed op-amp can be simplified and approximated by (12). AOL(s)≈AIAII AIII (1+s/ωz) 1+s/ωpDOM 1+s/ωpHFOUT (12) In the proposed design values RCMIN =8kwere selected that lead to a moderate low gain AI∼3. As a result, the poles ωpM,M0are located at a factor 4 times higher than GBW. As indicated in the analysis below, the effective transconductance gmeff and GBW of the op-amp are also enhanced by the factor AI=3. These essential enhancements are achieved with a very modest increase in power dissipation and a negligible effect on PM. Nodes Vo1,1’ have a very high impedance and large capacitance due to Miller multiplication effect. Thus, the dominant pole ωpDOM at nodes Vo1,1’ can be expressed approximately by (13). ωpDOM ≈1 RVo1,10AIII CC (13) The Gain-bandwidth product (GBW) of the proposed op-amp is given by (14). GBW =AOLDC ωpDOM =(AIAII AIII )1/RVo1,10AIII CC =(AIAII )1/RVo1,10CC =AIgmN1RVo1,101/RVo1,10CC =(AIgmN1)/CC=gmeff /CC(14) The high-frequency poles at the output nodes are given by the usual expression (15). ωpHFOUT =geff mOUT CL (15) Here geff mOUT is given by geff mOUT =gmOP1,2+gmON1,2. Note that due to class AB operation the effective output transconductance of the op-amp at high frequencies is the sum of the transconductances of MOP1,2and MON1,2since capacitor CBAT connects the gates of MOP1,2and MON1,2at high frequencies. The zero ωzis given by (16). ωz=1/CCReff C(16) where Reff C=RC−1/ geff mOUT FIGURE 6. Open-loop Frequency response of Common-Mode Feedback network of Figure 3(b). Now, to achieve high GBW and high phase margin with low silicon area, CCis selected to have a moderately lowvalue CC=CL/7 and the output quiescent current is chosen with a value IQMON1,2=IQMOP1,2=4Ibias.RCwas selected so that the ωzapproximately matches ωpHFOUT . Open-Loop Gain of Common-Mode Feedback Network: The common-mode feedback network (CMFBN) of Figure 3(b) should also have a gain-bandwidth product GBWCMFBN equal to or higher than the GBW of the open-loop gain of the op-amp of Figure 3(a) and a phase margin of at least 60o. Hence a RLCMFB network using resistors with value RCM is also incorporated in this circuit. This in order to enhance its gain-bandwidth product GBWCMFBN . A moderate valued RCM is selected that provides a gain and GBW enhancement factor of also approximately 3. This results in high-frequency poles at nodes VCNTCM and VCNTCM1,which are also about four times larger than GBWCMFBN . With this, the CMFBN has similar open-loop gain, dominant pole, GBW, high-frequency pole, and zero as the differential loop of the op-amp. Figure 6 shows the open-loop frequency response of the CMFBN. It can be observed that it has a very high DC open-loop gain AOLDCCMFBN =156dB, 680 phase margin, and unity gain frequency fu=70MHz, which is comparable to the unity gain frequency of the differential loop of the op-amp. III. SIMULATION RESULTS The proposed op-amp was simulated with Cadence Design Framework II using commercial 130nm CMOS technology parameters provided by MOSIS [18]. Equal unit NMOS and PMOS transistor sizes (W/L)N,P=10µm/0.27µm were used in the input stage (see Table 1 for transistor sizes and other design parameters) of the proposed circuit. NMOS and VOLUME 9, 2021 57609 A. Paul et al.: Super-Gain-Boosted AB-AB Fully Differential Miller Op-Amp TABLE 1. Design parameters values for sections of proposed op-amp: differential op-amp, auxiliary amplifier, and CMFBN. PMOS transistors in the output stage were scaled by factors of 4 and 2, respectively. The op-amp was simulated with a bias current Ibias =30µA. To reduce quiescent power dissipation (PQ), the auxiliary amplifier’s bias current was scaled down by a factor of 10 i.e. Ibiasaux =3µA. Values Vref −X1= −380mV, Vref −Y1=400mV were used as reference voltages for the auxiliary amplifiers in order to keep all transistors in saturation within a safe range in the second stage. Dual ± 0.6V supply voltages and load capacitances CL=30pF on each output were used. Figure 7 shows the open-loop frequency responses of the Conventional Miller op-amp of Figure 1(b) (Conv-Miller), of the telescopic input 2-stage Miller op-amp (TEinp-Miller) of Figure 1( c), and of the proposed super-gain-boosted op-amp using the same bias currents. In order to make a fair comparison, the NMOS output transistors MON1,2of all op-amps are scaled up by the same factor 4 as it was done in the proposed op-amp. It can be seen that the conventional and telescopic input Miller op-amps have DC open-loop gains of 47dB and 71dB and lower unity gain frequencies (fu) of 23MHz and 26MHz, respectively. The proposed op-amp has open-loop gain, phase margin, and unity gain frequency of AOLDC =156dB, PM =74o ,and fu=70MHz, respectively. It can be seen that the proposed op-amp improves significantly (by 85dB to 109 dB) the open-loop DC gain and the unity gain frequency by a factor of approximately three compared to the conventional and telescopic input Miller op-amps. This comes at the expense of relatively moderate (30%) additional power dissipation. The common-mode rejection ratio (CMRR) of the Proposed, Conv-Miller, and TEinp-Miller are shown in Figure 8. Fully differential (FD) op-amps can ideally reject common-mode disturbances almost completely when no mismatch is taken into account. In this paper, the simulation of CMRR is performed by introducing a typical 1% mismatch in the transistors’ W/L dimensions and measured differentially. The CMRRs at DC of the proposed, Conv-Miller, and TEinp-Miller are 224dB, 88dB, and 105dB, respectively, at DC. The high CMRR of the proposed op-amp is achieved due to its very high AOLDC . The op-amp was simulated using the unity gain closed loop inverting amplifier configuration, shown in Figure 9, to determine transient response and output resistance. Equal Rin and Rfvalues of 100kwere used in the simulation The output resistances of the proposed, the TEinp-Miller, and the Conv-Miller op-amps are −74dB (0.2m), 7dB (2.2), and 34dB (50), respectively, at DC. Figure 10 shows the frequency responses of the output resistance of the op-amps. The proposed opamp has an extremely low output resistance at low frequencies due to its very high open-loop gain. The frequency responses of the op-amps in unity gain inverting amplifier configuration are shown in Figure 11. The amplifier using the proposed op-amp has a bandwidth (BW) of 55MHz whereas the amplifiers using TEinp-Miller and 57610 VOLUME 9, 2021 A. Paul et al.: Super-Gain-Boosted AB-AB Fully Differential Miller Op-Amp FIGURE 7. Comparison of open-loop frequency responses of conventional, telescopic input and proposed op-amps. FIGURE 8. CMRR of op-amps. Conv-Miller have bandwidths of 16MHz and 13MHz, respectively. The op-amps’ transient responses are shown in Figure 12 for a 5MHz input pulse with ±500mV amplitude. Positive and negative slew rates (SR) obtained from the proposed op-amp’s transient response are approximately equal FIGURE 9. Unity gain inverting differential amplifier. FIGURE 10. Output resistance of op-amps connected as unity gain amplifiers. FIGURE 11. Frequency response of op-amps in unity gain inverting amplifier configuration. with values 70V/µs and 69V/µs, respectively. Whereas the TEinp-Miller has SR+=9.5V/µs, SR=12 V/µs, and the Conv-Miller has SR+=8.7V/µs, SR−=10.2 V/µs. Neither the Conv-Miller nor the TEinp-Miller can follow the input signal due to their low slew rates and low current efficiency, as both of them are class-A op-amps. The proposed op-amp can provide 2.1mA positive and negative output peak currents at each output at the expense of a total of 572µA quiescent current. As the proposed fully differential opamp is driving two load capacitors of 30pF simultaneously, the current efficiency CE can be expressed as CE =ITot outMAX /IQtotal. VOLUME 9, 2021 57611