Enhanced Linearity in FD-SOI CMOS Body-Input Analog Circuits - Application to Voltage-Controlled Ring Oscillators and Frequency-Based sigma Delta ADCs

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS 1 Enhanced Linearity in FD-SOI CMOS Body-Input Analog Circuits – Application to Voltage-Controlled Ring Oscillators and Frequency-based Σ∆ ADCs Javad Ahmadi-Farsani, Student Member, IEEE, Virginia Z´ u˜ niga-Gonz´ alez, Student Member, IEEE, Teresa Serrano-Gotarredona, Member, IEEE, Bernab´ e Linares-Barranco, Fellow, IEEE, and Jos´ e M. de la Rosa, Fellow, IEEE Abstract—This paper investigates the use of the body terminal of MOS transistors to improve the linearity of some key circuits used to implement analog and mixed-signal circuits integrated in Fully Depleted Silicon on Insulator (FD-SOI) CMOS. This technology allows to increase the body factor with respect to conventional (bulk) CMOS processes. This effect is analyzed in basic analog building blocks – such as switches, simplestage transconductors and Voltage-Controlled Ring Oscillators (VCROs). Approximated expressions are derived for the nonlinear characteristics and harmonic distortion of some of these circuits. As an application, transistor-level simulations of two VCRO-based Σ∆ modulators designed in a 28-nm FD-SOI CMOS technology are shown in order to demonstrate the benefits of the presented techniques. Index Terms—Body effect, fully-depleted silicon-on-insulator, bulk-input analog circuits, voltage-controlled ring oscillators, sigma-delta modulators, analog-to-digital converters. I. INTRODUCTION ONE of the direct consequences of technology downscaling towards the nanoscale has been the redefinition of the Metal-Oxide-Semiconductor (MOS) transistor, in terms of the materials used for its fabrication as well as the structure of the device itself. Among other alternatives, two types of Fully Depleted (FD) devices are being used by semiconductor industry in 28-nm technology processes and beyond, namely: Fin-FET and FD Silicon-On-Insulator (FD-SOI). The latter has been postulated as one of the key technologies in those applications requiring ultra-low-power consumption – such as biomedical devices, wireless sensor networks, and Internet- of-Things (IoT) – thanks to its better performance in terms of transconductance efficiency, reduced impact of passive parasitic circuit elements, as well as improved noise isolation [1]. One of the best features of FD-SOI technology for analog design is its enhanced body effect, i.e. the dependency of the Manuscript received October 28, 2019; revised February 3, 2020; accepted March 1, 2020. This work has been partially supported by the EU Horizon 2020 Programme under grant 687299 NeuRAM3and by the Spanish Ministry of Economy and Competitiveness (with support from the European Regional Development Fund) under contract TEC2016-75151-C3-3-R. Javad Ahmadi-Farsani, Virginia Z´ u˜ niga-Gonz´ alez, Teresa Serrano- Gotarredona, Bernab´ e Linares-Barranco and Jos´ e M. de la Rosa are with the Institute of Microelectronics of Seville, IMSE-CNM (CSIC/University of Seville), Parque Tecnol´ ogico de la Cartuja, C/ Am´ erico Vespuccio 28, 41092 Sevilla, SPAIN, e-mail: [email protected]. threshold voltage, Vth, on the bulk biasing, as compared to standard (bulk) CMOS processes. Based on this effect and the physical structure of FD-SOI, the value of Vth can be tuned by using the body terminal of MOS transistors as control voltage, what can be exploited to enhance the performance of analog, mixed-signal and Radio-Frequency (RF) Integrated Circuits (ICs) [2]–[6]. Among other benefits, the tuning of Vth allows analog circuits to operate with reduced supply voltages, even within the order of a few hundreds of mV [1]. This requirement is becoming more and more necessary due to the limited dynamic range imposed by the reduction of supply voltages with technology downscaling below 1V. This fact precludes the use of conventional Operational Transconductance Amplifiers (OTAs) to implement the active elements of basic analog building blocks such as filters and Analog-to-Digital Converters (ADCs) [7]. Indeed, one of the trends to implement ADCs in deep nanometer nodes – either based on Sigma-Delta Modulation (Σ∆M) or SAR – is based on the use of Voltage-Controlled Ring Oscillators (VCROs) as basic building blocks. Although the first VCRO-based Σ∆ ADCs were based on replacing the conventional amplitude-based quantizers by time-based quantizers built with VCROs, these circuits have been also used to implement other basic building blocks of Σ∆ ADCs, SAR and hybrid SAR-Σ∆M ADCs [8]–[21]. However, in spite of the potential advantages of VCROs to design mostly-digital ADCs, the performance of these kinds of converters is degraded by the nonlinearity caused by the voltage-to-frequency (V-to-F) transformation carried out by VCRO circuits. In order to address this limitation, several strategies have been proposed, which include among others, the use of calibration [15], phase detection [16] or the so-called Gated switched- Ring Oscillators (GROs) [9], [14], [19]. In the majority of cases, reported linearization techniques imply an increased circuit complexity, thus loosing some of the benefits of VCROs as a digital-based alternative to analog signal processing [22]. In this scenario, this paper explores the use of FD-SOI CMOS technology to design body-input analog circuits with improved linearity as compared to their bulk CMOS counterparts. Based on the authors’ previous work [23], the main objective of this article is to investigate how the enhanced threshold-voltage modulation (body effect) presented in FDSOI technologies can be exploited to get a more linear performance in basic analog building blocks – such as OTAs, CMOS IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS 2 switches and voltage-controlled oscillators – and show their potential application to design analog circuits and systems. This improved linear performance can be achieved thanks to the higher linear relationship obtained between the threshold voltage and the bulk (body) voltage of FD-SOI MOS transistors. As an application, the presented techniques are shown for the linearization of VCROs implemented with current-starved inverter cells. A theoretical study of the V-to-F characteristic is carried out, which is verified by transistor-level simulations in a 28-nm FD-SOI CMOS technology. In order to show the potential benefits of the presented approach, transistorlevel simulations of a 1st-order and a 2nd-order VCRO- based Σ∆Ms are shown that demonstrate an improvement in the effective Dynamic Range (DR) thanks to its linearity enhancement with respect to conventional approaches. The rest of this paper is organized as follows. Section II gives some background on FD-SOI and compares its main features with respect to bulk CMOS process, paying attention to the body effect and enhanced Vth tuning. Section III analyzes the linearity of some basic analog circuits, such as simple OTAs and CMOS switches. Section IV and Section V apply the presented approach to increase the linearity of VCROs and frequency-based Σ∆ ADCs. Finally, conclusions are drawn in Section VI. II. BACKGROUND ON FD-SOI CMOS Fig. 1 shows a conceptual cross-section view of MOS transistors in 28-nm FD-SOI CMOS technology considered in this work as case study. As stated in [1], FD-SOI MOS devices behave as dual-gate transistors, having a front-side gate like in bulk CMOS technologies, and a back-side gate – denoted in Fig. 1 as Vbn and Vbp for the nMOS and pMOS transistors, respectively. It is well known that the body effect in CMOS can be expressed (for a nMOS transistor) as: Vth =Vth0 +γ·(p|2φF−Vbs|−p|2φF|)(1) where Vth denotes the threshold voltage; Vth0 is the threshold voltage when there is no body effect, i.e. the bulk-source voltage, Vbs, is zero; γis the body-effect parameter, and φF is the Fermi potential. A. Enhanced Body Effect of FD-SOI CMOS The back-gate terminal of MOS devices in Fig. 1 allows to implement a more efficient body biasing of Vth than in bulk CMOS, thanks to the wider voltage ranges (in the order of 3V) allowed by the parasitic zener diodes between N-well to substrate (in pMOS) and P-well to N-well (in nMOS) [1]. This allows to increase the body factor in MOS transistors while keeping a linear relationship between Vth and (Vbn, Vbp) as compared to the root square dependency of (1). This effect is shown in Fig. 2, which represents the variation of Vth with respect to Vbn and Vbp in a 28-nm FD-SOI CMOS process for different transistor sizes. The simulation data in Fig. 2 fit well with a linear function–also depicted in Fig. 2– given by: Vthn =Vthn0 −rn·Vbn (2) P-Substrate N-Well P-Well D,S Gate Drain, Source S,D Vbp Vbn pMOS nMOS Gate Bulk Bulk Fig. 1. Physical cross-section view of MOS transistors in 28-nm FD-SOI [1]. 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0.3 0.4 0.5 Vth (V) L=30nm,W=80nm L=84nm,W=80nm L=138nm,W=80nm L=192nm,W=80nm L=246nm,W=80nm 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 V(bn,bp) (V) 0.25 0.3 0.35 0.4 Vth (V) L=30nm,W=80nm L=30nm,W=260nm L=30nm,W=440nm L=30nm,W=620nm L=30nm,W=800nm pMOS nMOS pMOS nMOS pMOS nMOS L W (b) (a) Fig. 2. Variation of Vth with respect to Vbn and Vbp in 28-nm FD-SOI CMOS for different values of: (a) the transistor channel length (L) with minimum width (W= 80nm) and (b) width (W) with minimum length (L= 30nm). |Vthp|=|Vthp0|+rp·Vbp (3) where Vthn0 and Vthp0 stand for the zero-bias threshold voltages of nMOS and pMOS, respectively, and rnand rpare the corresponding body factors. The values of Vthn0 and Vthp0, are respectively Vthn0 = 326mV and Vthp0 = 335mV for minimumsize transistors. The body factors are rn≃70mV/V and rp≃80mV/V for minimum transistor sizes, slightly varying from rn≃68.8mV/V to rn≃77.8mV/V, and rp≃76.5mV/V to rp≃82.4mV/V for the sizes shown in Fig. 2. These bodyfactor values are higher than typical body factors of bulk CMOS1, thus allowing to increase the tuning range of Vth. Note also from (2) and (3) that the linear coefficients have opposite signs. This feature can be used to compensate for nonlinear dependencies in some body-input analog circuits, such as ring oscillators, thus allowing a better control of (Vgs- Vth), and consequently of the nonlinear V-to-F characteristic of VCROs as will be discussed later. B. Main Performance Metrics of FD-SOI CMOS In addition to the linear performance, the enhanced body factor of FD-SOI process may be advantageous to design analog and mixed-signal circuits in terms of other main performance metrics – such as transconductance efficiency, intrinsic gain and speed. A detailed analysis of all these design metrics –beyond the scope of this paper– can be found in [1], 1Note that in bulk CMOS processes, the body effect is not a linear function (see Eq. (1)). Therefore, the body factor is considered in this case as the maximum tuning range of Vth with respect to Vbs. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS 3 Vbn Vc IDS Vbn Vc ID1 (a) Vc ID2 +- (b) Fig. 3. Basic bulk-input nMOS OTA stages. (a) Single transistor. (b) Differential pair. 0 0.2 0.4 0.6 0.8 1 Vc (V) 0 0.5 1 gm (A/V) 10-4 Vbn=0 V Vbn=0.25V Vbn=0.5 V Vbn=0.75 V Vbn=1 V 0 0.2 0.4 0.6 0.8 1 Vc (V) 0 500 1000 1500 2000 Av (V/V) L=30 nm, W=2xL L=97.5 nm, W=2xL L=165 nm, W=2xL L=232.5 nm, W=2xL L=300 nm, W=2xL 0 0.2 0.4 0.6 0.8 1 Vc (V) 0 10 20 30 40 gm/ID (1/V) L=30 nm, W=2xL L=97.5 nm, W=2xL L=165 nm, W=2xL L=232.5 nm, W=2xL L=300 nm, W=2xL 0 0.2 0.4 0.6 0.8 1 Vc (V) 0 5 10 fT (Hz) 1011 L=30 nm, W=2xL L=97.5 nm, W=2xL L=165 nm, W=2xL L=232.5 nm, W=2xL L=300 nm, W=2xL (a) (b) (d) (c) Fig. 4. Illustrating some performance metrics for FD-SOI. (a) gmvs. Vcfor different values of Vbn. (b) gm/IDS vs. Vc. (c) Avvs. Vc. (d) fTvs. Vc. where these metrics are experimentally compared with a 28- nm bulk CMOS process. Instead, some basic expressions and simulations are given to illustrate the influence of Vth tuning. Let us consider the most simple case of a single nMOS transistor configured as a bulk-input OTA – conceptually depicted in Fig. 3(a). For the purposes of this work, let us assume that the transistor is in strong inversion and in saturation region, so that the drain-source current is given by2: IDS =βn 2(Vc−Vth)2(4) where βn=W LµnCox;µnis the mobility of electrons; Cox is the gate-oxide capacitance per unit area; and Wand L, are respectively the transistor channel width and length of the MOS transistor. The small-signal transconductance, gm≃βn(Vc−Vth), and its derived performance metrics, such as intrinsic voltage gain, Av≡gm/gds, transconductance efficiency, gmID ≃gm/IDS, and transit frequency, fT≡gm/Cg, can also benefit from the body biasing [1]. As an illustration, Fig. 4 shows the main simulated performance metrics for different sizing and ranges of Vcand Vbn. Note that these metrics can be optimized by properly setting the sizing and values of Vcand Vbn. 2This simplified first-order model is enough for the analysis presented here without loss of generality. More accurate models (including second-order effects) can be considered, although they will lead to more complex mathematical expressions, without adding significant information to the purposes of this work. 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Vbn (V) 1 1.5 2 2.5 3 3.5 fgmID Vc=400mV Vc=500mV Vc=600mV Fig. 5. Ratio between the transconductance efficiency in FDSOI CMOS and bulk CMOS, denoted as fgmID, versus Vbn, for different values of Vc. Moreover, some performance metrics can further benefit from the enhanced body effect provided by FD-SOI process [1]. For instance, the transconductance efficiency, gm/IDS ≃ 2/(Vc−Vth), can be improved as compared to bulk CMOS, by properly setting Vcand Vbn. This can be estimated by computing gmID considering two cases: bulk CMOS, i.e. Vth as given in (1) and FD-SOI, i.e. Vth expressed as in (2). This way, the ratio between the transconductance efficiency in FDSOI, gmIDFDSOI, and in bulk CMOS case, gmIDBULK, can be approximated for an nMOS transistor as follows: fgmID ≡gmIDFDSOI gmIDBULK = =Vc−Vthn0 −γ·(p|2φF−Vbs|−p|2φF|) Vc−Vthn0 +rn·Vbn (5) This is illustrated in Fig. 5, where fgmID is represented versus Vbn for an nMOS transistor with Vthn0 = 326mV, rn= 70mV/V, γ= 0.4√V, φF= 350mV and different values of Vc. Note that there is a set of values of Vcand Vbn that obtain a better transconductance efficiency than its bulk CMOS counterpart. Indeed, it can be shown that fgmID can be maximized for Vbn ≃2φF. A more detailed comparison of main performance metrics of FD-SOI versus bulk CMOS processes can be found in related literature [1]. The main objective of this work is to analyse how the enhanced body effect of FD-SOI CMOS can be exploited to improve the linearity of analog and mixedsignal circuits and systems. III. NONLINEAR PERFORMANCE OF BULK-INPUT BASIC ANALOG CIRCUITS: FD-SOI VS. CMOS Before studying more complex analog circuits, the analysis that follows focuses on some basic analog building blocks – such as single-transistor amplifiers and CMOS switches – as case studies to show how the use of back-gate voltage can be applied to improve the linearity performance of these circuits, and subsequently of the analog and mixed-signal systems based on them: such as oscillators, filters, ADCs, etc. As stated above, other performance metrics – such as electronic noise, finite dc gain, gain-bandwidth, etc. – are beyond the scope of this paper, which mainly focuses on how to get benefit of applying the wider tuning of Vth available in FD-SOI CMOS to enhance the linearity of analog and mixed-signal circuits. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS 4 A. Bulk-input single-transistor amplifier stages Let us assume that Vth depends on the bulk-source voltage, Vbn, i.e. according to the body-effect dependency of a bulk/standard CMOS process given in (1). In this case, it can be shown that, after applying a Taylor Series expansion of (4) as a function of Vbn, the drain-source current of an nMOS transistor (Fig. 3(a)) can be expressed as: IDS ≃IDS0 +g11 ·Vbn +g12 ·(Vbn)2+g13 ·(Vbn)3+... (6) where IDS0 =βn 2(Vc−Vth0)2, g11 =βn·γ·(Vc−Vth0) 2·√2φF g12 =βn·γ2·γ·√φF+√2·(Vc−Vth0) 32 ·(φF)3/2 g13 =βn·γ2·γ·√φF+√2·(Vc−Vth0) 128 ·(φF)5/2 (7) It is clear from (6) that the dependency of IDS on Vbn is strongly nonlinear, having multiple nonlinear terms (denoted as g1i), as compared to the quadratic dependency of IDS with respect to the gate-source voltage, Vc. Therefore, from the linearity viewpoint, using the bulk terminal as an input does not provide any advantage with respect to using the gate input terminal. Indeed, the second- and third-order Harmonic Distortion (HD) coefficients can be easily obtained from (7) as [24]: HD2≡g12 2·g11 ·|Vbn|=γ·√2φF+ (Vc−Vth0) 16 ·φF·(Vc−Vth0)·|Vbn| HD3≡g13 4·g11 ·|Vbn|2=γ·√2φF+ (Vc−Vth0) 128 ·φ2 F·(Vc−Vth0)·|Vbn|2 (8) where |Vbn|denotes the amplitude of a sinewave signal applied at the body terminal of the nMOS transistor shown in Fig. 3(a). Let us consider now that the MOS transistor is implemented in a FD-SOI technology. In this case, there will be a linear body-effect dependency given by (2), which for the nMOS transistor shown in Fig. 3(a), yields to a square-law dependency of the drain-source current given by: IDSFDSOI =βn 2(Vc+rn·Vbn −Vth0)2(9) In this case, considering a bulk-input differential input pair as that conceptually depicted in Fig. 3(b), the differential drain (output) current can be obtained from (9) as: Iout ≡ID1 −ID2 =βn·rn·(Vc−Vth0)·Vbn (10) that means a perfect linear relationship between the output current and the differential input signal applied at the bulk -1 -0.5 0 0.5 1 Vbn (V) -15 -10 -5 0 5 10 15 Iout ( A) Vc Vc Fig. 6. Simulation of the input-output characteristic of a bulk-input differential pair implemented in a 28-nm FD-SOI CMOS technology, where Vcis used as control voltage, ranging from 0.35V to 0.65V, as highlighted by the arrows. of both transistors3. This is illustrated in Fig. 6, where a simulation of the differential output current of Fig. 3(b) is shown for a 28-nm FD-SOI technology. In addition to get a more linear input-output characteristics as compared to a bulk CMOS process, the use of bulk-input FD-SOI OTA stages can use the gate voltage of transistors, Vc, as a gain control voltage – which is varied from 0.35V to 0.65V in Fig. 6. This feature adds some more degrees of freedom to make it easier to program the gain of a given OTA stage in more complex analog subsystems built with these kinds of OTAs. B. Bulk-terminal controlled CMOS Switches Switches – usually implemented as CMOS transmission gates like that illustrated in Fig. 7(a)– are also basic building blocks of analog circuits, for instance in Switched-Capacitor (SC) filters and ADCs [25], [26]. Most of these circuits have a sampling and hold (S/H) at the input, which usually limits the linearity of the overall system. Although there might be several circuit/physical effects limiting the nonideal/nonlinear operation of CMOS switches – charge redistribution and clock feedthrough – the discussion presented here focuses on the effect caused by the nonlinear switch-on resistance, since it can be reduced by using the enhanced body effect of FD-SOI as detailed bellow. Assuming that both nMOS and pMOS transistors in Fig. 7(a) are in ohmic region, it can be shown that the switchon resistance is approximately given by: Ron ≃1 gonp+gonn (11) where gonpand gonnstand for the switch-on conductances of the nMOS and pMOS transistors, respectively given by: gonn≃βΩn·(Vdd −Vthn −vin) gonp≃βΩp·(vin −Vss −|Vthp|)(12) 3Similarly to a conventional bulk CMOS technology, this perfect linear relationship can be degraded in practice by second-order effects of MOS transistors–not considered in this work without loss of generality. Moreover, the dependency of IDS and IDSFDSOI with respect to Vcis the same in both cases. Therefore, there would not be – a priori – any benefits of FD-SOI with respect to bulk CMOS process if a gate-input approach is considered in OTAs. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS 5 Vdd Vss Mn Mp vin vout Vbn Vbp (a) (b) ϕ ϕ vin vout Mn Mp Vbn Vbp Cs Fig. 7. Bulk-terminal controlled CMOS switches. (a) Switch-on schematic. (b) S/H circuit. where βΩ(n,p)stands for the βparameter of the (n,p)-MOS transistors in the ohmic region. Note that, as the value of Ron is a nonlinear function of the input signal, vin, being transmitted through the switch, then harmonic distortion is generated. Indeed, as discussed in [22], the harmonic distortion caused by this effect is mainly caused by the switches that are directly connected to the input signal given that the voltages at the input/output nodes of the remaining ones remain approximately constant over clock periods, and consequently Ron is approximately constant during the sampling phase time. Moreover, the nonlinearity increases with the ratio between the input signal frequency and the sampling frequency. Indeed, it can be shown that, using Volterra series method, the thirdorder HD due to nonlinear sampling is given by [25]: HD3≃πfinCsRon 2(VON −VT)2V2 in (13) where Vin is the input signal amplitude, Csis the sampling capacitance, VON denotes the switch-on voltage (either Vdd or |Vss|), and VTis the maximum (worst-case) value of Vthn and |Vthp|. However, the influence of the input signal on the switch-on resistance can be reduced if the back-gate terminal voltage of the nMOS and pMOS transistors in the CMOS switch (see Fig. 7(a)) are properly set to compensate for the effect of vin. This can be derived by substituting the Vth expressions of (2)- (3) in (12), yielding: gonn≃βΩn·(Vdd −Vthn0 −vin +rn·Vbn) gonp≃βΩp·(vin −Vss −|Vthp0|−rp·Vbp)(14) It can be inferred from (14) that by using an adaptive circuit mechanism – which can be controlled in some electronic devices by a Digital Signal Processor (DSP)– the effect of vin on the switch-on resistance can be minimized by properly setting the values of Vbn and Vbp. Indeed, the influence of vin on the switch-on resistance could be theoretically nulled if Vbn =vin/rnand Vbp =vin/rp. However, this is not feasible in practice due to the values of rnand rp. Nevertheless, the harmonic distortion caused by the nonlinear switch-on resistance can be attenuated up to some extend by properly tuning Vbn and Vbp. In order to illustrate this effect, let us consider a simple S/H circuit like that shown in Fig. 7(b). The distortion generated by the nonlinear sampling can be evaluated through simulations of this circuit as described in [22]. To this end, a sinewave signal 012345678910 Frequency (MHz) -100 -80 -60 -40 -20 0 PSD (dB/Hz) Vbn=1V Vbn=-1V -- Vbn=-1V -x- Vbn=1V -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 Vbn (V) -60 -55 -50 -45 -40 -35 -30 THD (dB) W=80nm W=160nm W=320nm W=640nm 0 1234 6789105 Frequency (MHz) -20 0 -100 -80 -60 -40 PSD (dB/Hz) (a) (b) Vbn= —1V Vbn= 1V Fig. 8. Effect of bulk voltage on the harmonic distortion of CMOS switches. (a) THD vs. Vbn for different CMOS switch sizes. (b) Output spectra for different values of Vbn (W= 640nm), showing how the power of harmonics decreases with Vbn. with 1-MHz frequency and 0.5-V amplitude is applied at the input and the voltage stored in Cs(Cs= 1pF in this example) can be collected at the clock rate to compute the Fast Fourier Transform (FFT) and calculate the Total Harmonic Distortion (THD). This is illustrated in Fig. 8(a), where the THD caused by the nonlinear switch-on resistance is depicted versus Vbn in a 28- nm FD-SOI technology, for different values of the width (W) of Mn and Mp in Fig. 7(a), by assuming the same size in both transistors and a minimum length. Note that THD – dominated by HD2in this single-ended circuit example – can be reduced up to 6 dB by the action of Vbn. This can be further improved if fully-differential circuits are considered. In this case, THD will be mostly dominated by HD3. Hence, increasing Vbn may lead to a reduction of more than 10dB. This is also illustrated in the output spectra shown in Fig. 8(b), where it can be seen how the power of harmonics due to the nonlinear switch-on resistance, can be reduced by increasing Vbn. Moreover, this enhanced linearity feature can be further improved if bulkcontrol voltages are combined with bootstrapped switches in FD-SOI [27], although the circuit complexity will increase. IV. APPLICATION TO VCROS: FD-SOI VS. BULK CMOS The simple circuit examples described in previous section show how the use of the bulk terminal of MOS transistors can be used to improve the linearity of basic analog building blocks such as OTAs and switches. Based on this strategy, a similar approach can be followed in order to reduce the nonlinearity of VCROs, which constitute one of the main limiting factors in the so-called time/frequency-based ADCs. To this end, let us analyse first how to apply the proposed technique to improve the linear characteristics of VCROs. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS 6 I1 I2 In Vc Vbn,p enb ph1ph2phn multi-phase output Vc Vbn,p Vc Vbn,p Vbn enb Mn1 Mn2 Mp2 Mp1 Vc vout vin Vbp Ipd Ipu pull-down net. pull-up net. CL Fig. 9. Single-ended schematic of the multi-phase VCRO/GRO considered in this work. Fig. 10. Transient simulation of a single output phase of the VCRO of Fig. 9. Note that the oscillation is activated as a function of the enable signal, enb. Fig. 9 shows a conceptual (single-ended) schematic of the VCRO under study. It consists of a pseudo-differential ring oscillator, in which the output of each inverter – denoted as phi (i= 1,2...n)– can be taken to generate a multi-phase output signal. Note that the circuit can be configured either as a GRO or as a VCRO, depending on the value of the enable signal –denoted as enb in Fig. 9. Thus, if enb switches between OFF (logic “0”) and ON (logic “1”) states, this will cause the VCO to oscillate or get frozen as illustrated in Fig. 10. Regardless the VCO is configured as a GRO or not, its operation is governed by different voltage signals: Vc,Vbn and Vbp. These voltages control the operation of each VCO inverter cell – depicted in Fig. 9. This circuit is a current-starved inverter, in which the current sources – implemented by transistors Mn1 and Mp1 – set the current flowing through the inverter – made up of transistors Mn2 and Mp2. The oscillation frequency, fosc, can be expressed as: fosc =1 2·mph ·τd(Vc, Vbn, Vbp)(15) where mph is the number of inverters, i.e. the number of phases in the VCRO, and τdstands for the propagation delay of each inverter-based VCRO cell. This delay depends on the charging/discharging time of the load capacitance, CL, at the inverter output, which in turns depends on the current flowing through the inverter – controlled by Vc,Vbn and Vbp. Thus, the overall propagation delay can be expressed as: τd=τLH +τHL (16) where τLH and τHL stand respectively for the charging (”Low- High”) and discharging (”High-Low”) transient times, which will be driven by the pull-up and pull-down networks of the inverter cell (see Fig. 9), such that: τLH ≃CL·∆voutLH Ipu , τHL ≃CL·∆voutHL Ipd (17) where Ipu and Ipd stand for the pull-up and pull-down currents, respectively. In order to obtain an accurate expression of (16), the transient response should be analyzed in different time intervals, according to the operation region of each transistor of the inverter at each time interval. However, for design purposes, some intuition can be obtained if the analysis is simplified by assuming that all transistors are operating in the saturation region during the transient response. This way, τLH can be computed as the time for an inverter output to reach a minimum voltage—∆voutLH = ∆voutHL =Vdd/2— in order to activate the next cell. Based on these assumptions, and considering that enb = 0V, it can derived from (16) and (17) that: τd≃CL·Vdd 1 βn·(Vc−Vthn)2+1 βp·(Vdd −|Vthp|)2 (18) where Vdd is the supply voltage and βnand βpstand for the βparameter of transistors Mn1 and Mp1, respectively. Replacing (18) in (15), it can be shown that: fosc ≃αosc h1 (Vc−Vthn)2+αβ (Vdd−|Vthp|)2i(19) where αβ=βn/βpand αosc =βn/(2 ·mph ·CL·Vdd). Note from (19) that, as expected, fosc depends on Vcand Vbn,p through the body effect of Vth(n,p). In order to obtain the V-to-F characteristics that relate fosc with the different control voltages, a Taylor series expansion of (19) as a function of those voltages can be derived. In order to simplify this analysis4, it will be assumed in (19) that (Vdd − |Vthp|)2 (Vc−Vthn)2, yielding to: fosc ≃αosc ·(Vc−Vthn)2(20) where Vthn depends on the bulk voltage of Mn1 as either (1) or (2), giving rise to different performance in terms of linearity. A. Bulk-Input Controlled VCROs Let us analyse first the effect of using Vbn as control voltage and that Vthn depends on Vbn according to (1) with Vbs =Vbn. Applying a Taylor series expansion of (20), it can be shown that: fosc ≃fq+kVCO1·Vbn +k21 ·V2 bn +k31 ·V3 bn +... (21) 4Similar conclusions can be derived if the first term in the denominator of (19) is neglected, i.e. if VcVthn. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS 7 where fqis the quiescent (or running) oscillation frequency, kVCO1is the VCRO gain and kn1stands for the n-th order nonlinear terms, respectively given by: fq=αosc ·(Vc−Vthn0)2 kVCO1=αosc ·γ·(Vc−Vthn0) √2φF k21 =αosc ·γ 8·φF·γ+(Vc−Vthn0) √2φF k31 =k21/4 (22) Let us consider that the VCRO cell is implemented using FD-SOI, and hence, Vthn depends on Vbn according to (2). Proceeding in a similar way, it can be shown that: fosc ≃fq+kVCO2·Vbn +k22 ·V2 bn (23) where kVCO2= 2 ·αosc ·(Vc−Vthn0)and k22 =αosc ·r2 n. Note from (23) that only a second-order nonlinearity is obtained in the case of FD-SOI bulk-input controlled VCRO cells, while in the case of conventional bulk processes, higherorder nonlinear terms (3rd-order, 4th-order, etc.) are obtained as shown in (21). This is illustrated in Fig. 11(a), where fosc/αosc is represented for Vc= 0.5V, Vthn0 = 326mV, rn≃70mV/V, γ= 0.4√V and φF= 350mV. An estimation of the nonlinear error can be computed as [28]: osc =fosc −fosc-ideal fosc-ideal (24) where fosc-ideal stands for the ideal (perfectly linear) V-to-F characteristic of the VCRO. Fig. 11(b) depicts the nonlinear error for both FD-SOI and bulk CMOS, corresponding to the V-to-F characteristics shown in Fig. 11(a). It is clear how the use of FD-SOI technology to apply the bulk terminal as a control voltage of VCROs can reduce the nonlinear error in several orders of magnitude. Moreover, only comparing the expressions of the 2nd-order terms in (21) and (23), it can be shown that k22 is lower than k21, and the ratio k22/k21 decreases with Vc. This is illustrated in Fig. 12 where k22/k21 is represented for Vc> Vthn0 for the same MOS parameters used in Fig. 11. This way, Vcand Vbn can be combined to reduce the nonlinearity of VCROs within a given frequency tuning range as will be demonstrated later by transistor-level simulations. B. Gate-Input Controlled VCROs Let us consider now the most conventional case in which the control voltage of the VCRO cell is the gate voltage of Mn1, i.e. Vc, and there is not any body effect, i.e. Vbn = 0 and Vbp =Vdd. In this case, it can be shown from (20) that the oscillation frequency is given by: fosc ≃αosc ·V2 thn0 −2αosc ·Vthn0 ·Vc+αosc ·V2 c(25) Comparing (23) and (25), it is clear that in both cases, quadratic dependencies on the control voltages are obtained. However, the second-order nonlinear term (k22) in FD-SOI case – eq. (23) – is attenuated by the body factor, which in 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Vbn (V) -10 -5 0 5 Nonlinear error (%) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0.2 0.4 0.6 0.8 1 fosc/osc (V2) Bulk CMOS FD-SOI Vc = 550mV Vc = 750mV Vc = 750mV Vc = (550,750) mV Vc = 550mV (a) (b) Fig. 11. Bulk-input VCROs: (a) fosc/αosc vs. Vbn. (b) Nonlinear error (osc). 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Vc(V) 0.01 0.015 0.02 0.025 0.03 0.035 k22/k21 Fig. 12. Comparison of the second-order non-linear term of the V-to-F characteristic in bulk-input VCROs: CMOS (k21 ) vs. FDSOI (k22). the 28-nm technology process is rn≃70mV/V, i.e. almost two orders of magnitude lower than the nonlinearity obtained in the case of conventional gate-controlled VCROs – Eq. (25). This is verified by transistor-level simulations as shown in Fig. 13, where the V-to-F characteristic of the VCRO in Fig. 9 is depicted. Note that, as predicted by the above theoretical analysis shown in eqs. (19)-(25) – also illustrated in Fig. 11, the use of bulk-input voltage drastically improves the nonlinear error, at the price of reducing the frequency tuning range with respect to the gate-input case. However, as can be shown in (23), both fqand kVCO can be tuned also through the gate control voltage, Vc. This feature increases the flexibility and reconfigurability of VCROs in terms of frequency tuning range, thanks to the combined action of both gate- (Vc) and bulk-input (Vbn) control voltages, as despited in the simulations shown in Fig. 13. As shown in Fig. 13(a), a wider tuning range can be achieved by using Vcas control voltage, due to its direct effect on fq. The overall tuning range of fosc is also controlled by Vbn through kVCO– see Eq. (21). However, the nonlinear error is much lower if Vbn is used as control voltage, as illustrated in the simulated error shown in Fig. 13(b). The effect of PVT variations and technology parasitics IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS 8 0.5 0.55 0.6 0.65 0.7 0.75 0.8 200 300 400 500 600 fosc (MHz) 0.5 0.55 0.6 0.65 0.7 0.75 0.8 Vbn, Vc (V) -10 -5 0 5 10 Nonlinear error (%) Gate-Input Bulk-Input Vc=620mV Vc=560mV Vc=500mV Vc=(500, 560, 620)mV Fig. 13. Transistor-level simulation of the V-to-F characteristic and nonlinear error of a VCRO in 28-nm FD-SOI CMOS: gate-input (Vc) vs. bulk-input (Vbn). Fig. 14. Effect of technology corners on the nonlinear error of the designed VCRO for Vc= 510mV. The notation used for the corners is the following: SS: Slow-Slow, TT: Typical-Typical, FF: Fast-Fast. have been taken into account in this design example. As an illustration, Fig. 14 shows the impact of the main technology corners of transistor models for Vc= 510mV. The worst-case nonlinear error is −0.6% – obtained for Fast-Fast (FF) corner when the input signal is close to 1V. Note that this value is still better than that obtained for gate-input VCRO topologies (see Fig. 13(b)). This combined effect of gate-control voltage and bulk-input signals can be exploited to improve the performance of some analog systems which require linear VCROs, such as frequency-based Σ∆ ADCs as described in the next section. V. APPLICATION TO VCRO-BASED Σ∆ ADCS In the last years, VCROs are being used to build Σ∆ ADCs in order to palliate the reduced dynamic range caused by the technology downscaling in conventional, amplitude-based, quantizers, and Σ∆M loop filters [8]–[19]. For the purposes of the analysis presented in this paper, and without the loss of generality, let us consider as case studies single-loop VCRO- based Σ∆M architectures based on the topologies proposed in [17], [18]. VCRO enb Vbn in mph fs up/ down counter reset Sampler out Analog Digital (a) (b) in mph kVCO fs=1 Ts mph fq 1 s VCRO up/down Counter out Sampler c1 1z1 mph Fig. 15. Bulk-input 1st-order VCRO-based Σ∆M. (a) Block diagram. (b) Equivalent behavioral model. (The system is implemented in practice using a pseudo-differential topology – similar to other VCO-based Σ∆Ms [17], [29]). A. First-order bulk-input VCRO-based Σ∆ Modulator Considering this approach, a bulk-input multi-phase VCRO like that shown in Fig. 9 can be used to implement a 1st- order Σ∆M as conceptually depicted in Fig. 15(a). The input signal of the Σ∆M is connected at the back-gate terminal (Vbn) of the VCRO (see Fig. 9), which implements the frontend integrator of the Σ∆M as shown in the equivalent behavioral model shown in Fig. 15(b) [18]. This VCRO drives a (up/down) counter, which counts the number of transitions of the input signal within a given time period, i.e. sampling time, Ts= 1/fs, with fsbeing the sampling frequency. As a result, this block acts as a digital differentiator and as quantizer, generating a digital representation of the input signal plus a phase quantization error [11], [17], as conceptually shown in the model of Fig. 15(b)5. The VCRO-based Σ∆M loop is closed by a Flip-Flop (FF) sampling register, which feeds the Σ∆M output back to the VCRO in order to reset its counter, thus avoiding its saturation [17]. In a more practical implementation – as the one used in this example – a pseudo-differential circuit realization is considered, so that the common-mode input frequency of Fig. 15(b) – corresponding to fq– can be nulled by the action of the differential topology. Thus, assuming a linear model for the quantizer blocks in Fig. 15(b), it can be shown that the Z-domain transform of the modulator output is given by: Y(z) = kVCO fs·Vin(z) + (1 −z−1)·Eφ(z)(26) where kVCO stands for the VCRO gain and Eφdenotes the Z-transform of the phase quantization error associated to the VCRO and the sampling process carried out in the FF register. In the circuit design used as a case study, eleven phases (mph = 11) will be used for the VCRO, and fosc can be tuned in a wide range by combining Vcand Vbn as shown in Fig. 13(a). A True Single-Phase Clock (TSPC) logic based FF is used to 5Note that the quantizer block included to model the behavior of the VCO- based integrator, emulates the effect of phase quantization [11], [17]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS 9 a b reset phi phi out Mn1 Mn2 Mn3 Mp1 Mp2 out Mp2 reset Mn3 Mp1 Ca Cb (a) (b) phi phi out Mn1 Mn2 (c) Ca Overlapping Interval phi phi Fig. 16. Proposed TSPC-based up/down counter: (a) Schematic. Equivalent circuit during (b) off-on transition of reset and (c) off-on transition of phi. implement the sampling register, since it consumes less power and occupies less area than conventional logic circuits [30]. Fig. 16(a) shows the proposed up/down reset counter circuit for a single VCO phase, phi, which is also based on TSPC logic. The counter is made up of a pull-down and a pull-up network. At rising edges of the reset signal, the output will be a “0” logic, whereas at rising edges of phi, the output will be a logic “1”. Let us consider first the operation of the pullup network of this circuit, i.e. during the off-on transition of reset signal as shown in Fig. 16(b). When reset signal is “0”, the implicit capacitance at node “b” will be charged so that the voltage at this node is Vdd and both Mn3 and Mp1 will be turned on for a short period of time. During this short period, the current flowing through Mn3 will charge the capacitance at node “a” so that this node will reach to a maximum value of Vdd −Vth, leading to a “0” logic at the output of the inverter. The action of Mn3 is enhanced by the positive feedback implemented by the auxiliary pMOS transistor, Mp2, which is placed between the input and output terminals. The opposite situation happens when the pull-down network is active during the off-on transition of phi(Fig. 16(c)). In this case, the inverted delayed version of phi, denoted as phi, switches from on to off with a given delay with respect to phi. During this delay period, both signals phiand phiare overlapped, so that both transistors Mn1 and Mn2 are on, and hence the current flowing through them discharges the implicit capacitance at node “a”, and the counter output is “1”. The VCRO-based Σ∆M of Fig. 15 has been designed in a 28-nm FD-SOI CMOS technology in order to show the benefits of using bulk-input VCROs – rather than gate-input VCROs – on the linearity of frequency-based Σ∆ ADCs. Fig. 17 shows this feature, by depicting two transistor-level simulated output spectra6of the 1st-order VCRO-based Σ∆M clocked at fs= 500MHz, with a 1.24-MHz input sinewave signal and two values of Vc, namely: Vc= 400mV and Vc= 500mV. It can be shown how the latter case yield to 6All transistor-level simulations shown in this paper were carried out in Cadence Spectre®, by including electronic noise to accurately estimate the in-band noise power as well as the impact of phase noise in VCROs. Nevertheless, a detailed study on the influence of phase noise is beyond of this paper, which is focused on the nonlinear behavior of VCROs. 104105106107108 −80 −60 −40 −20 0 Magnitude (dB) Frequency (Hz) Vc=500mV Vc=400mV Fig. 17. Output spectra of a bulk-input VCRO-based 1st-order Σ∆M for different values of Vc. a higher harmonic distortion –with HD3being in the order of −30dB– while a proper combination of bulk- and gatecontrol voltages of the VCRO can drastically reduce the harmonic distortion of the modulator. Note that if an input signal is applied at the gate terminal of the VCRO, i.e. using Vcas the input node of the Σ∆M, a similar noise-shaping performance can be obtained as compared to the bulk-input case. This is illustrated in the output spectra shown in Fig. 18, where the 1st-order VCRO-based Σ∆M is simulated by considering two cases: a gate-input (conventional case) and a bulk-input (proposed approach). In both cases, similar noise-shaping is obtained, and the estimated power consumption is 141.5µW in both cases. However, in the case of the input signal applied at the gate terminal, the maximum input Dynamic Range (DR) corresponds to a peak- to-peak input amplitude of only Vin-pp = 40mV, whereas in the bulk-input case, the input DR can be extended up to Vin-pp = 400mV, i.e. ten times higher in terms of the input DR of the ADC. Moreover, the input amplitude range of a conventional (gate-input) case can be increased, although the performance of the modulator will be degraded by the nonlinearity. This is illustrated in Fig. 19, where two cases are compared: an input sinewave with Vin-pp = 100mV applied at the gate of the VCRO (conventional case), and an input with Vin-pp = 400mV applied at the bulk (proposed approach). The main reason for such a difference in the input range of both cases, gate-input and bulk-input, is due to the wider variation of fosc with respect to Vcand Vbn – also illustrated in Fig. 13. Therefore, the frequency range, and consequently the input-voltage range, can be increased if the input signal is applied at the gate of the front-end VCO, at the price of reducing the input amplitude range. The effect of Vcand Vbn on the input DR is better illustrated in Fig. 20, that represents the Signal-to-(Noise+Distortion) Ratio (SNDR) versus the input signal amplitude, by considering a signal bandwidth of BW = 10MHz. Note that, although similar values of SNDR are obtained in both gate- and bulkinput cases, in the later case (bulk input), higher values of input amplitudes can be digitized. Thus, the Full-Scale (FS) input amplitude corresponds to 500-mV if the input signal is applied at the body terminal, whereas that FS is reduced