CMOS design of a current-mode multiplier/divider circuit with applications to fuzzy controllers

CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers 1 CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers Abstract Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/ divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design based on current-mode data converters is presented herein. Continuous-time algorithmic converters are chosen to reduce the control circuitry and to obtain a modular design based on a cascade of bit cells. Several circuit structures to implement these cells are presented and discussed. The one that is selected enables a better trade-off speed/power than others previously reported in the literature while maintaining a low area occupation. The resulting multiplier/divider circuit offers a low voltage operation, provides the division result in both analog and digital formats, and it is suitable for applications of low or middle resolution (up to 9 bits) like applications to fuzzy controllers. The analysis is illustrated with Hspice simulations and experimental results from a CMOS multiplier/ divider prototype with 5-bit resolution. Experimental results from a CMOS current-mode fuzzy controller chip that contains the proposed design are also included. I.- Introduction. Multiplier/divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems [1-19]. In this paper, we will focus on the application to fuzzy controllers, which are currently drawing a great attention. Typical fuzzy systems like Mamdani’s or Takagi-Sugeno’s types infer a crisp (not fuzzy) output by aggregating all the rules’ conclusions and performing a division. One of the main problems that appears when implementing a fuzzy system in hardware is the selection of an adequate divider circuit. The divider is usually the circuit that limits the speed, precision and interface capabilities (it is the output block) of the resulting fuzzy chip [1-9]. Several techniques to design multiplier/divider circuits have been proposed in the literature. Conventional log-antilog or bipolar translinear techniques have been employed in the analog fuzzy CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers 2 chips described in [1-2]. These structures can be realized with CMOS technology by using MOS transistors working in subthreshold region. However, the low current levels make them operate slowly [10]. Low operating speed is also the main limitation of multiplier/dividers based on the time-division technique [11]. The MOS translinear principle is another approach. In this case, the main limitation is a low resolution because the performance of the resulting circuits is very sensitive to deviations from the simple square-law model of the transistors in saturation, caused by length-channel modulation, mobility reduction or mismatching [3][12][13]. Another technique widely employed is to invert the behavior of a multiplier by using local feedback or by inserting it in the feedback path of an inverting amplifier. Performance of these multiplier/dividers depends primarilyontheperformanceofthemultiplierandtheamplifieremployed.Precisionismainlylimited by offsets associated with the input and output variables [3][14][15]. The analog fuzzy chips reported in [4-7] contain this type of multiplier/dividers. An alternative solution is the successive-approximation technique that employs two accumulators, as shown in Figure 1 [16]. The master accumulator approximates the value of the input signal, xnum, after N steps: (1) where xden is a reference signal and biis a digital output whose value is “1” (“0”) if the output of the master accumulator at the i-th step is smaller (bigger) than xnum. The slave accumulator takes the set {bi} and another reference signal, xp, as inputs and provides the following output: (2) Solving equations (1) and (2), it follows that: (3) with a quantization error of ±xden / 2(N+1). Hence, the output {bi} is the digital code of the division xnum/xden while xout is the analog discrete signal that represents the multiplication/division xp•xnum/xden. This technique has been employed in [17] to implement a voltage-mode multiplier/divider circuit, using A/D and D/A switched-capacitor (SC) cyclic converters as master and slave accumuxnum xden 2i–bi ⋅ i1= N ∑ ⋅≅ xout xp2i–bi ⋅ i1= N ∑ ⋅= xout xp xnum xden ----------- ⋅≅ CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers 3 lators, respectively. In that proposal, the analog output is provided after two stages. The first of them consists of N steps in which the N bits of the digital output are obtained. The digital code is converted to analog format during the next stage which again consists of N steps. SC successiveapproximation multiplier/dividers have been employed in the fuzzy controllers described in [8-9]. The CMOS multiplier/divider circuit proposed in this paper implements the successive-ap- proximation technique with current-mode algorithmic converters that occupy smaller area and are capable of working at lower voltage supplies than their voltage-mode counterparts. The A/D and D/A converters employed are coupled in the sense that they begin conversion by the same bit (the most significant bit, MSB) so that the analog and digital outputs are provided after only one stage. Besides, the response time can be smaller than N times the duration of the slowest operation because continuous-time data converters are employed. Several circuit structures to design these current-mode continuous-time algorithmic converters are proposed in this paper, following the work in [20]-[24]. They are discussed and compared in terms of static and dynamic features in Section II. The most efficient of these structures enables realization of small and fast multiplier/divider circuits suitable for applications of low or middle resolution (below 9 bits, which is higher than the resolution obtained by many of the above commented proposals). Performance of the proposed multiplier/divider circuit is illustrated with Hspice simulation and has been verified with a 2.4-µm CMOS prototype with 5-bit resolution. These results are included in Section III. Section IV illustrates with experimental results the application of the proposed design to implement the divider in a current-mode CMOS fuzzy controller chip. Finally, Section V provides some conclusions of the work. II.- Circuit design. Among the different designs of current-mode converters, algorithmic types are widely used because they are very simple and modular. If switched-current techniques are employed, an iterative cyclic or a pipeline design can be implemented. In the first case, a cell performs the conversion of all the N bits sequentially so that the response time and throughput of the converter is N clock cycles. In the second case, an extreme realization is to employ a cascade of N bit cells that provide a bit every clock cycle so that the response time is also N clock cycles but the throughput is only one [23][24]. If continuous-time techniques are employed, the data converter also consists of a cascade of N bit cells but no control circuitry is required to govern the signal transmission from one cell to another [20]. Besides, the response time can be smaller than N times the duration of the slowest operation. A disadvantage is that the converters are sensitive to mismatching among the CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers 4 cells, so that resolution is limited typically to 9 bits [25]. Considering applications of low or middle resolution like IC realizations of fuzzy controllers, we have selected continuous-time algorithmic converters to reduce the control circuitry and the response time. The resulting multiplier/divider circuit has the modular structure shown in Figure 2. EachbitcellcontainsanA/DandaD/Abitcellthatprovide,respectively,abitofthedigitaloutput, {bi}, and a contribution to the analog output, Iout. As described in Section I, the output {bi}isthe digital code of the current-mode division Inum/Iden while Iout is the discrete current that represents the multiplication/division Ip•Inum/Iden. Design considerations for the A/D and D/A bit cells are given in the following. II.a Design considerations for the A/D bit cells. Most reported algorithmic A/D converters [18-22] implement the multiplying algorithmic conversion. However, the dividing algorithmic conversion (illustrated in Figure 3) is more suitable for a divider circuit in order to have Iden as the full-scale current of the A/D converter (master accumulator) and Iden/2Nas the quantization step (refer to Equation (1)). Focused on this case, the input range for Inum is Inum ≤ Iden. Using a current-mode approach, the operations required by an algorithmic A/D conversion are performed by current mirrors and current comparators. Regarding accuracy, the limit is imposed by mismatching in the current mirrors due to systematic and random errors. Random errors are caused mainly by threshold voltage variations between ideally identical transistors, and can be reduced by employing large devices (with a typical limit of 9 bits) [25]. Systematic errors may decrease this potential resolution. On one hand, they are caused by a difference between the input and output voltages of the current mirrors, and on the other, by their finite output resistance. Regarding operation speed, this is limited by the transient response of the current mirrors and by the settling time of the current comparators. In the following, we propose and discuss three structures of A/D bit cells that combine different circuit techniques to improve resolution and speed. The starting point is the dividing version of the original multiplying-type A/D bit cell proposed in [20]. This cell, which will be named type_0 cell, is illustrated in Figure 4. Its resolution is limited mainly by the systematic errors that appear at the subtraction operation, R(Ii)-R(Iden/2i), where R(.) represents the replication operation implemented by a current-mirror. To reduce this problem, which is caused by the high voltage swing at node x, the proposal in [20] is to use active current mirrors, at the cost of more area and power consumption. On the other side, the speed of this type_0 cell is limited mainly by the re- CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers 5 sponse time of the current comparator, which is based on a cascade of inverters like that described in [26]. Type 1 cells: The first modification we propose to improve the performance of the type_0 cell is the type_1 cell which is illustrated in Figure 5. It implements the flow chart of Figure 3, so that its output current Ioi is given by: (4) where the bit bi is obtained from the comparison of R(Ii) with R(Iden/2i). The most important systematic errors, which appear at the subtraction operation, R(Ii)-R (Iden/2i), are reduced with the regulated output stage of the mirrors that replicate Iiand Iden/2i. This output stage is also exploited to perform as a fast current comparator like that proposed in [27][28]. Since the input to this comparator is capacitive like in the type_0 cells, the offset is virtually zero and resolution is not degraded. Hence, an A/D converter based on these cells can occupy less area than another based on type_0 cells for a given resolution and range of operation. Another advantage of type_1 cells is that their speed is higher since the comparator employed is faster. The cost to pay for it is a higher power consumption because one of the inverters in the current comparator acts as an amplifier and consequently, the quiescent current through it is not null. As usual, the higher the quiescent current the higher the speed. The fast response of the comparator and the capacitive coupling between nodes zand xmay cause glitches in the digital output. Let us analyze this problem in the bit cell shown in Figure 5. When biis “1”, the pmos transistor Mpthat acts as a switch is off, the voltage at node xis high (M3is off) and the voltage at node yis low. When bichanges to “0”, (R(Ii)<R(Iden/2i)), the pmos switch begins to conduct and the voltage at the high-impedance node xdecreases rapidly following the voltage at the low impedance node y. The drain-to-gate capacitance, Cgd, of transistor M3and the gate-to-source capacitance of transistors M1, M2, and M3, Cgs, cause a capacitive coupling between nodes z and x so that: (5) The voltage decrease induced at node zcan make R(Ii) be momentarily superior to R(Iden/ 2i). Hence, bican return to “1” if the comparator is too fast. In this sense, the type_0 cells can be seen as a conservative design because they employ slow comparators. Glitches have to be reduced if high-speed operation is required. A solution is to include the Ioi biℜIi () ℜIden 2i ---------    –biℜIi ()⋅+⋅= ∆Vz∆Vx Cgd Cgd 3Cgs + --------------------------- ⋅≅ CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers 6 transistor shown with grey lines in Figure 5. This transistor is conducting when biis “1”, making low the voltage at node x. Therefore, a change of bifrom “1” to “0” causes a momentary increment in the voltage at xand, indirectly, at z. Opposite to the above commented situation, this affirms the “0” value of bi. Figure 6 illustrates how glitches are reduced with this solution. It corresponds to the Hspice transient simulation of an A/D converter of 5 bits when the digital code changes from 10000 to 01111 (Iden is 16µA and Inum is a square pulse between 8.25µA and 7.75µA). Figures 6a and b show, respectively, the voltage of the least significant bit, b5, and the output current, Io5,of the 5th bit cell, when the bit cells contain (black line) or do not contain (grey line) the additional transistors to reduce glitches. Type 2 cells: The multiplying bit cells of the A/D converter proposed in [21] employ a current injection technique (addition of a bias current, Ib) to increase the speed of the current mirrors and to decrease the voltage swings at the nodes, thus reducing systematic errors. We have applied this technique to dividing-algorithmic converters. The resulting flow chart and, consequently, the resulting bit cells, which will be named type_2 cells, are simpler than that obtained for multiplying converters, as can be seen in Figure 7. The schematic of this type_2 cell, which also employs a fast current comparator, is shown in Figure 8. Its output current Ioi is given by: (6) where the bit bi is obtained by comparing R(Ii) with R(Iden/2i) + R(Ib). The design of these cells has to be more careful than that of type_1 cells to achieve the same resolution. The reason is that the bits biare obtained by comparing currents that suffer more replicas and, hence, they are susceptible of more errors. The most significant glitches of these cells appear when the nmos transistor that acts as a switch (Mnin Figure 8) begins to conduct. However, they are not so important as they were in the not improved type_1 cells because the difference between the voltages at nodes xand ywhen the switch is open are not so high. Consequently, the operation speed of these cells can be similar (slightly inferior) to that of type_1 cells. Type 3 cells: Another way to increase the speed of the current mirrors in the bit cells is to always ensure a not zero current through them by modifying the conversion algorithm. The flow chart illustrated in Figure 9a is the proposal in [22] for multiplying A/D converters. Applying this idea to a dividing A/D converter, we have obtained a simpler flow chart which is shown in Figure Ioi ℜIi ()bi –ℜIden 2i ---------    ⋅ = CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers 7 9b. It ensures that the output current Ioi of each cell is always bigger or equal to Iden-Iden/2i. Figure 10 illustrates the type_3 cell that implements this algorithm. The expression of Ioi is the following: (7) where bi results from comparing R(Ii) with R(Iden) - R(Iden/2i) The additional transistor drawn with grey lines in Figure 10 is included to reduce glitches that can be very important in these cells because the currents involved are high. Comparison: To perform a quantitative comparison of the four bit cells commented, they have been employed to design four A/D converters of 5 bits using the transistor parameters provided by a 2.4-µm CMOS technology. Their response time and average power consumption have been obtained from Hspice simulation. The results shown in Figure 11 reflect the worst case: the slowest transition (10000 to 01111) and the slow model parameters for the transistors. The left and right bars correspond to a full-scale current (Iden)of16µA and 64µA, respectively (with Ib=Iden/4 and a 5-V power supply). The best trade-off power/speed is achieved by the type_1 cells (response time of 260ns-140ns and power consumption of 0.62mW-1.49mW). They also offer a good trade-off between silicon area occupation and resolution. Therefore, they have been selected as the A/D bit cells of the proposed multiplier/divider circuit. II.b Design considerations for the D/A bit cells. The basic structure for an algorithmic D/A bit cell is a digitally controlled current mirror, as shown in Figure 12 with black lines. The bits bigenerated by the A/D part vary during the circuit operation as Inum or Iden change. Hence, the features of the analog output Iout provided by the multiplier/divider circuit greatly depends on the dynamic behavior of the D/A bit cells. An important condition that should be met to reduce glitches at the output is to ensure synchronization of all the switches of the D/A cells. This is achieved by using a master-slave scheme for the latches that store the digital output {bi} of the digital part. Figure 13 illustrates the inclusion of this latch in the bit cell schematic of an A/D- D/A multiplier/divider that employs type_1 A/D bit cells. When H is “1” the digital word that represents the quotient Inum/Iden is calculated. When S is equal to “1” (H is “0”), the bits {bi} that control the D/A part are updated at the same time. The bits {bi}donot change when H is ”1”, thus maintaining both the analog (Iout) and the digital ({bi}) outputs while performing a new division. Ioi ℜIi () bi +ℜIden 2i ---------    ⋅ = CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers 8 The longest delay of the D/A converter appears when the digital code changes from 00...0 to 11...1 because all the nodes a(in Figure 12) have to be loaded starting from Vss. The typical solution to reduce this delay is to replace the single switches by differential switches that always offer a conducting path for the current [29]-[33]. In our case, we have introduced the transistor Ma shown with grey lines in Figure 12. It reduces the voltage swing at node abecause when biis “0” the voltage at ais not Vss but a bigger value close to a reference voltage, Vref (which is Vdd in Figure 13). Figure 14 shows the Hspice transient simulation of a 5-bit D/A converter when the digital code changes from 00000 to 11111 (the reference current Ipis 16µA). The grey and black lines correspond, respectively, to a converter that uses simple and differential switches. When biincreases from “0” to “1”, the additional pmos transistor (Main Figure 12) switches off once bibecomes equal to Vq=V ref -|V Tp|, where VTp is its threshold voltage. At this value, thetransistorM1, which is on, begins to dischargethenode aso that the nmos switch rapidlybegins to conduct. Nonsymmetrical switching of these nmos transistors is the cause of the glitches that remain at the output. A simple solution to reduce this problem is to employ all the D/A bit cells identical. Another solution more costly is to choose the value of Vqas the value where the bits bi that change to “0” and to “1” meet together, as illustrated in Figure 15. This can be achieved by tuning the value of Vref externally, as proposed in [31]. III.- Experimental results. To validate our approach, a 5-bit A/D-D/A multiplier/divider circuit has been implemented in a 2.4-µm CMOS process. It employs type_1 A/D bit cells, like that shown in Figure 5 but without additional transistors for glitch reduction, and D/A bit cells, like that shown in Figure 12 (with Vref equal to Vdd). We estimated that by using type_1 A/D bit cells instead of type_0 cells the silicon area occupation was smaller and the operation speed was 5.7 times higher, with a power consumption that was 1.5 times higher. This prototype consists of a cascade of alternating odd and even cells which provide, respectively, the odd and even bits. This solution eliminates the pmos current mirrors between cells (shown in Figures 5 and 12), thus saving area but increasing glitches, as commented above (because the bit cells are not identical). The ratio between channel width and length of the nmos transistors is W/L=10µm/10µm. The geometry of the pmos transistors is W/ L=20µm/10µm for those in the first and second bit cells and 10µm/10µm for the others. This design allows working at voltage supplies as low as 3V with input and output current ranges of 18µA. Figure 16 shows the die photograph of the circuit, whose active area is 528µm x 145µm (0.077mm2). It is worth pointing out that the area occupied by this current-mode A/D-D/A design CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers 9 of 5 bits is more than 4 times smaller than a 4-bit successive approximation SC A/D converter that was designed with the same technology. Figure 17 illustrates the behavior of the circuit obtained experimentally by varying the numerator current, Ii=Inum, with the denominator current, Iden, equal to 12µA and the reference current, Ip, taken the values 9, 12, 15 and 18µA. Figure 18 shows the transfer function measured when sweeping the denominator current, IAD=Iden, with the numerator current, Inum, taken the values 0, 0.25, 0.5, 0.75, and 1µA, and the reference current, Ip, fixed to 12µA. The function IR, represented by the hyperbolic and continuous line, is the ideal division for the last case, Inum=1µA. The prototype was tested at a 2-V output voltage and a 3-V power supply. Since these circuits contain A/D and D/A cells, we have chosen the total error as a global figure to evaluate their precision. The total error contains the inherent quantization error as well as the gain, offset and non-linearity errors of both the A/D and D/A parts. The total error measured in this prototype is ±2.47% with an offset of 1.82% of the full-scale current, Iden=12µA (the inherent quantization error is ±1.56% with an offset of 1.56%). The 5-bit resolution (32 discrete output levels) was experimentally confirmed. The performance of the circuit is not affected by variation of parameters due to temperature variation. Another advantage is the monotonic behavior of the converters employed. The static power consumption measured for the full scale currents, Iden=Ip=12µA, is 318µW. The response time measured for a full scale step at the input Inum and with Iden equal to 12µA is 1.23µs. The design of this prototype was not optimized regarding glitches, as commented above. Hence, the response time can be faster if applying the solutions discussed in Section II. If this is done, Hspice simulations give a response time of 120ns and a static power consumption of 409µW for the same conditions as in the experiments. Obviously, better results can be achieved with modern submicron technologies. IV.- Application to a current-mode fuzzy controller chip. Zero-order Takagi-Sugeno’s fuzzy controllers are widely employed by their simplicity and control efficiency. They implement a set of rules like the following: Rule i: IF x1 is A1i and ... and xu is Aui THEN y is ci where xj(j=1,..., u) are controller input signals, yis the output, Ajiare linguistic values defined by fuzzy sets on the input universes of discourse, and ci are crisp values (i=1,...,R). The control output is obtained from an average in which each consequent value, ci, is weighted by the activation degree, hi, of its corresponding rule: CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers 16 CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers 17 xnum xout 7 b1 bN master xden xp Fig 1: Structure of a successive-approximator multiplier/divider. accumulator slave accumulator in out in out ref ref Iout Iden b1b2bN 1 2 5 6 81 26 Fig 2: Modular structure of the multiplier/divider proposed. 7 1st bit cell 1 2 5 6 8 7 Inum Ip 34343 5 Ii bi=1 bi=0 (no) Ioi >Iden 2i-Iden 2i (yes) Fig. 3: Flow chart of the dividing algorithmic conversion method. bi Iden 2i Ioi Iden 2i-1 Ii 1 2 8 Fig 4: Schematic of the type_0 cell. A/D part D/A part 2nd bit cell A/D part D/A part Nth bit cell A/D part D/A part x CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers 18 CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers 19 Ii + Ib Inum >Iden 2i+Ib bi=1 bi=0 (no) -Iden 2i Ioi (yes) (a) (b) 1bi Iden 2i-1 IiIoi Iden 2i x y 2 8 7 Fig. 7: Flow chart of the algorithmic conversion method with current injection: (a) Multiplying type [21]. (b) Dividing type. Fig 5: Schematic of the type_1 cell. Fig. 6: Comparison of the dynamic behavior of a 5-bit A/D converter based on the type_1 cells with additional transistors (black lines) and without them (grey lines): (a) Transition of the least significant bit, b5. (b) Output current Io5 of the last bit cell. 5.0 5.5 6.0 6.5 7.0 7.5 time (µs) -0.5 0.5 1.5 2.5 3.5 4.5 5.5 b5 (v) 5.0 5.5 6.0 6.5 7.0 7.5 time (µs) -2 2 6 10 14 18 Io5 (µA) (a) (b) Ii + Ib Inum >Iden+2Ib bi=1 bi=0 (no) - Iden Ioi (yes) x2 - Ib M1M2M3 z Mp CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers 20 x y Ii >Iden 2i Iden-bi=0 bi=1 (yes) +Iden 2i Ioi (no) bi Iden y x Iden 2i-1 Ii 2 1 bi Ib Iden 2i-1 Ii 1 2 Fig 8: Schematic of the type_2 cell. 7 Iden 2i Ioi 8 (a) (b) Fig. 9: Flow chart of the algorithmic conversion method with algorithmic restriction: (a) Multiplying type [22]. (b) Dividing type. Inum >Iden 2 b0=0 b0=1 (yes) +Iden 2 Ioi (no) bi=1 - Iden (yes) x2 >3Iden 2 bi=0 (no) -Iden 2 Fig 10: Schematic of the type_3 cell. 7 Iden 2i Ioi 8 Mn CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers 21 CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers 22 type_0 type_1 type_2 type_3 time (µs) 4 3 2 1 type_0 type_1 type_2 type_3 avg-power (mW) 4 3 2 1 5 Fig. 11: Comparison of the different A/D bit cells considered. bi a Ma c Fig. 12: Dividing algorithmic D/A bit cell. Vref Ip 2i-1 Ip 2i 3 5 Iout 4 1 bi H S Sbi S H bi H M1 Ma Iden 2i-1 Ii Ioi Iden 2i Ip 2i-1 Ip 2i Fig. 13: Schematic of the selected A/D-D/A bit cell. 2 34 5 6 7 8 M1 CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers 23 Fig. 14: Output current of a 5-bit D/A converter for a full-scale step when simple switches (grey line) and differential switches (black line) are employed. 0.5 0.6 0.7 0.8 0.9 1.0 time (µs) -2 2 6 10 14 18 22 26 30 Iout (µA) bi bj Vq Fig. 15: Value of Vq to reduce nonsymmetrical switching of the D/A part. Fig. 16: Die photograph of a 5-bit multiplier/divider prototype. CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers 24 Fig. 17: Experimental results of the circuit operating as a multiplier. Fig. 18: Experimental results of the circuit operating as a divider. CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers 25 (a) (b) Fig. 19: Experimental results of the proposed circuit integrated within a fuzzy controller chip: (a) Analog control output provided by the divider corresponding to the sweeping depicted in the control surface of (b). (c) An experimentally obtained control surface. (d) Several step responses of the discrete analog control output. Vx(v) 2.80 4.00 2.8 4 4 2.8 Vy (v) Vx (v) 10µs/div 2.45V 100mV /div 1.45V 32 0 Ix (µA) Io (µA) 32 0 Iy (µA) 0 40 (c) (d)