Pseudo-optimal five-level DCC modulation based on machine learning

Electrical Power and Energy Systems xxx (xxxx) xxx Please cite this article as: Pablo Montero-Robina et al., Electrical Power and Energy Systems, https://doi.org/10.1016/j.ijepes.2023.109677 0142-0615/© 2023 The Authors. Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/bync-nd/4.0/). Contents lists available at ScienceDirect International Journal of Electrical Power and Energy Systems journal homepage: www.elsevier.com/locate/ijepes Pseudo-optimal five-level DCC modulation based on machine learning✩ Pablo Montero-Robina a,∗, Francisco Gordillo b, Fabio Gómez-Estern c, Federico Cuesta b aAutel Iberia, S.L., Barcelona, Spain bEscuela Técnica Superior de Ingeniería, Universidad de Sevilla, Sevilla, Spain cEscuela Técnica Superior de Ingeniería, Universidad Loyola Andalucía, Sevilla, Spain ARTICLE INFO Keywords: Classification and regression trees Diode-clamped converter Mixed-integer linear optimization Multilevel converter ABSTRACT This paper presents a method for the control design of five-level DCC converters based on mixed-integer optimization and machine learning. The resulting controller is computationally simple and can be easily implemented on low-resource control hardware using simple nested ‘‘if-else’’ statements. The optimization problem is recalled from previous work by modifying the cost function to further enhance the dynamic performance. Additionally, and in contrast to previous works, the online implementation accomplished in this paper allows the system to cover a wider range of operating points. For this, the optimization problem is solved offline for several operating conditions, and the results are gathered into a dataset to train classification and regression trees (CARTs), which are later used online. Due to the generalization capability of the CARTs, a more flexible and less resource-intensive implementation is achieved which is capable of operating at points outside the ones considered in the training dataset. The resulting control strategy is compared in simulation and experiments with several alternative approaches found in the literature. This approach can be extended to other power converter topologies, allowing the implementation of optimized modulations. 1. Introduction Trends in energy consumption encourage researchers to look for feasible solutions that reduce the cost of grid infrastructure. Highpower industrial applications have been the scope of this search, as they facilitate the delivery and consumption of energy from the highvoltage distribution grid in a straightforward way [1]. Therefore, the voltage limits of power electronics devices are a major concern in the field [2]. In this context, multilevel converter topologies emerged as a predominant solution [3]. The use of serialized switching devices enables them to support larger grid voltage by dividing it among the connected devices [4]. Furthermore, they can achieve more accurate modulation and reduction of current distortion, which facilitates the fulfillment of the grid codes EN50160. However, as the number of levels increases, so does the control complexity as there are more possible switching states. Besides, the additional capacitors have to be balanced, which involves additional control objectives. If this aspect is not taken into account, the system may not behave properly or even suffer irreversible damage. There are a large number of multilevel converter topologies, and each has its advantages and drawbacks [5]. This paper focuses on ✩This work has been funded by the Spanish Ministry of Science, Innovation and Universities under grant PID2019-109071RB-I00/AEI/10.13039/501100011033 and by Junta de Andalucía-FEDER grant P20-01116. ∗Corresponding author. E-mail addresses: [email protected] (P. Montero-Robina), [email protected] (F. Gordillo), [email protected] (F. Gómez-Estern), [email protected] (F. Cuesta). the diode-clamped converter (DCC) [6]. The three-level neutral-point- clamped (NPC) converter belongs to this topology and is one of the most investigated, accepted, and used multilevel converter topologies in the industry. However, the five-level one still finds some reluctance. This is due to the increase in the number of switching vectors (125) and the control objectives that must be considered. Therefore, designing a proper modulation algorithm to command the switches is vital for the integration of this topology. The modulation must satisfactorily implement the desired output voltages at the same time that the capacitors must be evenly charged. This is not an easy task, and many different approaches are currently found in the literature as shown below. A strategy based on space-vector modulation (SVM) that solves the modulation and balancing issues is the one presented in [7], which uses a combination of a small switching vector and two outer ones in such a way that balancing capabilities can be achieved using the redundant vectors of the small one. The work shown in [8] further takes this approach to produce a switching sequence that guarantees smooth transitions between switching periods. These approaches will be referred to as space-vector-based algorithms (SVBA) from now on for comparative purposes. In another line, [9] uses carrier-based PWM with zero-sequence injection in such a way that it takes into account the https://doi.org/10.1016/j.ijepes.2023.109677 Received 30 October 2022; Received in revised form 12 August 2023; Accepted 20 November 2023 International Journal of Electrical Power and Energy Systems xxx (xxxx) xxx 2 P. Montero-Robina et al. capacitor voltage balance for a five-level DCC. However, this approach only offers balancing capabilities for applications with low power factor values or low modulation indices, as operating with high modulation indexes does not guarantee capacitor voltage balancing in five-level DCC [8]. Alternatively, work [10] presents a modulation strategy that decouples the achievement of the output voltage from the capacitor voltage balancing control accomplishing both control objectives simultaneously. Thus, it is referred as integrated control modulation (ICM). For this, the modulation could use any level within a switching period. Furthermore, the original ICM (OICM) is modified (MICM) to improve performance. This strategy is based on the implementation of PWM for every level. Any of the aforementioned approaches present a solution for the modulation and voltage balancing of five-level DCC but they are not optimized in terms of number of commutations, that is, using the minimal amount of levels every switching period. In the field of optimal approaches, one well-known option is the finite-control set model predictive control (FCS-MPC) [11]. For this, at every sampling interval, all possible switching states are evaluated with a cost function that covers, with different weights, the control objectives: current reference tracking, capacitor voltage balancing, and reduced number of commutations. Therefore, the optimum switching state is selected and implemented in the next sampling interval. Note that the performance of the system depends on how these objectives are weighted in the cost function. As a noticeable disadvantage, the FCSMPC selects only one switching state in each sampling period, losing the advantage the PWM has of commuting inside the switching period. In [12], by defining a mixed-integer linear programming optimization problem, with control objectives as constraints and key variables to account for the optimal result, a cost function leads to the best solution in terms of duty ratios for every phase at every level. Therefore, in contrast to FCS-MPC, the PWM is still used, as the outputs of the optimization problem are the levels that will be used every switching period. Unfortunately, this optimization problem has a large computational burden and cannot be executed online. A solution was presented in [13], where the optimization problem was solved offline for an operating point under steady state conditions, and the optimization results were stored in a look-up table (LUT)—this approach will be referred to as LUT from now on. However, large variations in the modulation index or the power factor can change the conditions under which the LUT was obtained, and hence impede the fulfillment of the control objectives. Consequently, the LUT approach seems infeasible for systems that require a wider range of operating points. To overcome this and to avoid the need to solve the optimization problem at every sampling instant, we propose in this paper a machine learning-based approach, with improved optimization, that deals with this lack of generality and difficulty of online implementation in such a way that the resulting online algorithm takes the form of decision trees, which are simple and require very low computational load. In summary, an easy-to-implement algorithm is obtained that seeks optimality while still using PWM. Machine learning is probably the fastest-spreading technical field today, boosted by the steady increase of processing power, the abundance of data thanks to mobile and IoT technologies, and the refinement of data science algorithms. In automatic control, neural networks have been the most common machine learning tool since the 1990s [14]. whether as a predictor, a tool for optimization, decision making, or determination of the control action. Machine learning algorithms have also been used for a long time in converter control applications [15,16]. In a recent paper [17], real-time implementation of DC/DC power converter control based on deep machine learning techniques is analyzed. See [18], and the references therein, for a detailed overview of artificial intelligence applications for power electronics, including expert systems, fuzzy logic, metaheuristics, and machine learning. In machine learning, two main types of learning can be outlined: supervised and unsupervised. The former considers both input and output datasets in the learning algorithm, while the latter is mainly used in classification algorithms that do not require feedback and thus is less common in control problems. A well-known supervised classification algorithm is Classification and Regression Trees (CART) [19] or their extension, Random Forests [20]. CART can capture complex and nonlinear relations and can also be very helpful in detecting critical variables, in addition to other advantages in the field of automatic control [21]. Therefore, the CART algorithm is a well established method and it is well suited to the problem considered in this paper, since choosing which switches to commute is equivalent to a classification problem. In this paper, the CART algorithm is used as a mean to directly obtain the results of the optimization problem from the system state information with no need to execute online traditional solvers. For this, the information obtained by solving the optimization problem offline along a full grid cycle [12,13], which is previously codified (the input–output dataset), is used to train several CARTs. These CARTs will associate the codified system state (input) with the corresponding codified optimal modulation (output). Afterwards, the resulting trees are implemented online using the same codification for the inputs and decodification for the outputs. In addition, by considering several operating points simultaneously in the training datasets, a more general solution is expected, which will overcome the limitations of using lookup tables which are valid for particular operating points. To increase the generality of the resulting trees, the use of quantitative information is avoided in the tree training. That is why raw input data is codified into qualitative variables, that provide enough information of the system state, before feeding the CART algorithm. In the same way, the output of the tree is a coded number with qualitative information about how to implement the modulation in each sampling time (it will be called modulation policy in the following). Simulation and experimental results are presented showing the validity of the method for different working conditions compared to existing approaches. In particular, the novelties of this paper compared to [13] are the following: •The proposed method avoids the use of LUTs to obtain the modulation criteria and uses the decision trees obtained from the CART training. Such decision trees are less resource-demanding than LUTs. •Several operating points are considered in the training datasets, achieving a general solution, as will be shown later in simulations and experiments. •Additional performance features are introduced into the cost function to achieve best steady-state performance. •A comparison by simulation with several approaches: LUT [13], FCS-MPC [11], OICM–MICM [10], and the original SVBA [7]. •Experimental comparison with the enhanced SVBA approach with balancing capabilities [8]. This approach, which combines offline optimization and Machine Learning to perform online modulation could be consider for other types of topologies. This could include MMC for HVDC, as the large number of submodules does not pose a problem for offline optimization resolution. Furthermore, additional objectives could be included in the cost function depending on the target application. The outline of the paper is given as follows: •Section 2: A description of the five-level DCC as a grid-connected rectifier is presented along with its mathematical model. Moreover, the strategy for controlling the currents and dc-link voltage of the converter that is later used in simulation and experiments is also introduced, highlighting the role of the modulation process on which this paper focuses on. •Section 3: The modulation stage as an optimization problem is formulated and discussed in further detail as in [13]. Some improvements are presented. It is also shown that this optimization is carried out offline and, thus, the optimization execution time is not a problem for online modulation operation, but the need of an alternative for online implementation is demonstrated. International Journal of Electrical Power and Energy Systems xxx (xxxx) xxx 3 P. Montero-Robina et al. Fig. 1. Circuit of a three-phase five-level diode-clamped converter. •Section 4: The pre- and post-processing stages for the optimization results as well as training and online implementation of the decision trees are presented. •Section 5: The comparison in simulations in MATLAB-Simulink® with alternative control approaches is shown and discussed. •Section 6: Experimental results are depicted and compared with other control techniques. •Section 7: Some conclusions are drawn. 2. System model and control scheme 2.1. System model This paper focuses on a three-phase, five-level DCC connected to the grid in AC/DC configuration. The diagram of this converter is shown in Fig. 1. The system is composed of a filter of inductance 𝐿, three phases with 8 switches and 6 diodes each, a dc-link (𝑣𝑑𝑐) composed of 4 capacitors — whose voltages are 𝑣𝑐1, 𝑣𝑐2, 𝑣𝑐3and 𝑣𝑐4, respectively –, and a resistor 𝑅connected to the dc-link to emulate the consumption of power. Phase currents and voltages are denoted as 𝑖𝑖 and 𝑣𝑠𝑖 for 𝑖=𝑎, 𝑏, 𝑐, respectively. The output voltage of each phase 𝑖is measured from point 𝑖to dc-link middle point 𝑜3. The switching states of each phase (𝑓𝑖𝑗 ) will be equal to 1 if phase 𝑖is connected to level 𝑗and 0 otherwise, for 𝑖=𝑎, 𝑏, 𝑐 and 𝑗= 1,…,5. For the dc-link capacitor voltage unbalance, variables 𝑣𝑑1, 𝑣𝑑2, 𝑣𝑑3are defined using the following system of equations ⎡⎢⎢⎢⎢⎣ 𝑣𝑑1 𝑣𝑑2 𝑣𝑑3 𝑣𝑑𝑐 ⎤⎥⎥⎥⎥⎦ =⎡⎢⎢⎢⎢⎣ 1 −1 0 0 −1 0 0 1 0 0 1 −1 1 1 1 1 ⎤⎥⎥⎥⎥⎦ ⋅⎡⎢⎢⎢⎢⎣ 𝑣𝑐1 𝑣𝑐2 𝑣𝑐3 𝑣𝑐4 ⎤⎥⎥⎥⎥⎦ .(1) The dynamical model of the system in 𝛼𝛽 can be retrieved by applying the Kirchhoff’s laws (KL) to Fig. 1 and the Clarke transformation, resulting as follows 𝐿𝑑 𝑑𝑡 [𝑖𝛼 𝑖𝛽]=[𝑣𝑠𝛼 𝑣𝑠𝛽 ]−[𝑣𝛼 𝑣𝛽],(2) where parasitic resistors are obviated for the current dynamics and [𝑣𝛼 𝑣𝛽]= (𝑣𝑐1(𝑡) + 𝑣𝑐2(𝑡)) [𝑓𝛼5 𝑓𝛽5]+𝑣𝑐2(𝑡)[𝑓𝛼4 𝑓𝛽4] −𝑣𝑐3(𝑡)[𝑓𝛼2 𝑓𝛽2]− (𝑣𝑐3(𝑡) + 𝑣𝑐4(𝑡)) [𝑓𝛼1 𝑓𝛽1],(3) for the output voltage. System sampling and switching frequencies (for PWM implementation) have the same value 𝑓s. By assuming that its corresponding period (𝑇= 1∕𝑓s) is sufficiently small, the switching function 𝑓𝑖𝑗 can be averaged by using the duty ratio 𝑑𝑖𝑗 instead, which expresses the fraction of the sampling interval in which phase 𝑖=𝑎, 𝑏, 𝑐 is connected to point 𝑜𝑗. With this, the resulting model contains only continuous signals, and the constraints ∑5 𝑗=1 𝑑𝑖𝑗 = 1 for 𝑖=𝑎, 𝑏, 𝑐 must be fulfilled. This averaging stage can be applied to Eq. (3), obtaining the duty ratios 𝑑𝑘𝑗 for 𝑘=𝛼, 𝛽. Note that one degree of freedom is made explicit in the 𝑑𝛼𝛽,𝑗 →𝑑𝑎𝑏𝑐,𝑗 transformation and will be used in the same way as [22] and will be explained later. Assuming that the capacitors are equalized 𝑣𝑐1=𝑣𝑐2=𝑣𝑐3=𝑣𝑐4= 𝑣𝑑𝑐 ∕4, variable 𝑣𝑘can be normalized and averaged as 𝑢𝑘: 𝑢𝑘≐𝑣𝑘 𝑣𝑑𝑐 4 = 2𝑑𝑘5+𝑑𝑘4−𝑑𝑘2− 2𝑑𝑘1. 𝑘 =𝛼, 𝛽. (4) Using 𝑢𝑘for 𝑘=𝛼, 𝛽 as control signals, a standard current controller can be used to compute their values in such a way that the phase currents {𝑖𝛼, 𝑖𝛽}track their references {𝑖𝛼∗, 𝑖𝛽∗}. Once 𝑢𝛼, 𝑢𝛽are known, their transformation to 𝑎𝑏𝑐 leaves open one degree of freedom. This value will be called 𝑥and is limited by the definition of duty ratio, Eq. (4) and the modulation boundaries 𝑢𝑖∈ [−2,2] for 𝑖=𝑎, 𝑏, 𝑐, yielding an upper and lower bound for 𝑥. In summary, ⎡⎢⎢⎣ 𝑢𝑎 𝑢𝑏 𝑢𝑐⎤⎥⎥⎦ =𝑇[𝛼𝛽→𝑎𝑏𝑐][𝑢𝛼 𝑢𝛽]+⎡⎢⎢⎣ 1 1 1⎤⎥⎥⎦ 𝑥(5) 𝑢𝑖=2𝑑𝑖5+𝑑𝑖4−𝑑𝑖2− 2𝑑𝑖1;𝑢𝑖∈ [−2,−1,0,1,2] (6) 5 ∑ 𝑗=1 𝑑𝑖𝑗 = 1 𝑖=𝑎, 𝑏, 𝑐 , (7) where 𝑇[𝛼𝛽→𝑎𝑏𝑐]is the inverse Clark transformation. The optimization problem that will be formulated in Section 3will use this degree of freedom, 𝑥, and it will also consider constraints (6) and (7). The dynamics of 𝑣𝑑1, 𝑣𝑑2, 𝑣𝑑3(1) are obtained from the capacitor dynamics and the definition of duty ratios as 𝐶𝑑𝑣𝑑1 𝑑𝑡 =∑ 𝑖=𝑎,𝑏,𝑐 (−𝑑𝑖4𝑖𝑖)(8) 𝐶𝑑𝑣𝑑2 𝑑𝑡 =∑ 𝑖=𝑎,𝑏,𝑐 (−(𝑑𝑖1+𝑑𝑖5)𝑖𝑖)(9) 𝐶𝑑𝑣𝑑3 𝑑𝑡 =∑ 𝑖=𝑎,𝑏,𝑐 (−𝑑𝑖2𝑖𝑖),(10) where terms 𝑑𝑖𝑗 𝑖𝑖refer to the averaged current of phase 𝑖that goes into node 𝑜𝑗. Note that this formulation relates the duty ratio values with the current control fulfillment (𝑖𝑎𝑏𝑐 →𝑖∗ 𝑎𝑏𝑐) in (6), and with the capacitor balance issue in (8)–(10). 2.2. Control strategy The main blocks of the control scheme used in this paper are shown in Fig. 2. Notice that this work focuses on the modulation block and how it deals with the capacitor voltage problem based on an optimization process and machine learning, as it will be detailed in Sections 3and 4(Fig. 4 shows the proposed real-time implementation of the modulation block). A conventional two-block control scheme based on dc-link voltage and current controllers is used. However, alternative approaches based on averaged modeling, for example, could be used [23–25], as they can provide the modulation block with the required inputs. This fact also illustrates the flexibility of the proposed method. The remainder of this section is devoted to briefly introduce the dc-link and current controller that are later used in simulation and experiments. It is worth mentioning that this is not the aim of the paper and, therefore, they are included briefly for the sake of completeness. In grid-connected power converters, it is common to implement two cascaded controllers: dc-link voltage regulation and current reference tracking [26]. In this way, the dc-link voltage controller defines the references for the current controller. The former outputs the desired active power (𝑝∗) in such a way that the dc-voltage reaches its reference International Journal of Electrical Power and Energy Systems xxx (xxxx) xxx 4 P. Montero-Robina et al. Fig. 2. Control scheme of the proposal. Notice that the paper focuses on the block ‘‘Modulation’’. For blocks ‘‘Dc-link controller’’ and ‘‘Current controller’’ different approaches can be used. at steady-state. To achieve this, a simple PI controller is commonly employed [27]: 𝑝∗=𝑘𝑑𝑐 𝑝(𝑣∗ 𝑑𝑐 2−𝑣2 𝑑𝑐 )+𝑘𝑑𝑐 𝑖∫𝑡 0(𝑣∗ 𝑑𝑐 2−𝑣2 𝑑𝑐 )𝑑𝜏 (11) where 𝑘𝑑𝑐 𝑝and 𝑘𝑑𝑐 𝑖are the control parameters. Once the active power reference is known and the reactive power reference is given externally (𝑞∗), the current references might be extracted as follows: [𝑖∗ 𝛼 𝑖∗ 𝛽]=1 𝑣2 𝑠𝛼 +𝑣2 𝑠𝛽 [𝑣𝑠𝛼 −𝑣𝑠𝛽 𝑣𝑠𝛽 𝑣𝑠𝛼 ][𝑝∗ 𝑞∗].(12) These references input the current controller, where the well-known non-ideal proportional-resonant (PR) controller [28] is used in this paper. The formulation for such controller is 𝐺𝜔𝑟 PR(𝑠) = 𝑘𝑝+2𝐾𝑟𝜔𝑐𝑠 𝑠2+ 2𝜔𝑐𝑠+𝜔2 𝑟 [𝑢𝛼 𝑢𝛽]=4 𝑣𝑑𝑐 (−𝐺𝜔𝑔 PR ([𝑖∗ 𝛼−𝑖𝛼 𝑖∗ 𝛽−𝑖𝛽])+[𝑣𝑠𝛼 𝑣𝑠𝛽 ]),(13) where 𝜔𝑟is the resonant frequency – tuned to be equal to the grid one (𝜔𝑔) –, 𝜔𝑐is the cut-off frequency, and 𝑘𝑝and 𝐾𝑟are the control parameters. Thus, the values of 𝑢𝛼and 𝑢𝛽are obtained and then transformed to 𝑎𝑏𝑐 (5) once variable 𝑥is chosen. Capacitor voltage balance highly depends of this value, and still some degrees of freedom remain as the ones that are present in Space Vector Modulation. This stage is not trivial in five-level converters, above all if voltage balance is required (see, for example [7,8] where this problem is addressed with SVM related methods). This paper presents a different approach based on mixed-integer optimization for the computation of duty ratios and machine learning for the achievement of simple algorithms that are implementable online. In the following, variables 𝜂𝑎, 𝜂𝑏and 𝜂𝑐are used as the corresponding values for 𝑢𝑎,𝑢𝑏and 𝑢𝑐when 𝑥is chosen to be zero in Eq. (5): ⎡⎢⎢⎣ 𝜂𝑎 𝜂𝑏 𝜂𝑐⎤⎥⎥⎦ ≐𝑇[𝛼𝛽→𝑎𝑏𝑐][𝑢𝛼 𝑢𝛽].(14) 3. Modulation as an optimization problem This section is devoted to present the modulation stage (shown in Fig. 2) as an optimization problem. Thus, it begins recalling the optimization procedure described in [12] and implemented in [13] through look-up tables, and several improvements in the formulation are made with respect to them. Therefore, a linear, mixed-integer optimization problem is considered, which obtains the duty ratios 𝑑𝑖𝑗 that accomplish 𝑢𝛼and 𝑢𝛽at the same time that other objectives, such as capacitor voltage balance and reduced number of commutations, are pursued. In contrast to [13], this paper resorts to machine learning to obtain decision trees that are used online to implement the results of the optimization approach. With this, an improvement in the robustness is achieved as it will be shown in Sections 5and 6. 3.1. Optimization problem This section presents the formulation of the linear mixed-integer optimization problem that could be solved at every sampling instant to determine which duty ratios 𝑑𝑖𝑗 for each phase 𝑖=𝑎, 𝑏, 𝑐 and level 𝑗= 1,…,5are chosen to be different from zero, i.e. which levels are used. The following objectives are considered as constrains for the optimization problem [22]: •The sum of the duty ratios for each phase 𝑖has to be 1 (7). •The output of the power controller (𝑢𝛼, 𝑢𝛽)(13) has to be accurately modulated in 𝑎𝑏𝑐 taking into account (4): 𝑢𝑖= 2𝑑𝑖5+𝑑𝑖4−𝑑𝑖2− 2𝑑𝑖1.(15) •The balancing error signals cannot increase: sign(𝑣𝑑𝑝)𝑑𝑣𝑑𝑝 𝑑𝑡 ≤0, 𝑝 = 1,2,3.(16) Considering (8)–(10), these constraints can be related to the duty ratios. Note that strict constraints in the sign of 𝑑𝑣𝑑𝑝 𝑑𝑡 for 𝑝= 1,2,3 might yield an increase in the number of commutations, that is why these constraints are softened to a non-strict inequality. The desired behavior is prioritized by descending order of precedence: 1. Reduce as much as possible the number of commutations in order to reduce the switching losses. For this, the lowest amount of non-zero 𝑑𝑖𝑗 should be prioritized. 2. Large jumps within a phase must take place as little as possible. Large jumps are the sequential use of non-consecutive levels, and they can be expressed mathematically for a generic phase 𝑖as: 𝑑𝑖𝑗1≠0; 𝑑𝑖𝑗2= 0; 𝑑𝑖𝑗3≠0when 𝑗1< 𝑗2< 𝑗3 for {𝑗1, 𝑗2, 𝑗3} ∈ {1,2,3,4,5}.(17) Large jumps increase the current ripple and compromise the voltage limits of the devices, and thus they should be penalized. 3. Since the previous objectives are expressed in the cost function as integer numbers, it is likely that several points achieve the same score. In these cases, the points that fulfill the strict inequality in (8)–(10) should be prioritized over others, which is a point not considered in [12,13]. Furthermore, the signal error derivative magnitude may also be taken into account for the same purpose. These considerations are gathered in a new term 2 of the cost function as is shown in Eq. (18). From [13] and adding term 2, the cost function results in 𝑓cost =∑ 𝑖=𝑎,𝑏,𝑐 (5 ∑ 𝑗=1 𝑠𝑖𝑗 + 6 ∑ 𝑚=1 𝑝𝑖𝑚𝑞𝑖𝑚) ⏟⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏟⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏟ term 1 + 3 ∑ 𝑝=1 (𝛼ℎ𝑝−𝛼1sign(𝑣𝑑𝑝)𝑑𝑣𝑑𝑝 𝑑𝑡 ) ⏟⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏟⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏟ term 2 . (18) A brief explanation of these variables and their associated constraints are given in the following. •Integer variables 𝑠𝑖𝑗 ≥0for 𝑖=𝑎, 𝑏, 𝑐 and 𝑗= 1,…,5are greater than zero in the cases when level 𝑗in phase 𝑖is being used for the current solution, i.e. if duty ratio 𝑑𝑖𝑗 ≠0, and equal to zero in the opposite case. To fulfill such purpose, the following linear constraint is defined: 𝑠𝑖𝑗 −𝑑𝑖𝑗 ≥0for 𝑖=𝑎, 𝑏, 𝑐;𝑗= 1,…,5.(19) International Journal of Electrical Power and Energy Systems xxx (xxxx) xxx 5 P. Montero-Robina et al. •Integer variables 𝑝𝑖𝑚 ∈ {0,1} and 𝑞𝑖𝑚 ∈ {1,2,3} are used to penalize large jumps in the solution candidate considered for each phase 𝑖. Large jumps are classified using index 𝑚= 1,…,6for the 6 types of large jumps: levels 1–3, 2–4, 3–5, 1–4, 2–5, and 1–5. Auxiliary variable 𝑝𝑖𝑚 is introduced in order to register whether the large jumps are taking place (𝑝𝑖𝑚 = 1) or not (𝑝𝑖𝑚 = 0). A cost 𝑞𝑖𝑚 ∈ {1,2,3} is used in (18) that expresses the amount of nonused intermediate levels. For example, large jump 1–4 has two intermediate levels and two non-zero duty ratios – 𝑠𝑖1= 1, 𝑠𝑖4= 1 – then 𝑞𝑖4= 2. Besides, the detection stage, i.e. determination of 𝑝𝑖𝑚, for phase 𝑖must search for the occurrence of 𝑑𝑖𝑗 ≠0for 𝑗=𝑗𝑚1and 𝑗=𝑗𝑚2and 𝑑𝑖𝑗 = 0 for 𝑗𝑚1< 𝑗 < 𝑗𝑚2. This can be considered by means of the following constraints. 𝑠𝑖𝑗𝑚1+𝑠𝑖𝑗𝑚2−𝑟𝑖𝑚 ≤1; 0 ≤𝑟𝑖𝑚 ≤1(20) 𝑟𝑖𝑚 −𝑝𝑖𝑚 − 𝑗𝑚2−1 ∑ 𝑗=𝑗𝑚1+1 𝑠𝑖𝑗 ≤0; 0 ≤𝑝𝑖𝑚 ≤1,(21) where 𝑟𝑖𝑚 = 1 if the outer levels of the large jump candidate are used (𝑑𝑗𝑚1≠0and 𝑑𝑗𝑚2≠0). •Integer variables ℎ𝑝≥0for 𝑝= 1,2,3indicate whether 𝑑𝑣𝑑𝑝 𝑑𝑡 fulfills the strict inequality 𝑑𝑣𝑑𝑝 𝑑𝑡 sign(𝑣𝑑𝑝)<0 (ℎ𝑝≤0) or not (ℎ𝑝>0). Therefore, the following constraint is added: ℎ𝑝−𝑑𝑣𝑑𝑝 𝑑𝑡 sign(𝑣𝑑𝑝)≥0,for 𝑝= 1,2,3 (22) •Weighting factors 𝛼1and 𝛼satisfy 𝛼1≪ 𝛼 ≪ 1in such a way that term 2 will only be relevant for candidates with the same value in term 1, prioritizing, firstly, the fulfillment of a larger amount of strict inequalities, and secondly, the voltage balance speed. In summary, a linear, mixed-integer optimization problem is formulated. As it can be seen, such a problem has to be solved every sampling time, which may not be feasible for typical digital signal processors. Therefore, it is proposed to solve the problem offline and resort to Machine Learning to come up with a reduced procedure with an easy and fast implementation, as it will be exposed in Section 4. 3.2. Solution of the optimization problem The optimization problem has to be solved each sampling period, resulting in the duty ratio values. However, the previous problem can hardly be solved at usual switching frequencies (around 5–10 kHz). For this, [12] proposes to solve it offline for 𝑁samples over a grid period under nominal operating conditions, recalling these results during online operation. Given the fact that there are 8 combinations of sign(𝑣𝑑𝑝), eight tables of results are obtained. Paper [13] accomplishes such implementation by resorting to look-up tables that used the angle of 𝑢𝛼𝛽 vector as index variable. Although this implementation was validated experimentally even with slight variations of the operating point, the LUT results were designed for specific operating conditions. Consequently, the same LUT will not necessarily work under different operating conditions, as will be shown later in experiments. This paper proposes to use the optimization results to come up with a solution that works in a wider range of operating points. For this, and contrary to [13], in this paper several operating points are considered, and the results of the optimization problem are stored in datasets. It is shown in [12,13] that the solutions for every switching instant usually have the following characteristics: •One phase (𝑖fix) fixed to one level (𝑗fix), i.e. it has one duty ratio equal to 1, and the remaining ones equal to zero. 𝑑𝑖fix𝑗fix = 1; 𝑑𝑖fix𝑗= 0 ∀𝑗≠𝑗fix ∈ {1,2,3,4,5} •Two phases (𝑖1and 𝑖2) that commute between two levels only (𝑗11–𝑗12 and 𝑗21–𝑗22 respectively), i.e. they have two duty ratios different from zero, and the remaining ones equal to zero. 𝑑𝑖1𝑗11 ≠0; 𝑑𝑖1𝑗12 ≠0; 𝑑𝑖1𝑗= 0 ∀𝑗≠𝑗11, 𝑗12 ∈ {1,2,3,4,5} 𝑑𝑖2𝑗21 ≠0; 𝑑𝑖2𝑗22 ≠0; 𝑑𝑖2𝑗= 0 ∀𝑗≠𝑗21, 𝑗22 ∈ {1,2,3,4,5} The idea is to use this knowledge about the solutions to the optimization problem to propose a codification procedure for the inputs and outputs of the CARTs. Thus, raw input and output data are transformed into qualitative integer variables before feeding the CART algorithm, as will be shown later. The data are arranged into eight datasets, one for each sign(𝑣𝑑𝑝)combination, obtained by simulating several operating conditions, and used to train a CART algorithm with the coded result being the output. Section 4will provide more information on the coding of the inputs and results, as well as the training process. The resulting CARTs can be easily implemented online, and given the generality of the solutions of the CART learning algorithm and the codification of input and output data, a wide range of operating points can be covered, as will be shown in the simulation and experimental sections. 4. CART based modulation The aim of this section is to depict how the previous optimal modulation can be implemented online without requiring to solve the optimization problem at every sampling time. For this, CARTs are trained with a wide variety of system states and the corresponding optimal modulation policies (solutions of the optimization problems as shown in Section 3.2). The resulting CARTs are implemented for online operation. Note that the optimization problem is solved for every combination of signs of 𝑣𝑑1, 𝑣𝑑2, 𝑣𝑑3as this factor imposes a different constraint on the optimization problem. Therefore, eight CARTs have to be obtained. For this objective, several issues need to be tackled and elaborated in the following sections: (1) Codification of system state and resultant modulation policy into integer variables as CART inputs and outputs, respectively; (2) CART training; (3) Robust CART implementation for online modulation. 4.1. CART inputs and outputs codification This section presents a codification procedure for the system state as well as modulation policies into integer variables. This codification procedure will later be used for both the training and the online implementation. As a result, each CART produces a coded output from any possible input data. For this, instead of using raw data from the continuous variables 𝑖𝑎,𝑖𝑏,𝑖𝑐,𝑢𝛼and 𝑢𝛽, the input data should represent qualitative information of the system variables through discretized integer variables, improving CART training and achieving generality at the same time. Therefore, it is critical to select how to compute these integer variables (from 𝑖𝑎,𝑖𝑏,𝑖𝑐,𝑢𝛼and 𝑢𝛽) and how to code the output. 4.1.1. CART inputs In the following, the computation of the 22 categorized integer variables that are later used as inputs in the CART, either in the training and online implementation, is presented. For this, qualitative information is extracted from the optimization results and this information is fed into the CART generation algorithm. The qualitative information for each sampling time was chosen carefully using expert knowledge and the analysis of the optimization results for several test cases, such as: •The sign of the currents 𝑖𝑎, 𝑖𝑏, 𝑖𝑐:−1 for negative values, and 1 for positive values. (3 variables) •An integer number for each phase 𝑖(level𝑖) that indicates between which two levels the associated voltage reference 𝜂𝑖(14) is found. The code for this number is shown in Table 1. (3 variables) International Journal of Electrical Power and Energy Systems xxx (xxxx) xxx 6 P. Montero-Robina et al. Fig. 3. Flowchart of carried out steps to obtain the eight decision trees based on the optimization problem. Table 1 Integer number to indicate associated levels for 𝜂𝑖. level𝑖𝜂𝑖level𝑖𝜂𝑖 1 [−2,-1] 3 (0,1] 2 (−1,0] 4 (1,2) Table 2 Integer number to indicate current order. 𝑟Current order 𝑟Current order 1𝑖𝑎≥𝑖𝑏≥𝑖𝑐4𝑖𝑐≥𝑖𝑏≥𝑖𝑎 2𝑖𝑎≥𝑖𝑐≥𝑖𝑏5𝑖𝑏≥𝑖𝑐≥𝑖𝑎 3𝑖𝑐≥𝑖𝑎≥𝑖𝑏6𝑖𝑏≥𝑖𝑎≥𝑖𝑐 •A code (𝑟) that indicates the order relation among 𝑖𝑎, 𝑖𝑏and 𝑖𝑐. This code is shown in Table 2. For example, when 𝑖𝑎≥𝑖𝑏≥𝑖𝑐this code is equal to 1, when 𝑖𝑎≥𝑖𝑐≥𝑖𝑏the code is equal to 2, and so on. (1 variable) •Variables 𝑦𝑖𝑗 for 𝑖=𝑎, 𝑏, 𝑐 and 𝑗= 1,…,5are set to 1 when there exists a value of 𝑥that satisfies 𝑥min ≤𝑥≤𝑥max such that the corresponding value of 𝜂𝑖+𝑥is equal to 𝑗. This means that for the current sample data it is possible to consider a value of the homopolar component such that 𝑢𝑖∈ [−2,2] is equal to level 𝑗, as it is shown in (5)–(7). Therefore, 𝑦𝑖𝑗 = 1 if 𝑥min ≤𝑗−3−𝜂𝑖≤𝑥max, and 𝑦𝑖𝑗 = 0 otherwise. (15 variables) The previous 22 variables are computed for every sample from 𝑖𝑎, 𝑖𝑏,𝑖𝑐,𝑢𝛼and 𝑢𝛽, and will be used as representative of the current state of the system for the CART. 4.1.2. CART outputs Given one sample of the system, the optimization problem can be solved. It is assumed that the optimization problem result dictates one phase to be fixed at one level, while the other two phases commute between two different levels. Therefore, a code that captures this information is defined by using three numbers 𝑎1, 𝑎2, 𝑎3: •The first number 𝑎1indicates the pair of values 𝑖and 𝑗such that 𝑑𝑖𝑗 = 1, i.e. which phase 𝑖is fixed at which level 𝑗. Table 3 shows this codification (15 possible values) Table 3 Integer number 𝑎1to indicate which 𝑑𝑖𝑗 equals one. 𝑎1(𝑖, 𝑗)𝑎1(𝑖, 𝑗)𝑎1(𝑖, 𝑗)𝑎1(𝑖, 𝑗)𝑎1(𝑖, 𝑗) 1 (𝑎,1) 2 (𝑎,2) 3 (𝑎,3) 4 (𝑎,4) 5 (𝑎,5) 6 (𝑏,1) 7 (𝑏,2) 8 (𝑏,3) 9 (𝑏,4) 10 (𝑏,5) 11 (𝑐,1) 12 (𝑐,2) 13 (𝑐,3) 14 (𝑐,4) 15 (𝑐,5) Table 4 Integer number 𝑎2/𝑎3to indicate pair of used levels. Code Levels Code Levels Code Levels 11−2 51−3 81−4 22−3 62−4 92−5 33−4 73−5 10 1−5 44−5 •Numbers 𝑎2and 𝑎3represent the pair of levels that the remaining phases use. The correspondence of 𝑎2and 𝑎3with the phases follows alphabetical order: for example, if the phase used for code 𝑎1is phase 𝑏, code 𝑎2corresponds to phase 𝑎and code 𝑎3to phase 𝑐. The pair of levels are coded by enumeration as shown in Table 4. (10 possible values each) These values can be combined into a single variable with 15 × 10 × 10 = 1500 possible values. This variable is used as the output for the CART algorithm and it is coded as follows Output code ∶ (𝑎1− 1) ⋅102+ (𝑎2− 1) ⋅10 + (𝑎3− 1).(23) 4.2. CART training In this section, the CART inputs and outputs, as described in Section 4.1, are gathered into datasets to perform the training of the CARTs. This information comes from offline simulations where 𝑁samples over a grid period at steady state conditions for several operating points are obtained to feed the optimization problem. Both the system state and the optimization result for every sample are stored to form the training dataset. This training operation has to be computed for every possible combination of signs of 𝑣𝑑1, 𝑣𝑑2, 𝑣𝑑3, obtaining as a result 8 International Journal of Electrical Power and Energy Systems xxx (xxxx) xxx 7 P. Montero-Robina et al. Table 5 CART training parameters. Parameter Value Parameter Value Samples per operation point and grid period 𝑁100 Optimization weighting factor 𝛼10.01 Optimization weighting factor 𝛼0.001 CART complexity parameter 𝑐𝑝 0.002 Training dataset coverage >85% Max. number of levels 11 Number of operating points (Table 6) 6 Integer input variables 22 Table 6 Operations points considered for the training data set. No. 𝑣𝑑𝑐 (V) 𝑝(kW) 𝑞(kVA) 1 800 10 0 2 800 0 10 3 800 0 −10 4 700 10 0 5 700 0 10 6 700 0 −10 decision trees. Fig. 3 shows the summary of the training stage for one operating point. In order to extend the operability of this approach, additional operating points are considered, simulated and added to the corresponding dataset. The training parameters and information on the resulting trees are included in Table 5, and the considered operating points are shown in Table 6. The trees are generated using the recursive partitioning and regression trees technique from the rpart library for R language. The arguments of this function are: the input–output variables; the classification method set as ‘‘class’’; the way the decisions are considered, in this case, through the complexity parameter 𝑐𝑝, which determines that a split is not carried out if it does not decrease the overall lack of coverage by the 𝑐𝑝 value; and a vector with the cost values. The latter is a vector that contains one cost value for each input such that the inputs with increased cost would appear less frequently in the decision tree. The 𝑐𝑝 value is tuned in such a way that a minimum of 85% of coverage of the training data set is obtained. The input cost values are justified and selected as: •The sign of the currents and their order code (𝑟) keep the same value for a large number of samples within one grid period, and thus they should be consulted less frequently: Cost value = 5 •Variables level𝑖are the next considered as they change more frequently: Cost value = 2.5 •Variables 𝑦𝑖𝑗 are the easiest to classify due to their binary nature, while they also provide useful information about the feasible values of 𝑥: Cost value = 1. In summary, there exist 22 variables to be used as input parameters and one coded integer result whose value could range from 0 to 1500. An example of a generated tree is depicted in Fig. A.14 in Appendix. The maximum number of levels for all trees is 11, and they are balanced with a similar percentage of coverage. 4.3. Implementation for online modulation The computed decision trees can be easily implemented just by means of simple nested ‘‘if...else’’ statements, making it possible to be evaluated in real time in order to perform the modulation block within the control loop shown in Fig. 2. Thus, Fig. 4 shows the detailed real time implementation scheme for the modulation block, which consists of the following steps: 4.3.1. CART selection During online operation, the decision tree that corresponds to the actual combination of sign(𝑣𝑑𝑝),𝑝= 1,…,3, (see Eq. (1)) is selected, as shown in Fig. 4. 4.3.2. Computing CART inputs and evaluation This CART is fed with the input data parameters computed from the actual currents 𝑖𝑎𝑏𝑐 and voltage commands 𝑢𝛼𝛽 (see Section 4.1.1). With these inputs, the ‘‘if...else’’ statements of the CART can be evaluated and, thus, the corresponding output code is obtained. (see Section 4.1.2). 4.3.3. Decodification In order to obtain the values of the duty ratios 𝑑𝑖𝑗 from the output code, the following procedure is considered, I. Variables 𝑎1, 𝑎2and 𝑎3are obtained from the output code. To depict an example, let us consider an output code of 574 from Fig. A.14. Variables 𝑎1, 𝑎2, 𝑎3are extracted from the output code by means of simple integer division: 𝑎1=int(code∕102) + 1 = 6 (24) 𝑎2=int((code − (𝑎1− 1) ⋅102)∕10) + 1 = 8 (25) 𝑎3=int((code − (𝑎1− 1) ⋅102− (𝑎2− 1) ⋅10)) + 1 = 5 (26) II. Using (5)–(7) with 𝑢𝛼, 𝑢𝛽obtained from (13), and the information provided by 𝑎1, the value of 𝑥is obtained. III. Knowing 𝑥and the information provided by 𝑎2and 𝑎3, the remaining 𝑑𝑖𝑗 are computed according to (5)–(7). 4.3.4. Duty cycle computation To guarantee a robust implementation of the desired voltage vector, for example, when the 𝑢𝛼, 𝑢𝛽values cannot be represented using the levels indicated by 𝑎1,𝑎2and 𝑎3, we propose the following procedure: I. The result is decoded and the levels to be used for each phase are obtained according to 𝑎1, 𝑎2and 𝑎3: fixed phase 𝑖fix at level 𝑙fix; phases 𝑖1and 𝑖2fixed at 𝑗11, 𝑗12 and 𝑗21, 𝑗22, respectively. II. It is checked if the indicated fixed phase (𝑖fix) can be fixed at level (𝑙fix), that is: 𝑥min ≤𝑙fix −3−𝜂𝑖fix ⏟⏞⏞⏞⏞⏞⏟⏞⏞⏞⏞⏞⏟ 𝑥fix ≤𝑥max.(27) If so, then set 𝑥=𝑥fix, otherwise 𝑥is saturated to the closest value 𝑥min or 𝑥max such that one phase is still fixed at one level. III. A similar procedure is carried out for phases 𝑖1and 𝑖2. For each of them, they should be modulated using the indicated levels taking into account the previous 𝑥value. This is equal to check if: 𝑗11 ≤𝜂𝑖1+3+𝑥≤𝑗12 (28) 𝑗21 ≤𝜂𝑖2+3+𝑥≤𝑗22.(29) In the case this check is not fulfilled, the used levels are changed to the nearest levels. That is, the closest levels above and below of (𝜂𝑖+ 3 + 𝑥). Once the two levels for each phase, for which the corresponding duty cycles are not zero, the computation of them is obvious using trivial and well-known weighting formulae. Because of this procedure, the implemented duty ratios might not be the optimal values according to the formulated problem, which is the reason why this work is entitled pseudo-optimal modulation. Additional sources of error that could make the implemented result to diverge from the optimal one are: International Journal of Electrical Power and Energy Systems xxx (xxxx) xxx 8 P. Montero-Robina et al. Fig. 4. Implementation scheme for real time modulation block implementation with robust modulation of 𝑢𝛼, 𝑢𝛽. Table 7 Converter parameters. Parameter Value Parameter Value Grid frequency 𝑓50 Hz Sampling frequency 𝑓𝑠10 kHz Grid voltage 𝑣𝑠𝑎𝑏𝑐 230 VRMS Switching frequency 𝑓𝑠𝑤 10 kHz Inductance 𝐿2 mH Prop. term PR controller 𝑘𝑝5 Capacitance 𝐶3300 μF Resonant term PR controller 𝐾𝑟50 dc-link load 𝑅[60,∞] Ω Prop. term dc-link controller 𝑘𝑑𝑐 𝑝0.05 dc-link voltage reference 𝑣∗ 𝑑𝑐 [700,800] V Integral term dc-link controller 𝑘𝑑𝑐 𝑖1 Low-pass cut-off frequency (PR) 𝜔𝑐2𝜋5rad/s Resonant frequency (PR) 𝜔𝑟2𝜋50 rad/s Table 8 THD values of the currents (Fig. 5(a)) and number of commutations over a grid period (Fig. 5(b)). Approach THD (%) # Commt CART 4.6 550 LUT 4.6 645 SVBA [7] 7.01 935 FCS-MPC [11] 10 kHz 25 kHz 50 kHz 13.42 5.10 2.54 210 540 1100 OICM [10] 5.40 1600 MICM [10] 4.2 1333 I. The measured variables, as well as the values of 𝑢𝛼and 𝑢𝛽, may not correspond exactly to any of the training data sets, and therefore the result is inferred from the training datasets. II. The CART algorithm has a coverage error and not all cases used for the training are correctly matched in the output given by the decision trees. III. There were some samples that did not fulfill the generic rule of one phase fixed to one level and the others using only two levels, thus those few cases are neglected with the current approach — less than 3% in any of the solved optimization problems. Despite these sources of errors, it will be shown in the following sections that the results are satisfactory. Overall, the implementation that has been used in this paper is depicted in Figs. 2 and 4, where it can be seen that the contribution lies in the modulation and voltage balancing stage. In other words, the only requirement is to give the phase currents 𝑖𝑎𝑏𝑐 and the voltage commands 𝑢𝛼𝛽 to the pre-processing stage (apart from the signs of 𝑣𝑑1, 𝑣𝑑2and 𝑣𝑑3to select the appropriate decision tree), which can be derived from any control technique that relies on voltage vector modulation 4.4. Summary of CART based modulation and remarks In summary for this approach, for each of the 8 possible combinations of 𝑣𝑑1, 𝑣𝑑2, 𝑣𝑑3, the following steps were carried out: 1. The optimization problem is solved offline under fixed operating conditions. Such optimization would determine which levels to use for every sampled instant, obtaining a table for those fixed operating conditions. Several operating conditions can be gathered in a database. (Section 4.1.2) 2. For each sampling instant in the database, the 22 integer CART inputs are obtained (from 𝑖𝑎,𝑖𝑏,𝑖𝑐,𝑢𝛼and 𝑢𝛽), and the results, i.e. which levels should be used in the modulation, are codified. (Section 4.1) 3. The CART is trained offline with the previous information. As a result, a decision tree (nested if-else) is obtained. Such a tree yields a codified output when a string of inputs is given. (Section 4.2) Once all 8 offline decision trees have been computed, the online implementation (Section 4.3) consists of only the execution of the decision tree considering the inputs obtained from the measurements, as shown in Fig. 4. Remark 1. This approach proposes a modulation stage to solve the balancing capacitor voltages, but at the same time, the current control is always fulfilled and given maximum priority. Remark 2. This approach is based on the model of the five-level DCC, as the optimization is based on the capacitor voltages balancing dynamics. However, other multilevel converters with different dynamics can be considered as long as the optimization problem is modified accordingly. Furthermore, given that the desired output of the current control is always prioritized and that the balancing is executed to modify the sign of the derivatives of 𝑣𝑑1, 𝑣𝑑2, 𝑣𝑑3, without paying attention to their magnitude, this approach fulfills the control objectives regardless of the International Journal of Electrical Power and Energy Systems xxx (xxxx) xxx 9 P. Montero-Robina et al. Fig. 5. Simulation: Steady-state performance for the proposed approach (top), the LUT-based (second row), the SVBA (third row), the FCS-MPC for three different sampling and switching rates (fourth row), and the OICM and MICM (bottom). 𝑣𝑑𝑐 = 800 V,𝑅= 60 Ω,𝑞𝑟= 0 kV A. Fig. 6. Simulation: Capacitor voltages evolution starting from an unbalanced situation 𝑣𝑑1= −40, 𝑣𝑑2= 60, 𝑣𝑑3= −5 for all the considered approaches under different tests whose power references are shown at the top of the figure. 𝑣𝑑𝑐 = 700 V. system parameters, such as capacitance or phase inductance (within the boundaries of active and reactive power and modulation index). 5. Simulation results Before testing the proposed technique in a real environment, some in-depth simulations have been performed in MATLAB-Simulink®. The operation points of the offline simulations considered to generate the training datasets are the same shown in Table 6. For a proper comparison, 5 different modulation methods, with balancing capabilities, for 5-level DCC converters are considered apart from the proposed one (CART): •A space-vector based algorithm [7] (SVBA). •Two integrated control and modulation methods proposed in [10] (OICM and MICM). •A model-predictive control based on finite control set (FCSMPC) [11]. •The original proposal for the optimization problem implemented through a look-up table [13] (LUT). Among these six controllers, LUT, CART and FCS-MPC are based on optimal formulations, whereas SVBA, OICM and MICM are based on conventional approaches that uses averaged models. The LUT method is an alternative procedure to implement the results of the offline optimization based on interpolating them from a look-up table. The SVBA combines the small and large switching vectors in the space vector hexagon in such a way that balancing capabilities are achieved for any operating point. The FCS-MPC is based on selecting every sampling interval the switching state that yields the lower value of a weighted cost function that covers current reference tracking and voltage balance while minimizing the number of commutations. The cost-function weighting values of the FCS-MPC have been selected in such a way that the balancing error at steady state is lower than 10 V. Moreover, the FCS-MPC approach has been evaluated under three sampling frequencies: 10, 25 and 50 kHz. Lastly, OICM and MICM define a control law to compute the duty ratios for each phase and level in the control stage.