AI-Assisted Sigma-Delta Converters. Application to Cognitive Radio

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – II: EXPRESS BRIEFS 1 AI-Assisted Sigma-Delta Converters – Application to Cognitive Radio Jos´ e M. de la Rosa, Fellow, IEEE Abstract—This brief discusses the use of Artificial Intelligence (AI) to manage the operation and improve the performance of Analog-to-Digital Converters (ADCs) based on Sigma-Delta Modulators (Σ∆Ms). The reconfigurable nature of Σ∆Ms can be enhanced by AI algorithms in order to adapt the specifications of ADCs to diverse input signal requirements, environment interferences, noise levels, battery status, etc. A high degree of programmability is required, which demands for scaling-friendly, mostly-digital analog circuit techniques as well as suitable topologies of Artificial Neural Networks (ANNs) to implement the AI engine. Moreover, the practical implementation of AI-assisted Σ∆Ms requires to adopt diverse design strategies – from the Σ∆M architecture itself to AI modules and circuit building blocks – which are overviewed in this brief. As an application and case study, an ANN-assisted ADC for Software-Defined Radio (SDR) and Cognitive Radio (CR) is considered. The system is based on the use of a widely-tunable Band-Pass (BP)-Σ∆M, and an ANN is used to predict the occupancy of frequency bands and modify the notch frequency of the BP-Σ∆M accordingly. Index Terms—Analog-to-digital conversion, sigma-delta modulation, artificial intelligence, neural networks, cognitive radio. I. INTRODUCTION ARTIFICIAL Intelligence (AI) is one of the key technology players of the so-called digital transformation, which is shaping many different aspects of our daily lives [1], [2]. The use of AI algorithms is becoming more and more intensive in countless application scenarios which include, among others, multimedia pattern classification and recognition, biometric identification, robotics, computation, communications, etc. [3]–[7]. In most cases, AI modules are implemented in the form of Artificial Neural Networks (ANNs). Essentially, an ANN is a computing system formed by the interconnection of layers of artificial neurons, which are inspired by the way biological neurons set connections among them by means of synapses [8]. ANN-based AI systems, such as Machine Learning (ML) and Deep Learning (DL), are fuelled by an increasingly computing power provided by both cloud and edge computing, as well as the giant volumes of data collected and provided by Internet-of-Things (IoT) devices [9], [10]. This way, the combination of big data and AI is used nowadays to solve a number of automatization and optimization problems [7], [11]. Manuscript received January 24, 2022. This work was supported in part by Grant PID2019-103876RB-I00, funded by MCIN/AEI/10.13039/501100011033, by the European Union ”ESF Investing in your future”, and by ”Junta de Andaluc´ ıa” under grants US-1260118 and P20-00599. Jos´ e M. de la Rosa is with the Institute of Microelectronics of Seville, IMSE-CNM (CSIC/University of Seville), C/ Am´ erico Vespuccio 28, 41092 Sevilla, SPAIN, e-mail: [email protected]. Moreover, technology downscaling is allowing the integration of more and more systems into a single chip, with the subsequent benefits in terms of increased performance of information storage and management, together with communication and computation facilities, located in end-devices such as mobile phones and IoT nodes [12], [13]. Embedding AI modules in Systems-on-Chip (SoC) is becoming a commonplace in mobile terminals, where ML/DL engines are used for some specific tasks such as face or fingerprint recognition [7]. Moreover, ANN-based algorithms are also being applied to improve the performance metrics of analog circuits by means of linearization or calibration techniques [14]–[20]. These AI-empowered systems benefit from digital signal processing in terms of programmability, scalability and robustness against technology process and environment variations. Thus, the increasingly number of digital-driven applications and systems is moving the analog/digital interfaces closer and closer to the point where the information is either collected or transmitted, so that most part of the hardware is digital, and hence, easier to program via software. The need of earlier digitization makes the Analog-to-Digital Converter (ADC) one of the key components in many SoCs. The use of ML/DL algorithms can be applied to improve the performance metrics of ADCs [21], so that their main specifications such as the effective resolution and the sampling rate, can be dynamically adapted and optimized to diverse signal requirements, environment conditions, power/battery status, etc. AI algorithms can be also applied as optimization engines to automate the synthesis and design procedure of ADCs [22]. The state of the art on ADCs is mostly dominated by three architectures: Pipeline, Successive Approximation Register (SAR) and Sigma-Delta Modulators (Σ∆Ms) [23]–[27]. These techniques – or a combination of them – cover a vast range of applications: from biomedical devices, sensors, instrumentation to wideband communications. In terms of energy, SAR ADCs are more efficient in applications with resolutions below medium resolution (11−12 bit), while Σ∆M ADCs consume less energy if higher resolutions are needed. However, the efficient implementation of AI-managed ADCs demands for new generations of A/D interfaces which will be able to include strategies at both system and circuit level, and increase the degree of programmability and robustness to make them suited to be controlled by AI modules. Examples of these ADCs include hybrid SAR/Σ∆M/Pipeline [28], [29] or Noise- Shaping (band-pass) SAR ADCs [30], among others. At circuit level, some scaling-friendly/mostly-digital techniques such as time/frequency-based quantization [31], [32] or digital-assisted analog circuits [33], [34], are among the most promising candidates to implement programmable AI-managed ADCs, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – II: EXPRESS BRIEFS 2 since they are more suitable to embed ANN-based algorithms to enhance their performance. The main goal of this tutorial brief is to present a survey of some circuits and systems techniques and design methods intended for AI-managed Σ∆M ADCs – going from systemlevel models, architectures and algorithms to circuit-level implementation. As a case study, the use of AI-managed ADCs for Cognitive-Radio (CR) digitizers is considered as one of the key technology enablers to implement efficient hand-held terminals and IoT nodes. The rest of this article is organized as follows. Section II explains the concept behind AI-empowered Σ∆Ms, revisiting their main fundamentals. Section III discusses the use of ANNs as optimization engine for the automated synthesis of Σ∆Ms. Section IV highlights some programmable and mostly-digital circuits suited for AI- assisted Σ∆Ms. Finally, Section V shows a case study, and conclusions are drawn in Section VI. II. AI-EMPOWERED Σ∆MS: THE CONCEPT Fig. 1(a) shows a conceptual block diagram of an AI- managed Σ∆ ADC, where the operation of the Σ∆M is assisted by an ANN. In order for this system to work properly, the ANN should be previously trained to optimize the performance of the Σ∆M in terms of its main specifications, i.e. Signal-to-Noise Ratio (SNR), Dynamic Range (DR), Total Harmonic Distortion (THD), etc. These Σ∆M performance metrics are used as input variables for the ANN and its outputs are the design parameters that determine the maximum performance of Σ∆M in practice, i.e. the building-block electrical requirements such as: amplifier finite DC gain, Gain Bandwidth (GB), Slew-Rate (SR), Output Swing (OS), etc. The nonideal errors associated to Σ∆M building-block metrics are grouped into an error vector, denoted as ¯, which degrades in practice the Σ∆M loop-filter transfer function, H(f, ¯), and consequently the noise-shaping of the modulator. Assuming a linear additive white noise model with gain kq for the B-bit quantizer in Fig. 1(a), the Z-transform of the Σ∆M output, y, can be expressed as: Y(z, ¯) = STF(z, ¯)X(z) + NTF(z, ¯)E(z)(1) where X(z)is the Z-transform of the input signal, E(z)is the Z-transform of the quantization error, and STF and NTF stand for the signal- and noise-transfer functions, given by: STF(z, ¯) = kqH(z, ¯) 1 + kqH(z, ¯),NTF(z, ¯) = 1 1 + kqH(z, ¯)(2) Considering an Lth-order loop filter, it can be shown that the DR of a Σ∆M can be approximately given by [26]: DR ≈6.02 ·B+ 1.76dB + 10 log10[(2L+ 1) ·OSR(2L+1)/π2L] −∆DR(OSR, L, B, ¯)|dB (3) where OSR ≡fs/(2 ·Bw), stands for the oversampling ratio, fsis the sampling frequency and Bwis the signal bandwidth. The first term of Eq. (3) defines the Effective Number Of Bits (ENOB) of a Nyquist-rate B-bit ADC. As known, Σ∆Ms B-bit ADC x(t)y(n) H(f,¯✏) QuantizerLoop Filter Decimator OSR DSP / FPGA B-bit DAC {SNR, DR, THD,…} ¯✏±¯✏ Trained ANN (a) opt.( ) ¯✏ ADC ⌃ {SNR, DR, THD,…} x(t) ¯✏ (b) Training Fig. 1. AI-assisted Σ∆Ms: (a) Conceptual diagram, (b) ANN training. increase ENOB with OSR by approximately 3·(2L+ 1) dB/octave – second term in (3) – although this enhancement is degraded by the effect of circuit errors – conceptually formulated as ∆DR in (3). The three key parameters, namely OSR, Land B, define the system-level performance of Σ∆Ms, and can be combined in many ways, giving rise to a diverse topologies of Σ∆Ms – single-loop or cascade; Low-Pass (LP) or Band-Pass (BP); single-bit or multi-bit; Continuous-Time (CT) or Switched-Capacitor (SC) — in order to achieve the maximum DR [35], [36]. The idea behind an AI-empowered Σ∆M consists of using an ANN to minimize the DR degradation, ∆DR, caused by circuit nonidealities, ¯. To this end, an ANN can be trained to achieve the maximum performance for a given Σ∆M architecture. The training process is conceptually depicted in Fig. 1(b). During the design phase of the Σ∆M, training data is generated from simulated Σ∆M output metrics, i.e. SNR, THD, NTF, STF, etc. within the multi-dimensional design space formed by a number of design points defined by the combinations of design parameters inset ¯. This way, the Σ∆M performance metrics (SNR, THD, etc), play the role of input variables of the ANN while ¯are the ANN outputs. This way, the learning process consists of mapping such input data, i.e. the Σ∆M specifications, onto the output data, i.e. the design parameters, ¯, that optimize the performance of the Σ∆M. Once the ANN is trained, it can be used to control the operation of the Σ∆M by modifying its building-block design parameters as depicted in Fig. 1(a). Thus, measured SNR, DR, THD, etc. are provided to the trained ANN, which generates a new set of design parameters, denoted as ∆¯, that minimizes ∆DR. This approach – successfully implemented as calibration scheme to linearize CT-Σ∆Ms [6] – can be extended to control and optimize the performance of Σ∆Ms. III. ANN-ASSISTED SYNTHESIS OF Σ∆MS In addition to be embedded in Σ∆M circuits to enhance their performance after being designed, ANNs can be used during the design phase of Σ∆Ms. In this case, the ANN plays the role of the optimization engine which is combined with a simulator to automate the synthesis of Σ∆Ms. Indeed, ANNs IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – II: EXPRESS BRIEFS 3 have been already applied as part of the design methodology for the sizing of analog and mixed-signal circuits [14]–[17], [22], [37], and they can be used for the optimization of Σ∆Ms. Optimization-based synthesis methodology is widely used for the automatic sizing of circuits and systems, in order to find the best set of design parameters that meet the required specifications of a given circuit. To this end, the well-known top-down/bottom-up design procedure divides a given system – a Σ∆M in this case – into several hierarchy levels, so that at each abstraction level, the design process consists of transmitting or mapping the specifications in a hierarchical way: from the top level to the bottom level. Thus, at system level, Σ∆M specifications, Bwand ENOB, are mapped onto bulding-block specifications, i.e. the electrical requirements of amplifiers, transconductors, comparators, switches, etc. At this design stage, the design variables of the sizing problem are the finite DC gain, GB, SR, etc. Once these design variables are found, the sizing process is moved to the lower abstraction level, i.e. the electrical level, in which, after an appropriate topology has been selected for every Σ∆M subcircuit, transistor sizes and bias currents are obtained [38]. Fig. 2(a) shows the conventional flow diagram of the optimization-based high-level synthesis of Σ∆Ms based on the combination of behavioral simulation (SIMSIDES in this example [39]) as performance evaluator, and an optimizer to explore the design space and find the optimum set of buildingblock electrical parameters to get the optimum modulator performance. The starting point is the modulator architecture. Here, the design parameters are the building-block specifications; that is, the nonideal parameters used to model the main error mechanisms that affect the performance of Σ∆Ms and define the electrical specifications of its subcircuits: integrators, comparators, DAC elements, and so on, which are generically denoted in this paper as ¯. Considering arbitrary initial conditions in Fig. 2(a), a set of perturbations of the design parameters is generated by the optimizer. With the new design parameters, a new set of simulations is carried out to evaluate the modulator performance and the process is repeated in an iterative way until a cost function is optimized. The type and value of such perturbations, as well as the iteration acceptance or rejection criteria, depend on the type of optimization method, i.e. evolutionary algorithms, genetic, simulated annealing, etc [26], [40]. Some authors propose using ANNs in an optimizationbased synthesis methodology. In some works, the ANN has been trained to replace the simulator, while other approaches consider ANNs as the optimization engine [14]. In the latter case, the ANN is trained to size a given system for a set of specifications. Thus, the ANN should be trained with sized solutions known from prior optimized designs. Once the ANN is trained, it is able to automate the sizing process and generate optimum sizing solutions for additional sets of specifications which were not considered in the training dataset. This methodology, proposed in [14] for arbitrary analog circuits, is illustrated in Fig. 2(b) for the optimization of Σ∆Ms. As conceptually depicted in Fig. 2(b), the data used to train the ANN is comprised of a set of data pairs denoted as {¯, ¯ Γ}, Optimization Optimum Design Found ? Design Parameter Update Sigma-Delta Architecture NO Design Parameter (Definition & Ranges) Performance Metric Evaluation Simulation (SIMSIDES) END YES ¯✏±¯✏ {SNR, DR, THD,…} (a) ¯✏ Optimum Design Found ? Sigma-Delta Architecture NO Design Parameter (Definition & Ranges) Performance Metric Evaluation Simulation (SIMSIDES) END YES ¯✏±¯✏ {SNR, DR, THD,…} (b) Training Trained ANN ¯✏ Opt. Param. Update ¯ ±¯  { , } ¯✏ ¯  { } Optimun Fig. 2. Using ANNs to optimize the high-level design of Σ∆Ms: (a) Conventional synthesis methodology, (b) ANN-based synthesis methodology. where ¯ Γstands for a vector of performance metrics, i.e. SNR, Bw, THD, etc. In order to train the ANN, an input dataset {¯, ¯ Γ}is generated from a database of previous simulations of Σ∆Ms which led to useful designs1. This dataset can be augmented to increase the number of input data to train the ANNs, so that they can learn to find optimum designs outside the train set distributions. Once the ANN is trained, it can be used to generate optimum designs, i.e. to provide an optimum case of ¯that satisfies a given set of specifications. To that end, the ANN-based optimizer is combined with a behavioral simulator (SIMSIDES) to explore the design space and to find the best design as illustrated in Fig. 2(b). ANNs can be implemented in many different ways, regardless it is used as an optimization algorithm to design Σ∆Ms (Fig. 2(b)) or as part of the circuit itself (Fig. 1(a)). In the latter case, it can be either synthesized in hardware, as an Field-Programmable Gate Array (FPGA) or as an on-chip dedicated module, or software embedded in a Digital Signal Processor (DSP). There are also diverse ways to connect artificial neurons, either in a feedforward or Recurrent NNs (RNNs), or including hidden layers of neurons – referred to as Deep NNs or DNNs. Depending on the degree of connectivity of their neurons, ANNs can be divided into fully-connected ANNs – where each neuron in a given layer is connected to 1Typically, thousands of simulations are needed to generate the training dataset. This may take several hours depending on the computing resources. However, once this dataset is generated, it can be applied to a number of different synthesis problems, where the training and optimization process may take a few minutes, depending on the Σ∆M architecture and specifications. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – II: EXPRESS BRIEFS 4 Inverter-based OTAs c0 z-1 c1 z-1 c2 z-1 cN FIR-based DACs N-bit Register CLK Vtune 0 1 1 1 0 Time-based Quantization Hybrid Active/Passive Filters B-bit ADC H(f,¯✏) B-bit DAC + - - + Z vin+ vbias vinio- io+ + - + - + - gmu io vin Fig. 3. Scaling-friendly analog circuit techniques for mostly-digital Σ∆Ms. all neurons of the remaining layers – or Convolutional Neural Networks (CNNs), where each neuron is connected to a given subgroup of neighboring layers2. IV. DIGITAL-FRIENDLY PROGRAMMABLE ANALOG CIRCUITS FOR AI-MANAGED Σ∆MS Highly-reconfigurable analog circuits are needed to increase the programmability of Σ∆M building blocks, so that their operation can be managed by an ANN module. Digital-assisted, scaling-friendly analog circuits – some of them highlighted in Fig. 3 – are suited for AI-enhanced Σ∆Ms [41]. Inverter-based and VCO-based Operational Transconductance Amplifiers (OTAs): A good candidate is the use of CMOS inverters for the realization of OTAs, as originally proposed by Nauta [42]. Since the first inverter-based OTAs, there has been an increasing interest to apply this technique for the implementation of filters and ADCs, due to their better efficiency for the required gain performance and bandwidth [36]. More and more digital circuits are being embedded to improve the performance of analog circuits, by means of calibration, tuning, etc, that try to alleviate the limitations of nanometer CMOS analog circuits [43]. In spite of their potential benefits, inverter-based OTAs offer lower performance metrics such as robustness over PVT variations, impact of circuit parasitics, limited DC gain, etc. Some authors have proposed improved versions of inverted-based OTAs [43]–[48] and their use is becoming more and more popular in Σ∆Ms [33], [34], [49]. Other authors suggest the use of Voltage-Controlled Oscillators (VCOs) to implement OTAs, as an alternative to increase the gain of inverter-based OTAs for lower supply voltages, and to implement highly-programmable Σ∆Ms [50]. Hybrid Active/Passive Σ∆Ms: Another approach to reduce the number of power-hungry circuits consists of replacing some active building blocks with passive circuit elements. This has a number of drawbacks such as the loop-filter gain loss, increased thermal noise and a higher sensitivity to technology process variations and parasitics. In spite of these limitations, passive RC networks are becoming a popular circuit solution for the implementation of Σ∆Ms in diverse applications 2A detailed explanation of ANNs is beyond the scope of this brief and the interested reader can find a large number of references in literature [7]. [51]–[56]. Indeed, hybrid active/passive circuits are suited for reconfigurable loop filters such as Time-Interleaved (TI) or N-path filters [57] made up of switchable RC networks [58]. Time-based Quantization: Another scaling-friendly approach is based on translating the quantized information from the amplitude domain to the time domain by means of a voltage-to-frequency conversion. The principle of operation behind this approach, proposed in [59], relies on the use of a ring oscillator to count the number of edges within a given time period as conceptually depicted in Fig. 3. The result is directly related to the input signal, thus obtaining a digital representation of the amplitude. In addition to their higher speed and lower supply voltages, VCO-based quantizers provide an implicit first-order noise-shaping filter [15], [31], [32], [59]–[71]. However, it is limited in practice by the nonlinearity of the voltage-to-frequency conversion, requiring the use of either calibration or linearization techniques [65]– [67], [72], [73]. An alternative to VCO-based quantizers consists of using pulse-width modulation (PWM) [74], [75] and a Time-to-Digital Converter (TDC) that generates a timequantized representation of the signal [76]–[80]. The so-called Gated Ring Oscillators (GROs) have been successfully applied attenuate the nonlinearity of VCOs and be combined with active-RC integrators, thus benefiting from both amplitude- and time-based circuit techniques [81]. Finite Impulse Response (FIR) Feedback DACs: Regardless the Σ∆M quantizer is realized either in amplitude or time domain, by increasing the number of bits yield to an increase of the circuit complexity and nonlinearity of the feedback DAC. These problems can be palliated by using a DAC with a FIR filter [51], [82]–[84]. The idea – originally proposed in [85] and conceptually illustrated in Fig. 3 – is to feedback a filtered version of the single-bit quantization output, such that due to the high-frequency attenuation of the FIR filter, the DAC output, is a multi-level waveform. This allows to achieve the low-jitter sensitivity and high linearity of a multibit Σ∆M, while keeping the simplicity and robustness of single-bit Σ∆Ms [84], [86]. The combination of TI topologies and FIR DACs is an alternative to implement GHz-range Σ∆Ms [87], [88]. Moreover, FIR DACs make it easier to digitally control Σ∆M specifications by mean of an ANN, as required in AI-assisted Σ∆Ms. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – II: EXPRESS BRIEFS 5 V. CASE STUDY: AI-MANAGED Σ∆MS FOR CR ADCS As a case study, let us consider the CT BP-Σ∆M shown in Fig. 4(a) intended for RF ADCs in CR systems. This is a communication paradigm that allows to make a more efficient use of the frequency spectrum, by dynamically modifying receiver specifications according to the information sensed from the electromagnetic environment. In this example, an AI module – made up of Long Short-Term Memory (LSTM) networks – is used to predict and to identify the least occupied frequency band [89], [90], so that the noise-shaping of the BP-Σ∆M is modified accordingly, in order to operate over the selected band. This feature can be realized by BP-Σ∆M ADCs with a widely tunable notch frequency, fn, while keeping the required resolution over the digitized band [41], [91]. The BP-Σ∆M of Fig. 4(a) is designed in 65-nm CMOS, and consists of a 4th-order loop filter made up of inverted-based Gm-LC resonators and a 4-bit quantization [92]. The loopfilter resonators are based on programmable inverter-based transconductors like those shown in Fig. 3, which are in turn made up of unitary circuit elements that can be connected or disconnected depending on the operation mode required for the digitizer. This way, the tuning of specifications can be managed by the AI module. Both system-level and circuitlevel reconfiguration techniques are considered to allow the modulator to digitize signals placed at several carrier frequencies, ranging from 450MHz to 950MHz, with a programmable 1.2/2GHz clock rate [92], [93]. As stated in Section IV, inverted-based unitary transconductors are simple and modular, thus increasing the flexibility and programmability of the RF ADC according to the information provided by the ANN engine. In order to adjust the values of the requested loop-filter coefficients with a higher accuracy, different values of the unitary transconductance are used, namely: gmu,1/2gmu. These values can be easily changed by properly scaling the value of the tail current, Ibias, of the unitary transconductors as well as the sizing. Another reconfigurable circuit strategy consists of programming the resonant frequency by using banks of switchable unitary capacitors, which are in turn digitally controlled in order to program the value of fnrequired for the BP CT-Σ∆M to work in each operation mode [26], [92]. The performance of the CT BP-Σ∆M can be adapted to the different operation modes with optimized power consumption, by adjusting the biasing of all building blocks by means of a programmable master current generator. One of the characteristics of highly programmable ADCs is the huge number of digital control signals required to control and program their operation. For instance, in a reconfigurable BP CT-Σ∆M like that shown in Fig. 4, almost 200 digital control signals are needed. Such a large number of digital signals are provided in practice by a serial-to-parallel register that collects a serial input data and transforms this data into a set of parallel control bits which program the operation of the ADC [26]. This way, the CT BP-Σ∆M can be digitally programmed in an easy way, by loading the required control configuration for each operation mode. In the case of AI-managed digitizers for CR end-devices, the serial input data contains the infor- Time Samples Ch1 Ch2 Ch3 Ch4 Ch5 Ch1 Ch4 Ch1 Ch2 Ch5 Ch2 Ch3 Ch4 BP-ΣΔM Output (c) DSP Rx#Filter (a) Rx#Filter Rx Filters & LNAs Channel Occupancy 4-bit ADC 4th-ord Gm-LC Filter FIR DAC ANN Engine LC + - + - + -gmu Decimator (b) Spectrum Sensing Circuit # Samples Selected Channel Fig. 4. AI-assisted BP-Σ∆Ms for CR systems: (a) Receiver (Rx) diagram, (b) Channel occupancy over time, (c) BP-Σ∆M Noise shaping tuning. mation sensed from the electromagnetic environment, which is provided by the ANN engine, as conceptually illustrated in Fig. 4(a). Fig. 4(b) shows the evolution of the occupancy signals of several channels. Every time the ANN engine selects a certain channel, control parameters of different building blocks in the CT BP-Σ∆M can be modified accordingly. This is illustrated in Fig. 4(c), that shows how the notch frequency of the BP CT-Σ∆M can be tuned according to the feedback provided by the LTSM-based ANN module. In order for the overall CR system to operate correctly, the granularity of the programmability of the Σ∆M-based ADC must be as fine as possible in order to give the AI engine more degrees of freedom to properly choose the best parameters to optimize the communication in the selected channel. VI. CONCLUSIONS The performance of Σ∆M ADCs can be improved by the action of AI algorithms implemented as ANNs. These engines can be used as an enhancement building block to manage and control the operation of Σ∆Ms. They can also assist the synthesis methodology of Σ∆Ms by playing the role of an optimizer to find out the best sizing solution in a top-down design process. The practical implementation of these AI- assisted techniques would impose a number of design tradeoffs which involves reconfiguration techniques at both circuit and system level, as well as new design methods and CAD tools. Some of them have been overviewed in this tutorial brief, while many others are still open to research. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – II: EXPRESS BRIEFS 6 REFERENCES [1] T. M. Siebel, Digital Transformation: Survive and Thrive in an Era of Mass Extinction. RosettaBooks, 2019. [2] M. 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